MOSFETs Target the Major Efficiency Losses in DC/DC Converters

Von Europäische Herausgeber

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The silicon MOSFET has become a key component in the design of DC/DC converters, providing the high-speed switching and current-handling capability needed to implement high-efficiency, pulse-width-modulation-based control strategies. The drive towards higher efficiency is placing more intense demands on MOSFETs, particularly in designs that have constraints on size, reducing the amount of space that can be given over to heatsinks and other cooling assistance.

The trends are pushing towards the use of MOSFETs that offer reduced Rds(on), as well as offering low switching losses through good charge-storage characteristics. This article will examine a number of the key parameters for MOSFETs in typical DC/DC converter applications.

The metal-oxide semiconductor field-effect transistor (MOSFET) has become a key feature of power-conversion circuits. Its low-charge storage compared to bipolar circuits has made it the component of choice for handling the high-power functions in switched-mode DC/DC converters.

The typical DC/DC converter employs two MOSFETs. One is the control or high-side FET, marked as Q1 in Figure 1. The other is the synchronous or low-side FET, which is marked as Q2 in Figure 1. The name for the low-side FET comes from the fact that the transistor connects the supply rail to ground. The high-side FET, conversely, connects the input and output supply rails.

Typical synchronous DC/DC converter

Figure 1: The architecture of a typical synchronous DC/DC converter.

The high- and low-side FETs are synchronized, which gives the switching converter its commonly used name of synchronous rectifier. Only one switch can be open at any one time and the controller will generally organize switching events to prevent overlap in switching between the two transistors. One transistor will be switched off before the other is allowed to turn on. This behavior prevents losses caused by cross-conduction.

As well as the nominal maximum power that the DC/DC converter can deliver, the two MOSFETs need to handle voltage spikes caused by parasitic inductances and a current level equal to the maximum output current, plus 50 percent of the ripple current. Losses from the two transistors are important. Not only will static losses from the on-resistance through the transistor cause lower efficiency, but so will losses incurred during switching. The switching losses are especially important in DC/DC architectures that employ hard switching; this is where the transistor is exposed to non-zero voltage and current during switching events.

Hard switching tends to increase device stress, although this can be mitigated through the use of snubber circuits. The trend towards higher switching frequencies, with the aim of reducing electromagnetic interference and the size of the passive components needed by converters, has resulted in a shift away from hard-switching techniques. Many designers have gravitated towards soft switching, in which the state of the transistor is only allowed to change when either voltage or current are zero.

Soft-switching techniques take advantage of the resonant properties of the passive circuit elements in the DC/DC converter, the inductors and capacitors act to form a tank circuit with characteristic resonances. Designs have gone through a number of optimizations to overcome problems of high peak voltage and current values that are common to simpler zero-voltage or zero-current switching techniques. In these designs, the resonances are allowed to exhibit themselves just before switching events, allowing switching under zero-voltage or zero-current conditions using conventional pulse width modulation (PWM) switching algorithms.

Thanks to the use of soft-switching techniques, the stresses that transistors have to endure in a DC/DC converter have reduced, providing designers with the opportunity to trade-off factors such as breakdown voltage for better electrical performance in the operating region, such as on-resistance.

A number of factors contribute to discrete transistor on-resistance, and their weighting tends to change with the MOSFET requirements. For example, high-voltage MOSFETs see a much higher contribution to Rds(on) from doping in the epitaxial layers than those rated for lower voltages, which are typically used in lower-power and mobile systems. Increased doping levels are often used in high-voltage devices to increase the breakdown voltage, but this has the side effect of reducing conductivity. For low-voltage devices, the primary contribution to on-resistance comes from channel doping, with the metallization needed to pass signals within the device, as well as the parasitic JFET region and the epitaxial layer providing significant contributions.

One way in which manufacturers reduce Rds(on) is to split the MOSFET into numerous smaller devices that operate in parallel. Each miniature transistor forms a ‘cell’, often hexagonally packed to maximize density on the die. An individual die can contain thousands of such cells.

Another change from logic or analog transistor design often used in devices that are architected for low Rds(on), is the use of vertical device structures. The design provides a path for current flow that is less prone to the parasitics that reduce the performance of standard planar devices. In these architectures, the transistor is rotated so the current flow through the channel is vertical rather than in the plane of the silicon wafer. Typically, the drain is formed on the bottom surface of the wafer and provides a shorter distance for current to flow, which helps reduce on-resistance and increase converter efficiency.

A number of vendors have used a V-shaped groove to push the gate contact into the die. The source is effectively doubled in size. Two source regions lie on either side of the groove, making it possible to deliver a larger amount of current from the source to the drain. One issue with the VMOS structure is that high electric fields can develop at the point of the V. So manufacturers altered the shape to resemble a U by forming a trench with a flattened bottom in the surface of the die. Take, for example, the TrenchMOS process used by NXP Semiconductors’ PSMN1R2 logic-level voltage power transistors, among others. The trench is filled with polysilicon to form a gate electrode that reaches into the substrate. As with VMOS, the source electrode is wrapped around the gate. In an n-channel device, carriers flow through a thin n-doped epitaxial region to the n+-doped drain.

Typical trench-process MOSFET

Figure 2: Cross-section of a typical trench-process MOSFET.

A device such as the PSMN1R2-25YL can support drain-source voltages up to 25 V, suiting it for use in DC/DC converters that operate close to normal logic levels, and currents as high as 100 A. The use of the TrenchMOS process results in low Rds(on) and gate charge. The on-resistance is less than 2 mΩ, even at junction temperatures close to the qualified operating limit of 150°C when used in its PowerSO8-compatible LFPAK package. Gate charge is 105 nC at a gate-source voltage of 10 V.

The high- and low-side transistors within a DC/DC converter will generally have different requirements. In many cases, particularly with point-of-load (POL) applications that are now commonplace in electronic systems design, the input voltage will be higher than the output. The high-side device will have a short PWM duty cycle under most circumstances. As a result, switching losses will be more important than static losses.

To reduce switching losses, the transistor should have a low gate resistance (Rg) and gate inductance (Lg), which will reduce the switching time constant and therefore minimize the time it takes for the device to switch states. There should also be a low gate-drain capacitance to reduce the length of voltage transients, and a small gate-source capacitance to keep current transients short. These two capacitances are caused by overlap of the source and drain regions, and the polysilicon gate electrode above, which is separated from the source, channel, and drain by a dielectric material.

There is also a contribution from parasitic transistors that form between the source and the substrate silicon below the channel region, and also between the drain and the substrate.

This tends to lead to a small gate-charge figure. However, with MOSFETs, a low gate charge is generally accompanied by Rds(on). The trade-off between these values has led to the use of the figure of merit (FOM) for MOSFETs, which is the product of Rds(on) and gate charge. For a given process technology, the FOM will remain approximately constant, but gate charge and on-resistance can be shifted to suit a given application.

STMicroelectronics’ STripFET™ family of devices offer Rds(on) values down to 1.55 mΩ at 10 V against a gate charge of under 50 nC. The logic-level gate STD30, conversely offers a higher on-resistance of 25 mΩ, but with a gate charge of just 18 nC.

For the low-side transistor in a synchronous DC/DC converter, the PWM cycle will generally be longer than that of the high side, so the conduction losses, caused by on-resistance, will generally be the primary concern. Although, its switching losses still have an impact, particularly at high frequencies of operation.

Because manufacturers have focused attention on the FOM performance of their devices over the past decade, other sources of inefficiency have become more prominent. For example, parasitic inductances in the package can lead to wasted energy, which led to the development of packages such as the PowerSO8 and later QFN.

International Rectifier developed its DirectFET packaging to fit an SO8 footprint but provide better electrical properties. Used in devices such as the IRF6337, the package uses a specially-designed passivation technology to allow the die to be attached almost directly to the PCB for low resistance and inductance, without the risk of solder shorting between the gate and source contacts. Die-free resistance compared to that of a conventional SO8 was reduced by more than 80 percent using the DirectFET package.

The 30 V IRF6337, which has logic-level gate control, offers an Rds(on) of 5.7 mΩ at 10 V with a total gate charge of 11 nC. The device takes advantage of another technique that manufacturers have used to improve the performance of power MOSFETs in low-side switches. This is to provide a second path for current to flow through the die, by integrating a Schottky diode. In general, a Schottky diode recovers more quickly than a MOSFET. This is a helpful attribute during the dead time as it prevents the body diode within the MOSFET from becoming active and storing charge. Reducing this body diode charge can yield efficiency improvements of up to 2 percent. The IRF6337 has a reverse recovery charge of 20 nC and reverse recovery time of less than 20 ns.

Vishay Siliconix’ SkyFET power MOSFETs provide integrated Schottky diodes. One example is the 30 V Si7772DP, which can deal with current pulses up to 50 A. The device offers an Rds(on) of 10 mΩ against a gate charge of less than 30 nC. The body-diode recovery time is typically 17 ns with a reverse recovery charge of less than 15 nC and a reverse transfer capacitance of 77 pF.

Diodes Inc. has also developed a range of diode-integrated MOSFETs for DC/DC converters and similar applications. Devices in the SiMFET family support logic-level gate control with drain-to-source voltages of up to 30 V. The on-resistance of the DMG4710SSS is 12.5 mΩ at 10 V with a gate charge of 43 nC. The reverse transfer capacitance for the device is 136 pF.

On Semiconductor has cut the Rds(on) of its NTMFS4898 30 V MOSFET to just 3 mΩ, combined with a gate charge of approximately 50 nC at 10 V, and coupled the transistor with an integrated Schottky diode to provide a reverse recovery charge of 17.3 nC and reverse recovery time of 26.7 ns.

A combination of process improvements and the addition of helper devices such as Schottky diodes, have given the MOSFET extremely-low values for key parameters such as on-resistance and gate charge. Further improvements are gradually reducing the impact of the package on performance, as well as second-order parameters that are now beginning to become significant in circuit design.

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