STM6519 Datasheet by STMicroelectronics

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This is information on a product in full production.
June 2016 DocID022111 Rev 7 1/23
STM6519
Single-pin, push button Smart Reset™
Datasheet - production data
Features
Operating voltage range 2 V to 5.5 V
Low supply current 1 μA
Integrated test mode
Single Smart Reset™ push-button input with
fixed extended reset setup delay (tSRC) from
0.5 s to 10 s in 0.5 s steps (typ.), option with
internal input pull-up resistor
Push-button controlled reset pulse duration
Option 1: fully push-button controlled, no fixed
or minimum pulse width guaranteed
Option 2: defined output reset pulse duration
(tREC), factory-programmed
Single reset output
Active-low or active-high
Push-pull or open drain with optional pull-up
resistor
Fixed Smart Reset input logic voltage levels
Operating temperature: -40 °C to 85 °C
UDFN6 package 1.00 mm x 1.45 mm
ECOPACK®2
(RoHS compliant, Halogen-Free)
Applications
Mobile phones, smartphones, PDAs
e-books
MP3 players
Games
Portable navigation devices
Any application that requires delayed reset
push-button response for improved system
stability
UDFN6 1.00 mm x 1.45 mm
www.st.com
RST
Contents STM6519
2/23 DocID022111 Rev 7
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Smart Reset input (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6 RST output undervoltage behavior (for open-drain option) . . . . . . . . . . . . 8
4 Typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.1 UDFN6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.2 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DocID022111 Rev 7 3/23
STM6519 List of tables
3
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. UDFN6 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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List of figures STM6519
4/23 DocID022111 Rev 7
List of figures
Figure 1. STM6519 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. UDFN6 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. STM6519 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Typical application diagram - input, output and STM6519 device in one voltage domain . . 9
Figure 5. Typical application diagram - STM6519 device in a different voltage domain than input
and output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Typical application diagram in different voltage domains - SR input in VBAT domain like
VCC totally disables the test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. RST output without tREC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. RST output with tREC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Supply current (ICC) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Smart Reset delay (tSRC) vs. temperature (TA), tSRC = 4.0 s (typ.) . . . . . . . . . . . . . . . . . . 12
Figure 11. Test mode entry voltage (VTEST) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Initial test mode time (tSRC-INI) vs. temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. UDFN6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. UDFN6 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID022111 Rev 7 5/23
STM6519 Description
22
1 Description
The Smart ResetTM devices provide a useful feature which ensures that inadvertent short
reset push-button closures do not cause system resets. This is done by implementing an
extended Smart Reset input delay time (tSRC), which ensures a safe reset and eliminates
the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to distinguish
between a software generated interrupt and a hard system reset. When the input push-
button is connected to the microcontroller interrupt input, and is closed for a short time, the
processor can only be interrupted. If the system still does not respond properly, continuing
to keep the push-buttons closed for the extended setup time tSRC causes a hard reset of the
processor through the reset output.
The STM6519 has one Smart Reset input (SR) with preset delayed Smart Reset setup time
(tSRC). The reset output (RST) is asserted after the Smart Reset input is held active for the
selected tSRC delay time. The RST output remains asserted either until the SR input goes to
inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output
reset pulse duration is fixed for tREC (i.e. factory-programmed). The device fully operates
over a broad VCC range from 2.0 V to 5.5 V.
1.1 Test mode
After pulling SR up to VTEST (VCC + 1.4 V) or above, the counter starts to count the initial
shortened tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for
tREC (if tREC option is used) or stays low as long as overvoltage on SR is detected (if tREC
option is not used). This is feedback, and the user only knows that the device is locked in
test mode. Each time the SR input is connected to ground in test mode, a shortened
tSRC-SHORT (tSRC/128) is used instead of regular tSRC (0.5 s - 10 s). In this way the device
can be quickly tested without repeating test mode triggering. Return to normal mode is
possible by performing a new startup of the device (i.e. VCC goes to 0 V and back to its
original state).
The advantages of this solution are its high glitch immunity, user feedback regarding entry
into test mode, and testability within the full VCC range.
Description STM6519
6/23 DocID022111 Rev 7
1.2 Logic diagram
Figure 1. STM6519 logic diagram
1.3 Pin connections
Figure 2. UDFN6 pin connections (top view)
1. Not connected (not bonded); should be connected to VSS.
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DocID022111 Rev 7 7/23
STM6519 Device overview
22
2 Device overview
Figure 3. STM6519 block diagram
Table 1. Signal names
Pin number Name Type Description
1RST Output Reset output, active-low, open drain.
2V
SS Supply ground Ground
3SR Input Smart Reset input, active-low.
4V
CC Supply voltage
Positive supply voltage for the device. A 0.1 µF decoupling
ceramic capacitor is recommended to be connected between VCC
and VSS pins.
5 NC - Not connected (not bonded); should be connected to VSS.
6 NC - Not connected (not bonded); should be connected to VSS.
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Pin descriptions STM6519
8/23 DocID022111 Rev 7
3 Pin descriptions
3.1 Power supply (VCC)
This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling
capacitor is recommended to be connected between the VCC and VSS pins, as close to the
STM6519 device as possible.
3.2 Power-up sequence
In normal mode, if different input side (SR) and VCC voltage domains are used, power-on
sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode
entry: there should not be logic high present on the SR input before the VCC power-up.
However VCC and V(SR) rising at the same time is OK (e.g. if both are in the same voltage
domain), the device will then safely start into normal operating mode, with RST output
inactive (in High-Z mode for open-drain option).
3.3 Ground (VSS)
This is the ground pin for the device.
3.4 Smart Reset input (SR)
Push-button Smart Reset input, active-low with optional pull-up resistor. SR input needs to
be asserted for at least tSRC to assert the reset output (RST).
By connecting a voltage higher than VCC + 1.4 V to the SR input the device enters test mode
(see Section 1: Description on page 5 for more information).
3.5 Reset output (RST)
RST is active-low or active-high, open drain or push-pull reset output with optional internal
pull-up resistor.
Output reset pulse width is optional as follows:
Neither fixed nor minimum output reset pulse duration (releasing the push-button while
reset output is active, causes the output to de-assert)
Fixed, factory-programmed output reset pulse duration for tREC independent on Smart
Reset input state.
3.6 RST output undervoltage behavior (for open-drain option)
High-Z on RST output below the specified operating voltage range is guaranteed at VCC
power-on or in case that valid VCC dropped while the device was idle, i.e. while both output
and input were inactive.
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DocID022111 Rev 7 9/23
STM6519 Typical application diagrams
22
4 Typical application diagrams
Figure 4. Typical application diagram - input, output and STM6519 device in one
voltage domain
Figure 5. Typical application diagram - STM6519 device in a different voltage domain
than input and output
1. Open-drain RST output type and fixed SR input logic threshold allows to use the device in different voltage
domains. To prevent entering test mode by creating a condition V(SR) > VCC + 1.1 V typ., VCC should be
powered up before or together with voltage on the SR input.
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Typical application diagrams STM6519
10/23 DocID022111 Rev 7
Figure 6. Typical application diagram in different voltage domains - SR input in VBAT
domain like VCC totally disables the test mode
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DocID022111 Rev 7 11/23
STM6519 Timing diagrams
22
5 Timing diagrams
Figure 7. RST output without tREC option
1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating
a condition V(SR) > VCC +1.1 V typ.
Figure 8. RST output with tREC option
1. VCC should be powered up before or together with voltage on the SR input to prevent entering test mode by creating
a condition V(SR) > VCC +1.1 V typ.
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Typical operating characteristics STM6519
12/23 DocID022111 Rev 7
6 Typical operating characteristics
Figure 9. Supply current (ICC) vs. temperature (TA)
Figure 10. Smart Reset delay (tSRC) vs. temperature (TA), tSRC = 4.0 s (typ.)
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DocID022111 Rev 7 13/23
STM6519 Typical operating characteristics
22
Figure 11. Test mode entry voltage (VTEST) vs. temperature (TA)
Figure 12. Initial test mode time (tSRC-INI) vs. temperature (TA)
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Maximum ratings STM6519
14/23 DocID022111 Rev 7
7 Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 3: Operating and
measurement conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics™ SURE program and other relevant quality documents.
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
TSTG Storage temperature (VCC off) -55 to 150 °C
TSLD(1)
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Lead solder temperature for 10 seconds 260 °C
VIO Input or output voltage -0.3 to 5.5 V
VCC Supply voltage -0.3 to 7 V
ESD
VHBM
Electrostatic discharge protection, human body model (JESD22-
A114-B level 2) 2kV
VRCDM Electrostatic discharge protection, charged device model, all pins 1 kV
VMM
Electrostatic discharge protection, machine model, all pins
(JESD22-A115-A level A) 200 V
Latch-up (VCC pin, SR reset input pin) EIA/JESD78
DocID022111 Rev 7 15/23
STM6519 DC and AC parameters
22
8 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in Table 4: DC and AC characteristics are
derived from tests performed under the measurement conditions summarized in Table 3:
Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 3. Operating and measurement conditions
Symbol Parameter Value Unit
VCC Supply voltage 2.0 to 5.5 V
TAAmbient operating temperature -40 to 85 °C
tR, tFInput rise and fall times
5ns
Input pulse voltages 0.2 to 0.8 VCC V
Input and output timing reference voltages 0.3 to 0.7 VCC V
DC and AC parameters STM6519
16/23 DocID022111 Rev 7
Table 4. DC and AC characteristics
Symbol Parameter Test conditions(1) Min. Typ.(2) Max. Unit
VCC Supply voltage 2.0 5.5 V
ICC Supply current SR = VCC, tREC and tSRC
counter is not running 0.4 1.0 µA
VOL Reset output voltage low
VCC
4.5 V, sinking 3.2 mA 0.3 V
VCC
3.3 V, sinking 2.5 mA 0.3 V
VCC
2.0 V, sinking 1 mA 0.3 V
tREC
Reset timeout delay,
factory-programmed (device option)
0.85 1.28 1.71 ms
66 100 134 ms
140 210 280 ms
240 360 480 ms
RPUO
Internal output pull-up
resistor on RST (device option) 65 kΩ
ILO Output leakage current
VRST = 5.5 V, open drain
device option without output
pull-up resistor
-0.1 0.1 µA
Smart Reset
tSRC Smart Reset delay
TA = -40 to +85 °C 0.8 x tSRC tSRC(3) 1.2 x tSRC s
TA = 25 °C 0.9 x tSRC 1.1 x tSRC
VIL SR input voltage low VSS-0.3 0.3 V
VIH SR input voltage high 0.85 5.5 V
RPUI
Internal input pull-up
resistor on SR (device option) 65 kΩ
ILEAK SR input leakage current device option without input
pull-up resistor -0.1 0.1 µA
Input glitch immunity tSRC s
Test mode
VTEST Test mode entry voltage VCC +0.9 VCC + 1.1 VCC + 1.4 V
tSRC-INI Initial test mode time 28 42 56 ms
tSRC-SHORT
Shortened Smart Reset
delay tSRC / 128 ms
1. Valid for ambient operating temperature TA = -40 to 85 °C, VCC = 2.0 to 5.5 V.
2. Typical values are at 25 °C and VCC = 3.3 V unless otherwise noted.
3. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps.
DocID022111 Rev 7 17/23
STM6519 Package information
22
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
9.1 UDFN6 package information
Figure 13. UDFN6 package outline
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Package information STM6519
18/23 DocID022111 Rev 7
Figure 14. UDFN6 recommended footprint
Table 5. UDFN6 mechanical data
Symbol
Dimensions
Note(1)
1. Package outline exclusive of any mold flashes dimensions and metal burrs.
(mm) (inches)
Min. Typ. Max. Min. Typ. Max.
A0.50 0.55 0.60 0.0197 0.0217 0.0236
A1 0.00 0.02 0.05 0.000 0.0008 0.0020
b0.18 0.25 0.30 0.0071 0.0098 0.0118
D1.40 1.45 1.50 0.0551 0.0571 0.0591
E0.95 1.00 1.05 0.0374 0.0394 0.0413
e0.45 0.50 0.55 0.0177 0.0197 0.0217
k0.20 0.0079
L0.30 0.35 0.40 0.0118 0.0138 0.0157
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DocID022111 Rev 7 19/23
STM6519 Package information
22
9.2 Tape and reel information
Figure 15. Carrier tape
1. 10-sprocket hole pitch cumulative tolerance ±0.20.
Figure 16. Pin 1 orientation
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Part numbering STM6519
20/23 DocID022111 Rev 7
10 Part numbering
Table 6. Ordering information scheme
Example: STM6519 A H A R UB 6 F
Device type
STM6519
Reset (VCC monitoring threshold) voltage VRST
A = no VCC monitoring feature
Smart Reset setup delay (tSRC)(1)
1. Smart Reset delay (tSRC) is available from 0.5 s to 10 s in 0.5 s steps (typ.). Minimum order quantities may apply. Contact
local sales office for availability.
C = factory programmable tSRC = 1.5 s (typ.)
H = factory programmable tSRC = 4.0 s (typ.)
L = factory programmable tSRC = 6.0 s (typ.)
P = factory programmable tSRC = 7.5 s (typ.)
U = factory programmable tSRC = 10.0 s (typ.)
Inputs, outputs type(2)
2. Push-pull reset output type also available (active-low or active-high). SR input and open drain reset output available with
optional pull-up resistor. Minimum order quantities may apply. Contact local sales office for availability.
A = active-low SR input with no pull-up,
active-low open drain RST output with no pull-up
B = active-low SR input with pull-up,
active-low open drain RST output with no pull-up
Reset timeout period (tREC)
A = factory programmable tREC = 210 ms (typ.)
B = factory programmable tREC = 360 ms (typ.)
E = factory programmable tREC = 1.28 ms (typ.)
F = factory programmable tREC = 100 ms (typ.)
R = push-button controlled (no defined tREC)
Package
UB = UDFN-6L
Temperature range
6 = -40 °C to 85 °C
Shipping method
F = tape and reel
DocID022111 Rev 7 21/23
STM6519 Package marking information
22
11 Package marking information
Figure 17. Package marking (top view)
Table 7. Package marking
Part number tSRC (s) Smart Reset
inputs(1)
1. AL = active-low.
Output
type(2)
2. OD = open drain, AL = active-low.
tREC
option(3)
3. No tREC = push-button controlled reset pulse width, any other value represents typical value of tREC.
Package Topmark
STM6519ACARUB6F 1.5 AL OD, AL No tREC UDFN6 CA
STM6519AHARUB6F 4.0 AL OD, AL No tREC UDFN6 HA
STM6519ALARUB6F 6.0 AL OD, AL No tREC UDFN6 LA
STM6519APAAUB6F 7.5 AL OD, AL 210 ms UDFN6 PB
STM6519APARUB6F 7.5 AL OD, AL No tREC UDFN6 PA
STM6519APBBUB6F 7.5 AL + pull-up OD, AL 360 ms UDFN6 PC
STM6519AUARUB6F 10.0 AL OD, AL No tREC UDFN6 UA
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Revision history STM6519
22/23 DocID022111 Rev 7
12 Revision history
Table 8. Document revision history
Date Revision Changes
12-Aug-2011 1 Initial release.
22-Sep-2011 2 Updated Figure 5, Table 4, Table 7 and Table 8.
07-Oct-2011 3 Removed label “Preliminary data”.
27-Oct-2011 4 Updated Figure 3 and Table 1.
13-Jun-2012 5 Updated Features, Table 4, title of Section 9.
17-Jan-2013 6
Moved Figure 4 below Table 1.
Added Section 3.2, Section 3.6, Figure 6 and Figure 7.
Updated title of Figure 5.
Updated Figure 8 and Figure 9 (added notes and minor
modifications).
29-Jun-2016 7 Updated datasheet title
Removed UDFN4 package from datasheet
DocID022111 Rev 7 23/23
STM6519
23
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