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This is information on a product in full production.
www.st.com
STN3NF06L
N-channel 60 V, 0.07 Ω typ., 4 A STripFET™ II
Power MOSFET in a SOT-223 package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code
RDS(on) max.
ID
STN3NF06L
60 V
0.1 Ω
4 A
Exceptional dv/dt capability
100% avalanche tested
Low threshold drive
Applications
Switching applications
Description
This Power MOSFET series realized with
STMicroelectronics unique STripFET™ process
is specifically designed to minimize input
capacitance and gate charge. It is therefore ideal
as a primary switch in advanced high-efficiency
isolated DC-DC converters for Telecom and
Computer applications. It is also suitable for any
application with low gate charge drive
requirements.
Table 1: Device summary
Order code
Marking
Package
Packing
STN3NF06L
3NF06L
SOT-223
Tape and reel
Contents
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Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 SOT-223 package information .......................................................... 9
5 Revision history ............................................................................ 11
STN3NF06L
Electrical ratings
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1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
60
V
VGS
Gate-source voltage
±16
V
ID(1)
Drain current (continuous) at Tc = 25 °C
4
A
ID
Drain current (continuous) at Tc = 100 °C
2.9
A
IDM(2)
Drain current (pulsed)
16
A
PTOT
Total dissipation at Tpcb = 25 °C
3.3
W
dv/dt (3)
Peak diode recovery voltage slope
10
V/ns
EAS(4)
Single pulse avalanche energy
200
mJ
Tj
Operating junction temperature range
- 55 to 150
°C
Tstg
Storage temperature range
Notes:
(1)Current limited by the package.
(2)Pulse width limited by safe operating area.
(3)ISD ≤ 3 A, di/dt ≤ 150 A/μs, VDD ≤ V(BR)DSS
(4)Starting Tj = 25 °C, ID = 4 A, VDD = 30 V
Table 3: Thermal data
Symbol
Parameter
Value
Unit
Rthj-pcb
Thermal resistance junction-pcb (1)
38
°C/W
Rthj-pcb
Thermal resistance junction-pcb(2)
100
°C/W
Notes:
(1)When Mounted on FR-4 board 1 inch2 pad, 2 oz. of Cu and t <10 s.
(2)When mounted on minimum recommended footprint.
Electrical characteristics
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2 Electrical characteristics
TC = 25 °C unless otherwise specified
Table 4: On/off-state
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V, ID = 250 μA
60
V
IDSS
Zero gate voltage drain
current
VGS = 0 V, VDS = 60 V
1
µA
VGS = 0 V, VDS = 60 V
TC = 125 °C(1)
10
µA
IGSS
Gate body leakage current
VDS = 0 V, VGS = ±16 V
±100
nA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
1
2.8
V
RDS(on)
Static drain-source
on-resistance
VGS= 10 V, ID= 1.5 A
0.07
0.10
VGS= 5 V, ID= 1.5 A
0.085
0.12
Notes:
(1)Defined by design, not subject to production test.
Table 5: Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Input capacitance
VDS =25 V, f=1 MHz, VGS=0 V
-
340
pF
Coss
Output capacitance
-
63
pF
Crss
Reverse transfer
capacitance
-
30
pF
Qg
Total gate charge
VDD = 48 V, ID = 3 A
VGS= 0 to 5 V
(see Figure 14: "Test circuit for
gate charge behavior")
-
7
9
nC
Qgs
Gate-source charge
-
1.5
nC
Qgd
Gate-drain charge
-
2.8
nC
Table 6: Switching times
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
VDD= 30 V, ID = 1.5 A,
RG = 4.7 Ω
VGS = 5 V
(see Figure 13: "Test circuit for
resistive load switching times"
and Figure 18: "Switching time
waveform")
-
9
-
ns
tr
Rise time
-
25
-
ns
td(off)
Turn-off delay time
-
20
-
ns
tf
Fall time
-
10
-
ns
STN3NF06L
Electrical characteristics
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Table 7: Source-drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSD(1)
Forward on voltage
ISD= 4 A, VGS=0 V
-
1.5
V
trr
Reverse recovery time
ISD= 4 A, di/dt = 100 A/μs,
VDD=25 V, Tj=150 °C
(see Figure 15: "Test circuit for
inductive load switching and
diode recovery times")
-
50
ns
Qrr
Reverse recovery
charge
-
88
nC
IRRM
Reverse recovery
current
-
3.5
A
Notes:
(1)Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
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2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Static drain-source on-resistance
Figure 7: Gate charge vs. gate-source voltage
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STN3NF06L
Electrical characteristics
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Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage vs
temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Source-drain diode forward characteristics
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Test circuits
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3 Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
004606771 4
STN3NF06L
Package information
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4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1 SOT-223 package information
Figure 19: SOT-223 package outline
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Package information
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Table 8: SOT-223 package mechanical data
Dim.
mm
Min.
Typ.
Max.
A
1.8
A1
0.02
0.1
B
0.6
0.7
0.85
B1
2.9
3
3.15
c
0.24
0.26
0.35
D
6.3
6.5
6.7
e
2.3
e1
4.6
E
3.3
3.5
3.7
H
6.7
7.0
7.3
V
10º
Figure 20: SOT-223 recommended footprint (dimensions are in mm)
STN3NF06L
Revision history
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5 Revision history
Table 9: Document revision history
Date
Revision
Changes
21-Jun-2004
5
Complete version.
04-Oct-2006
6
New template, no content change.
01-Feb-2007
7
Typo mistake on Table 2.
12-Jun-2008
8
Corrected marking on Table 1
03-Jul-2017
9
Modified internal schematic diagram on cover page.
Updated Section 4: "Package information".
Minor text changes.
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