LTC1344 Datasheet by Analog Devices Inc.

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LTC 1 344 L7 IT-EICILINOLOGY
1
LTC1344
Software-Selectable
Cable Terminator
Software-Selectable Cable Termination for:
RS232 (V.28)
RS423 (V.10)
RS422 (V.11)
RS485
RS449
EIA530
EIA530-A
V.35
V.36
X.21
Outputs Won’t Load the Line with Power Off
The LTC
®
1344 features six software-selectable
multiprotocol cable terminators. Each terminator can be
configured as an RS422 (V.11) 100 minimum differen-
tial load, V.35 T-network load or an open circuit for use
with RS232 (V.28) or RS423 (V.10) transceivers that
provide their own termination. When combined with the
LTC1343, the LTC1344 forms a complete software-select-
able multiprotocol serial port. A data bus latch feature
allows sharing of the select lines between multiple inter-
face ports.
The LTC1344 is available in a 24-lead SSOP.
Daisy-Chained Control Outputs
Data Networking
CSU and DSU
Data Routers
, LTC and LT are registered trademarks of Linear Technology Corporation.
D2
LTC1343
RTSDTRDSR DCDCTS RL
D1
D3D4
R1
R3
R4 R2
D2
LTC1343
LL
TXDSCTETXCRXCRXDTM
LL A (141)
TXD A (103)
TXD B
SCTE A (113)
SCTE B
RXC A (115)
RXC B
RXD A (104)
RXD B
RTS A (105)
RTS B
DTR A (108)
DTR B
CTS A (106)
CTS B
TM A (142)
SGND (102)
SHIELD (101)
18
21424111512179314192023622 810513 21 7 1625
1344 TA01
DB-25 CONNECTOR
LTC1344
D1
D3D4
R1
R3
R4 R2
TXC A (114)
TXC B
RL A (140)
DCD A (109)
DCD B
DSR A (107)
DSR B
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATION
U
flBSOLUTE flXI U flflTl G flflflflflflflflflflflfl UUUUUUUUUUUU L7 LJIJQ‘R
2
LTC1344
ABSOLUTE MAXIMUM RATINGS
W
WW
U
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
LTC1344CG
LTC1344IG
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
G PACKAGE
24-LEAD PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
M0
V
EE
R1C
R1B
R1A
R2A
R2B
R2C
R3A
R3B
R3C
GND
M1
M2
DCE/DTE
LATCH
R6B
R6A
R5A
R5B
R4A
R4B
V
CC
GND
TJMAX = 150°C, θJA = 100°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°.
VCC = 5V ±5%, VEE = –5V ±5%, TA = TMIN to TMAX (Notes 2, 3) unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supplies
I
CC
Supply Current All Digital Pins = GND or V
CC
200 700 µA
Terminator Pins
R
V.35
Differential Mode Impedance All Loads (Figure 1), – 2V V
CM
2V (Commercial) 90 103 110
Common Mode Impedance All Loads (Figure 2), – 2V V
CM
2V (Commercial) 135 153 165
All Loads (Figure 1), – 2V V
CM
2V (Industrial) 90 104 125
All Loads (Figure 2), – 2V V
CM
2V (Industrial) 130 153 170
R
V.11
Differential Mode Impedance All Loads (Figure 1), – 7V V
CM
7V (Commercial) 100 104
All Loads (Figure 1), V
CM
= 0V (Commercial) 100 104 110
All Loads (Figure 1), V
CM
= 0V (Industrial) 95 104 125
I
LEAK
High Impedance Leakage Current All Loads, –7V V
CM
7V (Commercial) ±1±50 µA
Logic Inputs
V
IH
Input High Voltage All Logic Input Pins 2V
V
IL
Input Low Voltage All Logic Input Pins 0.8 V
I
IN
Input Current All Logic Input Pins ±10 µA
Note 3: All typicals are given at V
CC
= 5V, V
EE
= –5V, T
A
= 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are reference to ground unless otherwise
specified.
(Note 1)
Positive Supply Voltage (V
CC
)................................... 7V
Negative Supply Voltage (V
EE
) ........................... 13.2V
Input Voltage (Logic Inputs) .... V
EE
– 0.3V to V
CC
+ 0.3V
Input Voltage (Load Inputs) .................................. ±18V
Operating Temperature Range
LTC1344C ............................................... 0°C to 70°C
LTC1344I........................................... 40°C to 85°C
Storage Temperature Range ................ 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
3
LTC1344
TYPICAL PERFORMANCE CHARACTERISTICS
UW
V.11 or V.35 Differential Mode
Impedance vs Common Mode
Voltage
TEMPERATURE (°C)
–40
DIFFERENTIAL MODE IMPEDANCE ()
20
1344 G01
110
105
–20 0 40
100
120
115
60 80 100
VCM = –7V
VCM = –2V
VCM = 0V
VCM = 7V
V
CC
VOLTAGE (V)
103
DIFFERENTIAL MODE IMPEDANCE ()
104
105
1344 G03
4.6 4.8 5.0 5.2 5.4
COMMON MODE VOLTAGE (V)
–8
DIFFERENTIAL MODE IMPEDANCE ()
108
6
1344 G02
106
104
100 –6 –4 –2 0 2 4 8
102
V.11 or V.35 Differential Mode
Impedance vs Temperature
V.35 Common Mode Impedance
vs Supply Voltage (VCC)
V.35 Common Mode Inpedance
vs Negative Supply Voltage (VEE)
V
CC
VOLTAGE (V)
151
COMMON MODE IMPEDANCE ()
152
153
1344 G07
4.6 4.8 5.0 5.2 5.4
V
EE
VOLTAGE (V)
5.4
COMMON MODE IMPEDANCE ()
153
154
4.6
1344 G08
152
151
150 5.2 5.0 4.8
Supply Current vs Temperature
TEMPERATURE (°C)
–50
SUPPLY CURRENT (µA)
1344 G09
310
290
270
250
230
210
190
170
150
–20 10 40 70 100
V.11 or V.35 Differential Mode
Impedance vs Negative Supply
Voltage (VEE)
TEMPERATURE (°C)
–40
COMMON MODE IMPEDANCE ()
20
1344 G05
155
150
–20 0 40
145
165
160
60 80 100
VCM = –2V
VCM = 2V
VCM = 0V
COMMON MODE VOLTAGE (V)
–2
COMMON MODE IMPEDANCE ()
154
156
2
1344 G06
152
150 –1 01
158
V.35 Common Mode Impedance
vs Temperature
V.35 Common Mode Impedance
vs Common Mode Voltage
V
EE
VOLTAGE (V)
103
DIFFERENTIAL MODE IMPEDANCE ()
104
105
1344 G04
5.4 5.2 –5.0 4.8 4.6
V.11 or V.35 Differential Mode
Impedance vs Supply Voltage
(VCC)
.||._0_,| Wth ve‘ Mod L7 LJIJQ‘R
4
LTC1344
TEST CIRCUITS
PIN FUNCTIONS
UUU
M0 (Pin 1): TTL Level Mode Select Input. The data on M0
is latched when LATCH is high.
V
EE
(Pin 2): Negative Supply Voltage Input. Can connect
directly to the LTC1343 V
EE
pin.
R1C (Pin 3): Load 1 Center Tap.
R1B (Pin 4): Load 1 Node B.
R1A (Pin 5): Load 1 Node A.
R2A (Pin 6): Load 2 Node A.
R2B (Pin 7): Load 2 Node B.
R2C (Pin 8): Load 2 Center Tap.
R3A (Pin 9): Load 3 Node A.
R2B (Pin 10): Load 2 Node B.
R3C (Pin 11): Load 3 Center Tap.
GND (Pin 12): Ground Connection for Load 1 to Load 3.
GND (Pin 13): Ground Connection for Load 4 to Load 6.
V
CC
(Pin 14): Positive Supply Input. 4.75V V
CC
5.25V.
R4B (Pin 15): Load 4 Node B.
R4A (Pin 16): Load 4 Node A.
R5B (Pin 17): Load 5 Node B.
R5A (Pin 18): Load 5 Node A.
R6A (Pin 19): Load 6 Node A.
R6B (Pin 20): Load 6 Node B.
LATCH (Pin 21): TTL Level Logic Signal Latch Input. When
it is low the input buffers on M0, M1, M2 and DCE/DTE are
transparent. When it is high the logic pins are latched into
their respective input buffers. The data latch allows the
select lines to be shared between multiple I/O ports.
DCE/DTE (Pin 22): TTL Level Mode Select Input. The DCE
mode is selected when it is high and DTE mode when low.
The data on DCE/DTE is latched when LATCH is high.
M2 (Pin 23): TTL Level Mode Select Input 1. The data on
M2 is latched when LATCH is high.
M1 (Pin 24): TTL Level Mode Select Input 2. The data on
M1 is latched when LATCH is high.
R1
51.5
R2
51.5
±7V OR ±2V
1344 F01
R3
124
S2
OFF
S1
ON
C
V
A
B
R1
51.5
R2
51.5
±2V
1344 F02
R3
124
S2
ON
S1
ON
C
V
A, B
Figure 1. Differential V.11 or V.35 Impedance Measurement Figure 2. V.35 Common Mode Impedance Measurement
E 3 E a W 24:: on m 3% L7 LELUEAB
5
LTC1344
LTC1344
MODE NAME DCE/DTE M2 M1 M0 R1 R2 R3 R4 R5 R6
V.10/RS423 X 000ZZZZZZ
RS530A 0 001ZZZV.11 V.11 V.11
1 001ZZZZV.11 V.11
Reserved 0 010ZZZV.11 V.11 V.11
1 0 1 0 V.11 V.11 V.11 Z Z Z
X.21 0 011ZZZV.11 V.11 V.11
1 011ZZZZV.11 V.11
V.35 0 1 0 0 V.35 V.35 Z V.35 V.35 V.35
1 1 0 0 V.35 V.35 V.35 Z V.35 V.35
RS530/RS449/V.36 0 101ZZZV.11 V.11 V.11
1 101ZZZZV.11 V.11
V.28/RS232 X 110ZZZZZZ
No Cable X 1 1 1 V.11 V.11 V.11 V.11 V.11 V.11
X = don’t care, 0 = logic low, 1 = logic high
ODE SELECTIO
W U
R1
51.5
R2
51.5
R3
124
S2
OFF
S1
ON
C
V.11 Mode V.35 Mode Hi-Z Mode
A
B
R1
51.5
R2
51.5
R3
124
S2
ON
S1
ON
C
A
B
R1
51.5
R2
51.5
1344 F03
R3
124
C
A
B
S2
OFF
S1
OFF
Figure 3. LTC1344 Modes
L7 LJIJQ‘R
6
LTC1344
APPLICATIONS INFORMATION
WUUU
Multiprotocol Cable Termination
One of the most difficult problems facing the designer of
a multiprotocol serial interface is how to allow the trans-
mitters and receivers for different electrical standards to
share connector pins. In some cases the transmitters and
receivers for each interface standard can be simply tied
together and the appropriate circuitry enabled. But the
biggest problem still remains: how to switch the various
cable terminations required by the different standards.
Traditional implementations have included switching re-
sistors with expensive relays or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head or separate termina-
tions are built on the board, and a custom cable routes the
signals to the appropriate termination. Switching the
terminations using FETs is difficult because the FETs must
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
The LTC1344 solves the cable termination switching prob-
lem via software control. The LTC1344 provides termina-
tion for the V.10 (RS423), V.11 (RS422), V.28 (RS232)
and V.35 electrical protocols.
V.10 (RS423) Termination
A typical V.10 unbalanced interface is shown in Figure 4.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' con-
nected to A and input B' connected to the signal return
ground C. The receiver’s ground C' is separate from the
signal return. Usually no cable termination is required for
V.10 interfaces but the receiver inputs must be compliant
with the impedance curve shown in Figure 5.
In V.10 mode, both switches S1 and S2 are turned off so
the only cable termination is the input impedance of the
V.10 receiver.
A
CABLE
TERMINATION
LOADGENERATOR
BALANCED
INTERCONNECTING
CABLE
RECEIVER
A
'
C
B
'
C
'
1344 F04
Figure 4. Typical V.10 Interface
V.11 (RS422) Termination
A typical V.11 balanced interface is shown in Figure 6. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.11 interface requires a different termination at the re-
ceiver end that has a minimum value of 100. The receiver
inputs must also be compliant with the impedance curve
shown in Figure 7.
In V.11 mode, switch S1 is turned on and S2 is turned off
so the cable is terminated with a 103 impedance.
Figure 5. V.10 Interface Using the LTC1344
Z
Z
Z
S2
OFF 124
LTC1344 V.10
RECEIVER
A
B
C
1344 F05
51.5
51.5
I
Z
–3V
3V 10V
–10V
3.25mA
3.25mA
V
Z
S1
OFF
L7 LELUEAB
7
LTC1344
APPLICATIONS INFORMATION
WUUU
Figure 6. Typical V.11 Interface
Z
Z
Z
S1
ON
S2
OFF 124
LTC1344 V.11
RECEIVER
A
B
C
1344 F07
51.5
51.5
I
Z
–3V
3V 10V
–10V
3.25mA
3.25mA
V
Z
Figure 7. V.11 Interface Using the LTC1344
V.28 (RS232) Termination
A typical V.28 unbalanced interface is shown in Figure 8.
A V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with inputs A' con-
nected to A, ground C' connected via the signal return
ground to C. The V.28 standard requires a 5k terminating
resistor to ground which is included in almost all compli-
ant receivers as shown in Figure 9. Because the termina-
tion is included in the receiver, both switches S1 and S2 in
the LTC1344 are turned off.
A
CABLE
TERMINATION
LOADGENERATOR
BALANCED
INTERCONNECTING
CABLE
RECEIVER
A'
CC'1344 F08
Figure 8. Typical V.28 Interface
S1
OFF
S2
OFF 124
LTC1344 V.28
RECEIVER
A
B
C
1344 F09
51.5
51.5
5k
Figure 9. V.28 Interface Using the LTC1344
V.35 Termination
A typical V.35 balanced interface is shown in Figure 10. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T-network termination at the
receiver end and the generator end. In V.35 mode both
switches S1 and S2 in the LTC1344 are turned on as
shown in Figure 11.
The differential impedance measured at the connector
must be 100 ±10 and the impedance between shorted
terminals A' and B' to ground C' must be 150 ±15. The
input impedance of the V.35 receiver is connected in
parallel with the T-network inside the LTC1344, which can
cause the overall impedance to fail the specification on the
A
CABLE
TERMINATION
LOADGENERATOR
BALANCED
INTERCONNECTING
CABLE
RECEIVER
A
'
BB
'
C
'
C
100
MIN
1344 F06
L7 LJIJQ‘R
8
LTC1344
and B to ground C must be 150 ±15. For the generator
termination, switches S1 and S2 are both on and the top
side of the center resistor is brought out to a pin so it can
be bypassed with an external capacitor to reduce common
mode noise as shown in Figure 12.
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the com-
mon mode energy to ground rather than down the cable.
The LATCH Pin
The LATCH pin (21) allows the select lines (M0, M1, M2
and DCE/DTE) to be shared with multiple LTC1344s, each
with its own LATCH signal. When the LATCH pin is held
low the select line input buffers are transparent. When the
LATCH pin is pulled high, the select line input buffers latch
the state of the Select pins so that changes on the select
lines are ignored until LATCH is pulled low again. If the
latch feature is not used, the LATCH pin should be tied to
ground.
APPLICATIONS INFORMATION
WUUU
A
CABLE
TERMINATION
LOADGENERATOR
BALANCED
INTERCONNECTING
CABLE
RECEIVER
A
'
50
50
125
B
C
B
'
C
'
1344 F10
125
50
50
Figure 10. Typical V.35 Interface
Z
Z
Z
S1
ON S2
ON 124
LTC1344 V.35
RECEIVER
A
B
C
1344 F11
51.5
51.5
IZ
–3V
3V 12V
–7V
0.8mA
1mA
VZ
Figure 11. V.35 Receiver Using the LTC1344
low side. However, all of Linear Technology’s V.35 receiv-
ers meet the RS485 input impedance specification as
shown in Figure 11, which insures compliance with the
V.35 specification when used with the LTC1344.
The generator differential impedance must be 50 to
150 and the impedance between shorted terminals A
S1
ON
S2
ON
124
LTC1344
V.35
DRIVER
A
B
C
1344 F12
51.5
51.5
C1
100pF
Figure 12. V.35 Driver Using the LTC1344
|| 'n'o'nMMM“ . H
9
LTC1344
TYPICAL APPLICATIONS N
U
Figure 13 shows a typical application for the LTC1344
using the LTC1343 mixed mode transceiver chip to gener-
ate the clock and data signals for a serial interface. The
LTC1344 V
EE
supply is generated from the LTC1343
charge pump and the select lines M0, M1, M2, DCE and
LATCH are shared by both chips. Each driver output and
receiver input is connected to one of the LTC1344 termi-
nation ports. Each electrical protocol can then be chosen
using the digital select lines.
LTC1343
38
1344 F13
3842
6
7
9
13
14
15
37
36
35
34
33
32
31
30
29
28
27
M0
M1
M2
DCE/DTE
LATCH
17
18
19
21
22
LTC1344
14
21
22
23
24
1
2
5V 5
3811 12 13
467910 16 15 18 17 19 20
DTE DCE
TXD
+
RXD
+
TXD
RXD
RXD
+
TXD
+
RXD
TXD
SCTE
+
TXC
+
SCTE
TXC
NC RXC
+
NC RXC
RXC
+
NC
RXC
NC
TXC
+
SCTE
+
TXC
SCTE
V
CC
V
EE
M2
M1
M0
C2
3.3µF
C1
1µF
100pF
100pF
100pF
LATCH
DCE/DTE
M2
M1
M0
LATCH
DCE/DTE
+
Figure 13. Typical Application Using the LTC1344
10
LTC1344
TYPICAL APPLICATIONS N
U
LTC1343
1
2
4
3
8
5
6
7
9
10
39
38
37
36
35
34
33
32
31
30
29
28
27
26
21
19
18
17
12
13
14
15
16
40
23
20
22
11
25
CTRL
LATCH
INVERT
423 SET
DCE
M2
M1
M0
R2
R3
R4
R1
100k
LL A
TXD A
TXD B
SCTE A
SCTE B
TM A
RXD A
RXD B
RXC A
RXC B
RXC A
RXC B
RXD A
RXD B
TM A
RTS A
RTS B
DTR A
DTR B
DCD A
DCD B
DSR A
DSR B
CTS A
CTS B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
18 DTE DCE
20 22 23 24 1
M0M1M2
DCE/
DTE
13
121138
C6
100pF
C7
100pF
19171815161097645
2
44 C2
1µF
C4
3.3µF
C10
1µF
C13
3.3µF
C5
1µF
C1
1µF
43
42
41
14
VEE
VCC
VCC
5V
2
14
24
11
15
12
17
9
3
16
25
7
1
4
19
20
23
8
10
6
22
5
13
21
1344 TA02
DB-25 CONNECTOR
LTC1344
C8
100pF
21
R1
C3
1µF
GND
LB VCC
VCC
VCC
EC 24
LTC1343
1
2
4
3
8
5
6
7
9
10
39
38
37
36
35
34
33
32
31
30
29
28
27
26
21
19
18
17
12
13
14
15
16
40
23
20
22
11
25
CTRL
LATCH
INVERT
423 SET
DCE
M2
M1
M0
R2
R3
R4
R2
100k
44
C12
1µF
C9
1µF
43
42
41
C11
1µF
GND
LB EC
R1
DTE_LL/DCE_TM
DTE_TXD/DCE_RXD
DTE_SCT/DEC_RXC
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
DTE_RL/DCE_RL
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
LB
LATCH
DCE/DTE
M2
M1
M0
SGND
SHIELD
RL A
CTS A
CTS B
DSR A
DSR B
RL A
CHARGE
PUMP
CHARGE
PUMP
D1
D2
D3
D4
D1
D2
D3
D4
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
LL A
TXC A
TXC B
24
LATCH
+
+
Controller Selectable Multiprotocol DTE Port with DB-25 Connector
11
LTC1344
TYPICAL APPLICATIONS N
U
Cable Selectable Multiprotocol DTE Port with DB-25 Connector
LTC1343
1
2
4
3
8
5
6
7
9
10
39
38
37
36
35
34
33
32
31
30
29
28
27
26
21
19
18
17
12
13
14
15
16
40
23
20
22
11
25
CTRL
LATCH
INVERT
423 SET
DCE
M2
M1
M0
R2
R3
R4
R1
100k
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
RXC A
RXC B
RXD A
RXD B
RTS A
RTS B
DTR A
DTR B
DCD A
DCD B
DSR A
DSR B
CTS A
CTS B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
DTE DCE
20 22 23 24 1
M0M1M2
DCE/
DTE
13
121138
C6
100pF
C7
100pF
19171815161097645
2
44 C2
1µF
C4
3.3µF
C10
1µF
C13
3.3µF
C5
1µF
C1
1µF
43
42
41
14
VEE
VCC
VCC
5V
2
14
24
11
15
12
17
9
3
16
7
1
4
19
20
23
8
10
6
22
5
13
25
21
18
1344 TA03
DB-25 CONNECTOR
LTC1344
C8
100pF
R1
C3
1µF
GND
LB VCC
VCC
VCC
VCC
VCC
VCC
EC 24
LTC1343
1
2
4
3
8
5
6
7
9
10
39
38
37
36
35
34
33
32
31
30
29
28
27
26
21
19
18
17
12
13
14
15
16
40
23
20
22
11
25
CTRL
LATCH
INVERT
423 SET
DCE
M2
M1
M0
R2
R3
R4
R2
100k
44
C12
1µF
C9
1µF
43
42
41
C11
1µF
GND
LB EC
R1
DTE_TXD/DCE_RXD
DTE_SCTE/DEC_RXC
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/ DCE_RTS
LB
SGND
SHIELD
CTS A
CTS B
DSR A
DSR B
CHARGE
PUMP
CHARGE
PUMP
D1
D2
D3
D4
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
TXC A
TXC B
R5
10k
R4
10k
DCE/DTE
M1
M0
VCC
VCC
D1
D2
D3
D4
24
R3
10k
VCC
CABLE WIRING FOR MODE SELECTION
MODE PIN 18 PIN 21
V.35 PIN 7 PIN 7
EIA-530, RS449, NC PIN 7
V.36, X.21
RS232 PIN 7 NC
CABLE WIRING FOR DTE/DCE
SELECTION
MODE PIN 25
DTE PIN 7
DCE NC
21
LATCH
+
+
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5207538‘ 8077833‘ HHHHHHHHHHHH’ I O I HHHHHHHHHHHHAAA, LL! umlnzz k L f L7 LJIJQ‘R
12
LTC1344
LINEAR TECHNOLOGY CORPORATION 1996
1344fa LT/TP 0300 2K REV A • PRINTED IN USA
PACKAGE DESCRIPTION
U
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
G24 SSOP 1098
0.13 – 0.22
(0.005 – 0.009)
0° – 8°
0.55 – 0.95
(0.022 – 0.037)
5.20 – 5.38**
(0.205 – 0.212)
7.65 – 7.90
(0.301 – 0.311)
12345678 9 10 11 12
8.07 – 8.33*
(0.318 – 0.328)
2122 18 17 16 15 14 13
19202324
1.73 – 1.99
(0.068 – 0.078)
0.05 – 0.21
(0.002 – 0.008)
0.65
(0.0256)
BSC 0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
*
**
Dimensions in inches (millimeters) unless otherwise noted.
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1334 Single Supply RS232/RS485 Transceiver 2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs
LTC1343 Multiprotocol Serial Transceiver Software Selectable Mulitprotocol Interface
LTC1345 Single Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals
LTC1346A Dual Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals
LTC1344A Multiprotocol Cable Terminator, Pin Compatible to LTC1344 Allows Separate RS449 Mode
LTC1543 Multiprotocol Serial Transceiver 3 Dr/3 Rx for Data and CLK Signals
LTC1544 Multiprotocol Serial Transceiver 4 Dr/4 Rx for Control Signals and LL
LTC1545 Multiprotocol Serial Transceiver 5 Dr/5 Rx for Control Signals, LL, RL amd TM
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear-tech.com

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