TMS320F2833x, 2823x Datasheet by Texas Instruments

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TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs)
1 Features
High-performance static CMOS technology
Up to 150 MHz (6.67-ns cycle time)
1.9-V/1.8-V core, 3.3-V I/O design
High-performance 32-bit CPU (TMS320C28x)
IEEE 754 single-precision Floating-Point Unit
(FPU) (F2833x only)
16 × 16 and 32 × 32 MAC operations
16 × 16 dual MAC
Harvard bus architecture
Fast interrupt response and processing
Unified memory programming model
Code-efficient (in C/C++ and Assembly)
Six-channel DMA controller (for ADC, McBSP,
ePWM, XINTF, and SARAM)
16-bit or 32-bit External Interface (XINTF)
More than 2M × 16 address reach
On-chip memory
F28335, F28333, F28235:
256K × 16 flash, 34K × 16 SARAM
F28334, F28234:
128K × 16 flash, 34K × 16 SARAM
F28332, F28232:
64K × 16 flash, 26K × 16 SARAM
1K × 16 OTP ROM
Boot ROM (8K × 16)
With software boot modes (through SCI, SPI,
CAN, I2C, McBSP, XINTF, and parallel I/O)
Standard math tables
Clock and system control
On-chip oscillator
Watchdog timer module
GPIO0 to GPIO63 pins can be connected to one of
the eight external core interrupts
Peripheral Interrupt Expansion (PIE) block that
supports all 58 peripheral interrupts
128-bit security key/lock
Protects flash/OTP/RAM blocks
Prevents firmware reverse-engineering
Enhanced control peripherals
Up to 18 PWM outputs
Up to 6 HRPWM outputs with 150-ps MEP
resolution
Up to 6 event capture inputs
Up to 2 Quadrature Encoder interfaces
Up to 8 32-bit timers
(6 for eCAPs and 2 for eQEPs)
Up to 9 16-bit timers
(6 for ePWMs and 3 XINTCTRs)
Three 32-bit CPU timers
Serial port peripherals
Up to 2 CAN modules
Up to 3 SCI (UART) modules
Up to 2 McBSP modules (configurable as SPI)
One SPI module
One Inter-Integrated Circuit (I2C) bus
12-bit ADC, 16 channels
80-ns conversion rate
2 × 8 channel input multiplexer
Two sample-and-hold
Single/simultaneous conversions
Internal or external reference
Up to 88 individually programmable, multiplexed
GPIO pins with input filtering
JTAG boundary scan support
IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
Advanced emulation features
Analysis and breakpoint functions
Real-time debug using hardware
Development support includes
ANSI C/C++ compiler/assembler/linker
Code Composer Studio IDE
– DSP/BIOS and SYS/BIOS
Digital motor control and digital power software
libraries
Low-power modes and power savings
IDLE, STANDBY, HALT modes supported
Disable individual peripheral clocks
Endianness: Little endian
Package options:
Lead-free, green packaging
176-ball plastic Ball Grid Array (BGA) (ZJZ)
179-ball MicroStar BGA (ZHH)
176-pin Low-Profile Quad Flatpack (LQFP)
(PGF)
176-pin Thermally Enhanced Low-Profile Quad
Flatpack (HLQFP) (PTP)
Temperature options:
A: –40°C to 85°C (PGF, ZHH, ZJZ)
S: –40°C to 125°C (PTP, ZJZ)
Q: –40°C to 125°C (PTP, ZJZ)
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P JUNE 2007 REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
(AEC Q100 qualification for automotive
applications)
2 Applications
Advanced Driver Assistance Systems (ADAS)
Building automation
Electronic point of sale
Electric Vehicle/Hybrid Electric Vehicle (EV/HEV)
powertrain
Factory automation
Grid infrastructure
Industrial transport
Medical, healthcare and fitness
Motor drives
Power delivery
Telecom infrastructure
Test and measurement
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Delfino™ Premium Performance family and the Piccolo™ Entry Performance family.
TMS320C2000 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-
loop performance in real-time control applications. The C2000 microcontrollers line includes the Delfino™
Premium Performance microcontroller family and the Piccolo™ Entry Performance microcontroller family.
The TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332, TMS320F28235, TMS320F28234,
and TMS320F28232 devices, members of the TMS320C28x/ Delfino DSC/MCU generation, are highly
integrated, high-performance solutions for demanding control applications.
Throughout this document, the devices are abbreviated as F28335, F28334, F28333, F28332, F28235, F28234,
and F28232, respectively. F2833x Device Comparison and F2823x Device Comparison provide a summary of
features for each device.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information (1)
PART NUMBER PACKAGE BODY SIZE
TMS320F28335ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320F28334ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320F28332ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320F28235ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320F28234ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320F28232ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320F28335ZJZ BGA (176) 15.0 mm × 15.0 mm
TMS320F28334ZJZ BGA (176) 15.0 mm × 15.0 mm
TMS320F28332ZJZ BGA (176) 15.0 mm × 15.0 mm
TMS320F28235ZJZ BGA (176) 15.0 mm × 15.0 mm
TMS320F28234ZJZ BGA (176) 15.0 mm × 15.0 mm
TMS320F28232ZJZ BGA (176) 15.0 mm × 15.0 mm
TMS320F28335PGF LQFP (176) 24.0 mm × 24.0 mm
TMS320F28334PGF LQFP (176) 24.0 mm × 24.0 mm
TMS320F28333PGF LQFP (176) 24.0 mm × 24.0 mm
TMS320F28332PGF LQFP (176) 24.0 mm × 24.0 mm
TMS320F28235PGF LQFP (176) 24.0 mm × 24.0 mm
TMS320F28234PGF LQFP (176) 24.0 mm × 24.0 mm
TMS320F28232PGF LQFP (176) 24.0 mm × 24.0 mm
TMS320F28335PTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28334PTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
2Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
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Device Information (1) (continued)
PART NUMBER PACKAGE BODY SIZE
TMS320F28332PTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28235PTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28234PTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28232PTP HLQFP (176) 24.0 mm × 24.0 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
l TEXAS INSTRUMENTS smswm u SARAM AK x ts ta~w Dam. 1~w mg. L5 SARAM AK x ts ta~w Dam. 1~w mg. Ls SARAM AK x ts ta~w Dam. 1~w mg. L7 SARAM AK x ts ta~w Dam. 1~w mg. accessible
3.1 Functional Block Diagram
L0 SARAM 4K x 16
(0-Wait, Dual Map)
L1 SARAM 4K x 16
(0-Wait, Dual Map)
L2 SARAM 4K x 16
(0-Wait, Dual Map)
L3 SARAM 4K x 16
(0-Wait, Dual Map)
M0 SARAM 1Kx16
(0-Wait)
M1 SARAM 1Kx16
(0-Wait)
L4 SARAM 4K x 16
(0-W Data, 1-W Prog)
L5 SARAM 4K x 16
(0-W Data, 1-W Prog)
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
(0-W Data, 1-W Prog)
Memory Bus
Boot ROM
8K x 16
Code
Security
Module
DMA Bus
PSWD
OTP 1K x 16
Flash
256K x 16
8 Sectors
Pump
Flash
Wrapper
TEST1
TEST2
XINTF
XA0/XWE1
XWE0
XZCS6
XZCS7
XZCS0
XR/W
XREADY
XHOLD
XHOLDA
XD31:0
XA19:1
GPIO
MUX
Memory Bus
Memory Bus
XCLKOUT
XRD
GPIO
MUX
88 GPIOs 8 External Interrupts
88 GPIOs
12-Bit
ADC
2-S/H
A7:0
B7:0
CPU Timer 0
CPU Timer 1
CPU Timer 2
OSC,
PLL,
LPM,
WD
DMA
6 Ch
PIE
(Interrupts)
32-bit CPU
(150 MHZ @ 1.9 V)
(100 MHz @ 1.8 V)
EMU1
EMU0
TRST
TDO
TMS
TDI
TCK
XRS
X2
X1
XCLKIN
FPU
REFIN
DMA Bus
Memory Bus
FIFO
(16 Levels)
SCI-A/B/C
FIFO
(16 Levels)
SPI-A
FIFO
(16 Levels)
I2C
16-bit peripheral bus
SPISOMIx
SPISIMOx
SPICLKx
SPISTEx
SCIRXDx
SCITXDx
SDAx
SCLx
McBSP-A/B
MRXx
MDXx
MCLKXx
MCLKRx
MFSXx
MFSRx
32-bit peripheral bus
(DMA accessible)
ePWM-1/../6
HRPWM-1/../6
eCAP-1/../6 eQEP-1/2
EPWMxA
EPWMxB
ESYNCI
ESYNCO
TZx
ECAPx
EQEPxA
EQEPxB
EQEPxI
EQEPxS
CAN-A/B
(32-mbox)
CANRXx
CANTXx
32-bit peripheral bus
GPIO MUX
88 GPIOs
XINTF
Secure zone
Figure 3-1. Functional Block Diagram
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
4Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
3.1 Functional Block Diagram........................................... 4
4 Revision History.............................................................. 5
5 Device Comparison......................................................... 6
5.1 Related Products........................................................ 8
6 Terminal Configuration and Functions..........................9
6.1 Pin Diagrams.............................................................. 9
6.2 Signal Descriptions................................................... 19
7 Specifications................................................................ 30
7.1 Absolute Maximum Ratings...................................... 30
7.2 ESD Ratings – Automotive....................................... 31
7.3 ESD Ratings – Commercial...................................... 31
7.4 Recommended Operating Conditions.......................32
7.5 Power Consumption Summary................................. 33
7.6 Electrical Characteristics...........................................37
7.7 Thermal Resistance Characteristics......................... 38
7.8 Thermal Design Considerations................................41
7.9 Timing and Switching Characteristics....................... 42
7.10 On-Chip Analog-to-Digital Converter...................... 96
7.11 Migrating Between F2833x Devices and
F2823x Devices.........................................................103
8 Detailed Description....................................................104
8.1 Brief Descriptions....................................................104
8.2 Peripherals.............................................................. 112
8.3 Memory Maps......................................................... 156
8.4 Register Map...........................................................163
8.5 Interrupts.................................................................166
8.6 System Control....................................................... 171
8.7 Low-Power Modes Block........................................ 177
9 Applications, Implementation, and Layout............... 178
9.1 TI Design or Reference Design...............................178
10 Device and Documentation Support........................179
10.1 Getting Started......................................................179
10.2 Device and Development Support Tool
Nomenclature............................................................ 179
10.3 Tools and Software............................................... 181
10.4 Documentation Support........................................ 182
10.5 Support Resources............................................... 185
10.6 Trademarks...........................................................185
10.7 Electrostatic Discharge Caution............................185
10.8 Glossary................................................................185
11 Mechanical, Packaging, and Orderable
Information.................................................................. 186
11.1 Packaging Information.......................................... 186
4 Revision History
Changes from April 22, 2019 to February 1, 2021 (from Revision O (April 2019) to Revision P
(February 2021)) Page
Added Q1 Part Numbers................................................................................................................................ 0
Table 5-1, Table 5-2: Added Q1 Part Numbers...................................................................................................6
Figure 10-1: Added GPN information............................................................................................................. 179
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
5 Device Comparison
Table 5-1. F2833x Device Comparison
FEATURE TYPE(1)
F28335
F28335-Q1
(150 MHz)
F28334
(150 MHz)
F28333
(100 MHz)
F28332
(100 MHz)
Instruction cycle 6.67 ns 6.67 ns 10 ns 10 ns
Floating-point unit Yes Yes Yes Yes
3.3-V on-chip flash (16-bit word) 256K 128K 256K 64K
Single-access RAM (SARAM)
(16-bit word) – 34K 34K 34K 26K
One-time programmable (OTP) ROM
(16-bit word) – 1K 1K 1K 1K
Code security for on-chip flash/
SARAM/OTP blocks – Yes Yes Yes Yes
Boot ROM (8K × 16) Yes Yes Yes Yes
16/32-bit External Interface (XINTF) 1 Yes Yes Yes Yes
6-channel Direct Memory Access (DMA) 0 Yes Yes Yes Yes
PWM channels 0 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6
HRPWM channels 0 ePWM1A/2A/3A/4A/
5A/6A
ePWM1A/2A/3A/4A/
5A/6A
ePWM1A/2A/3A/4A/
5A/6A ePWM1A/2A/3A/4A
32-bit capture inputs or auxiliary PWM
outputs 0 eCAP1/2/3/4/5/6 eCAP1/2/3/4 eCAP1/2/3/4/5/6 eCAP1/2/3/4
32-bit QEP channels (four inputs/
channel) 0 eQEP1/2 eQEP1/2 eQEP1/2 eQEP1/2
Watchdog timer Yes Yes Yes Yes
12-bit ADC
No. of channels
2
16 16 16 16
MSPS 12.5 12.5 12.5 12.5
Conversion time 80 ns 80 ns 80 ns 80 ns
32-bit CPU timers 3 3 3 3
Multichannel Buffered Serial Port
(McBSP)/SPI 1 2 (A/B) 2 (A/B) 2 (A/B) 1 (A)
Serial Peripheral Interface (SPI) 0 1 1 1 1
Serial Communications Interface (SCI) 0 3 (A/B/C) 3 (A/B/C) 3 (A/B/C) 2 (A/B)
Enhanced Controller Area Network
(eCAN) 0 2 (A/B) 2 (A/B) 2 (A/B) 2 (A/B)
Inter-Integrated Circuit (I2C) 0 1 1 1 1
General-purpose I/O pins (shared) 88 88 88 88
External interrupts 8 8 8 8
Packaging
176-Pin PGF Yes Yes Yes Yes
176-Pin PTP Yes Yes Yes
179-Ball ZHH Yes Yes Yes
176-Ball ZJZ Yes Yes Yes
Temperature
options
A: –40°C to 85°C PGF, ZHH, ZJZ PGF, ZHH, ZJZ PGF PGF, ZHH, ZJZ
S: –40°C to 125°C PTP, ZJZ PTP, ZJZ PTP, ZJZ
Q: –40°C to 125°C
(AEC Q100
Qualification)
PTP, ZJZ PTP, ZJZ PTP, ZJZ
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 5-2. F2823x Device Comparison
FEATURE TYPE(1)
F28235
F28235-Q1
(150 MHz)
F28234
F28234-Q1
(150 MHz)
F28232
F28232-Q1
(100 MHz)
Instruction cycle 6.67 ns 6.67 ns 10 ns
Floating-point unit No No No
3.3-V on-chip flash (16-bit word) 256K 128K 64K
Single-access RAM (SARAM)
(16-bit word) – 34K 34K 26K
One-time programmable (OTP) ROM
(16-bit word) – 1K 1K 1K
Code security for on-chip flash/
SARAM/OTP blocks – Yes Yes Yes
Boot ROM (8K × 16) Yes Yes Yes
16/32-bit External Interface (XINTF) 1 Yes Yes Yes
6-channel Direct Memory Access (DMA) 0 Yes Yes Yes
PWM channels 0 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6
HRPWM channels 0 ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A
32-bit capture inputs or auxiliary PWM
outputs 0 eCAP1/2/3/4/5/6 eCAP1/2/3/4 eCAP1/2/3/4
32-bit QEP channels (four inputs/channel) 0 eQEP1/2 eQEP1/2 eQEP1/2
Watchdog timer Yes Yes Yes
12-bit ADC
No. of channels
2
16 16 16
MSPS 12.5 12.5 12.5
Conversion time 80 ns 80 ns 80 ns
32-bit CPU timers 3 3 3
Multichannel Buffered Serial Port
(McBSP)/SPI 1 2 (A/B) 2 (A/B) 1 (A)
Serial Peripheral Interface (SPI) 0 1 1 1
Serial Communications Interface (SCI) 0 3 (A/B/C) 3 (A/B/C) 2 (A/B)
Enhanced Controller Area Network (eCAN) 0 2 (A/B) 2 (A/B) 2 (A/B)
Inter-Integrated Circuit (I2C) 0 1 1 1
General-purpose I/O pins (shared) 88 88 88
External interrupts 8 8 8
Packaging
176-Pin PGF Yes Yes Yes
176-Pin PTP Yes Yes Yes
179-Ball ZHH Yes Yes Yes
176-Ball ZJZ Yes Yes Yes
Temperature options
A: –40°C to 85°C PGF, ZHH, ZJZ PGF, ZHH, ZJZ PGF, ZHH, ZJZ
S: –40°C to 125°C PTP, ZJZ PTP, ZJZ PTP, ZJZ
Q: –40°C to 125°C
(AEC Q100
Qualification)
PTP, ZJZ PTP, ZJZ PTP, ZJZ
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
5.1 Related Products
For information about other devices in the Delfino family of products, see the following links:
Original Delfino™ series:
TMS320F2833x Delfino™ Microcontrollers
The F2833x series is the original Delfino MCU. It is the first C2000 MCU that is offered with a floating-point unit
(FPU). It has the first-generation ePWM timers that are used throughout the rest of the Delfino and Piccolo
families. The 12.5-MSPS, 12-bit ADC is still class-leading for an integrated analog-to-digital converter. The
F2833x has a 150-MHz CPU and up to 512KB of on-chip Flash. It is available in a 176-pin QFP or 179-ball BGA
package.
TMS320C2834x Delfino™ Microcontrollers
The C2834x series removes the on-chip Flash memory and integrated ADC to enable the fastest available clock
speeds of up to 300 MHz. It is available in a 179-ball BGA or 256-ball BGA package.
Newest Delfino™ series:
TMS320F2837xD Delfino™ Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Delfino™ Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the Piccolo™
TMS320F2807x series.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
8Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
6 Terminal Configuration and Functions
6.1 Pin Diagrams
The 176-pin PGF/PTP low-profile quad flatpack (LQFP) pin assignments are shown in Figure 6-1. The 179-ball
ZHH ball grid array (BGA) terminal assignments are shown in Figure 6-2 through Figure 6-5. The 176-ball ZJZ
plastic BGA terminal assignments are shown in Figure 6-6 through Figure 6-9. Table 6-1 describes the
function(s) of each pin.
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
GPIO48/ECAP5/XD31
TCK
EMU1
EMU0
VDD3VFL
VSS
TEST2
TEST1
XRS
TMS
TRST
TDO
TDI
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO27/ECAP4/EQEP2S/MFSXB
GPIO26/ECAP3/EQEP2I/MCLKXB
VDDIO
VSS
GPIO25/ECAP2/EQEP2B/MDRB
GPIO24/ECAP1/EQEP2A/MDXB
GPIO23/EQEP1I/MFSXA/SCIRXDB
GPIO22/EQEP1S/MCLKXA/SCITXDB
GPIO21/EQEP1B/MDRA/CANRXB
GPIO20/EQEP1A/MDXA/CANTXB
GPIO19/ /SCIRXDB/CANTXASPISTEA
GPIO18/SPICLKA/SCITXDB/CANRXA
VDD
VSS
VDD2A18
VSS2AGND
ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
VDDAIO
GPIO75/XD4
GPIO74/XD5
GPIO73/XD6
GPIO72/XD7
GPIO71/XD8
GPIO70/XD9
VDD
VSS
GPIO69/XD10
GPIO68/XD11
GPIO67/XD12
VDDIO
VSS
GPIO66/XD13
VSS
VDD
GPIO65/XD14
GPIO64/XD15
GPIO63/SCITXDC/XD16
GPIO62/SCIRXDC/XD17
GPIO61/MFSRB/XD18
GPIO60/MCLKRB/XD19
GPIO59/MFSRA/XD20
VDD
VSS
VDDIO
VSS
XCLKIN
X1
VSS
X2
VDD
GPIO58/MCLKRA/XD21
GPIO57/ /XD22SPISTEA
GPIO56/SPICLKA/XD23
GPIO55/SPISOMIA/XD24
GPIO54/SPISIMOA/XD25
GPIO53/EQEP1I/XD26
GPIO52/EQEP1S/XD27
VDDIO
VSS
GPIO51/EQEP1B/XD28
GPIO50/EQEP1A/XD29
GPIO49/ECAP6/XD30
GPIO30/CANRXA/XA18
GPIO29/SCITXDA/XA19
VSS
VDD
GPIO0/EPWM1A
GPIO1/EPWM1B/ECAP6/MFSRB
GPIO2/EPWM2A
VSS
VDDIO
GPIO3/EPWM2B/ECAP5/MCLKRB
GPIO4/EPWM3A
GPIO5/EPWM3B/MFSRA/ECAP1
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
VDD
GPIO7/EPWM4B/MCLKRA/ECAP2
GPIO8/EPWM5A/CANTXB/ADCSOCAO
GPIO9/EPWM5B/SCITXDB/ECAP3
GPIO10/EPWM6A/CANRXB/ADCSOCBO
GPIO11/EPWM6B/SCIRXDB/ECAP4
GPIO12 /CANTXB/MDXB/TZ1
VSS
VDD
GPIO13/ /CANRXB/MDRBTZ2
GPIO14/ /XHOLD/ /TZ3 SCITXDBMCLKXB
GPIO15/ /XHOLDATZ4 /SCIRXDB/MFSXB
GPIO16/SPISIMOA/CANTXB/TZ5
GPIO17/SPISOMIA/CANRXB/TZ6
VDD
VSS
VDD1A18
VSS1AGND
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
VSSAIO
GPIO76/XD3
GPIO77/XD2
GPIO78/XD1
GPIO79/XD0
GPIO38/XWE0
XCLKOUT
VDD
VSS
GPIO28/SCIRXDA/XZCS6
GPIO34/ECAP1/XREADY
VDDIO
VSS
GPIO36/SCIRXDA/XZCS0
VDD
VSS
GPIO35/SCITXDA/XR/W
XRD
GPIO37/ECAP2/XZCS7
GPIO40/XA0/XWE1
GPIO41/XA1
GPIO42/XA2
VDD
VSS
GPIO43/XA3
GPIO44/XA4
GPIO45/XA5
VDDIO
VSS
GPIO46/XA6
GPIO47/XA7
GPIO80/XA8
GPIO81/XA9
GPIO82/XA10
VSS
VDD
GPIO83/XA11
GPIO84/XA12
VDDIO
VSS
GPIO85/XA13
GPIO86/XA14
GPIO87/XA15
GPIO39/XA16
GPIO31/CANTXA/XA17
GPIO28/SCIRXDA/XZCS6
Figure 6-1. F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View)
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
Note
The thermal pad should be soldered to the ground (GND) plane of the PCB because this will provide
the best thermal conduction path. For this device, the thermal pad is not electrically shorted to the
internal die VSS; therefore, the thermal pad does not provide an electrical connection to the PCB
ground. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the
PCB must be designed with this technology in mind. A thermal land is required on the surface of the
PCB directly underneath the thermal pad. The thermal land should be soldered to the thermal pad; the
thermal land should be as large as needed to dissipate the required heat. An array of thermal vias
should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™
thermally enhanced package for more details on using the PowerPAD package.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
ADCINB0 ADCINB2 ADCINB6 ADCREFP
ADCINA1
ADCRESEXTADCINA2 ADCLO ADCINA0 ADCINB4
VSS1AGND
ADCINA4 ADCINA3 ADCINB3 ADCREFIN
P P
N N
M M
L LADCINA5
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
VSSA2 ADCINA7 ADCINB7
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDD1A18
VDD
GPIO14/
/
SCITXDB/
MCLKXB
TZ3XHOLD/
GPIO13/
CANRXB/
MDRB
TZ2/
VDDAIO
K K
J J
H H
1 2 3 4 5
6 7
GPIO20/
EQEP1A/
MDXA/
CANTXB
VSS2AGND
GPIO21/
EQEP1B/
MDRA/
CANRXB
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
VSS
1 2 345 6 7
VSSAIO VSS
VDD
VDD
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO19/
SCIRXDB/
CANTXA
SPISTEA/
ADCINA6
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO15/
/
SCIRXDB/
MFSXB
TZ4XHOLDA/
VDDA2
VDD2A18
ADCREFMADCINB5ADCINB1
Figure 6-2. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper-Left Quadrant) (Bottom View)
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
GPIO50/
EQEP1A/
XD29
TMS TEST2 EMU1
GPIO51/
EQEP1B/
XD28
GPIO48/
ECAP5/
XD31
TCK
GPIO52/
EQEP1S/
XD27
VSS
GPIO27/
ECAP4/
EQEP2S/
MFSXB
XRS EMU0
GPIO53/
EQEP1I/
XD26
VDD
GPIO55/
SPISOMIA/
XD24
VSS
GPIO56/
SPICLKA/
XD23
GPIO58/
MCLKRA/
XD21
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
TRST
GPIO32/
SDAA/
EPWMSYNCI/
ADCSOCAO
VDDIO
8 9
10 11 12 13 14
PP
NN
MM
LL
KK
J
J
HH
GPIO57/
/
XD22
SPISTEA
X1 XCLKIN
GPIO59/
MFSRA/
XD20
VSS
GPIO25/
ECAP2/
EQEP2B/
MDRB
VSS
VDD
VSS
8 9 10 11 12 13 14
VSS
VSS
TEST1
VDD3VFL
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
TDO
VDDIO
VSS
X2
GPIO54/
SPISIMOA/
XD25
TDI
VDDIO
GPIO49/
ECAP6/
XD30
Figure 6-3. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper-Right Quadrant) (Bottom View)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
GPIO11
EPWM6B
SCIRXDB
ECAP4
/
/
/
GPIO12
CANTXB
MDXB
/
/
/
TZ1
GPIO10
EPWM6A
CANRXB
/
/
/
ADCSOCBO
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO81/
XA9
GPIO8/
EPWM5A/
CANTXB/
ADCSOCAO
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO84/
XA12
GPIO6/
EPWM4A/
EPWMSYNCI/
EPWMSYNCO
GPIO4/
EPWM3A
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
VDDIO
VDDIO
VSS
GPIO2/
EPWM2A
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO86/
XA14
GPIO83/
XA11
G
F
E
D
GPIO0/
EPWM1A
GPIO29/
SCITXDA/
XA19
VSS
GPIO85/
XA13
GPIO82/
XA10
VDD
GPIO30/
CANRXA/
XA18
GPIO39/
XA16 VSS VDD
GPIO31/
CANTXA/
XA17
GPIO87/
XA15 VDDIO
C
B
A
1 2 3 4 5 6 7
G
F
E
D
C
B
A
VSS
GPIO45/
XA5
VSS
GPIO80/
XA8
GPIO46/
XA6
GPIO43/
XA3
GPIO44/
XA4
GPIO47/
XA7
VSS
1 2 3 4 5
6 7
VSS
VDD
VSS
Figure 6-4. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower-Left Quadrant) (Bottom View)
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
GPIO60/
MCLKRB/
XD19
GPIO64/
XD15
GPIO63/
SCITXDC/
XD16
GPIO61/
MFSRB/
XD18
GPIO67/
XD12
GPIO65/
XD14
GPIO62/
SCIRXDC
XD17
GPIO78/
XD1
GPIO79/
XD0
GPIO66/
XD13
GPIO68/
XD11
VSS
GPIO37/
ECAP2/
XZCS7
GPIO34/
ECAP1/
XREADY
GPIO38/
XWE0
GPIO70/
XD9
G
F
E
D
VDD
GPIO40/
XA0/
XWE1
VSS
XCLKOUT GPIO73/
XD6
GPIO42/
XA2 XRD
GPIO28/
SCIRXDA/
XZCS6
VDD
GPIO35/
SCITXDA/
XR/W
GPIO69/
XD10
VDDIO
C
B
A
8 9 10 11 12 13 14
G
F
E
D
C
B
A
GPIO74/
XD5
GPIO76/
XD3
GPIO72/
XD7
GPIO75/
XD4
GPIO77/
XD2
VSS
GPIO41/
XA1
VSS
VDD
VSS
8 9
10 11 12 13 14
VSS VDD
VSS
VDDIO
GPIO36/
SCIRXDA/
XZCS0
VDD
GPIO71/
XD8
Figure 6-5. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower-Right Quadrant) (Bottom View)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
M TEXAS INSTRUMENTS
VSSA2 ADCINB0 ADCREFM ADCREFP ADCRESEXT ADCREFIN
VSSAIO ADCLO ADCINB1 ADCINB3 ADCINB5 ADCINB7 EMU0
ADCINA2 ADCINA1 ADCINA0 ADCINB2 ADCINB4 ADCINB6 TEST1
ADCINA5 ADCINA4 ADCINA3 VSS1AGND VDDAIO VDD2A18 TEST2
ADCINA7 ADCINA6 VDD1A18 VDDA2
GPIO15/
/ /
SCIRXDB/
MFSXB
TZ4XHOLDA
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDD VSS VSS
GPIO14/
/TZ3XHOLD/
SCITXDB/
MCLKXB
VDD VSS VSS
P
N
M
L
K
J
H
1 2 3 4 5 6 7
VSS2AGND
GPIO12/
TZ1/
CANTXB/
MDXB
GPIO13/
TZ2/
CANRXB/
MDRB
Figure 6-6. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper-Left Quadrant) (Bottom View)
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
VSS VSS
VSS VSS
P
N
M
L
K
J
H
8 9 10 11 12 13 14
EMU1
GPIO20/
EQEP1A/
MDXA/
CANTXB
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
VSS VSS
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO21/
EQEP1B/
MDRA/
CANRXB
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
TDI TDO VDDIO
GPIO19/
/
SCIRXDB/
CANTXA
SPISTEA
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO32/
SDAA/
EPWMSYNCI/
ADSOCAO
TMS XRS TCK
VDD VDD3VFL VDDIO TRST
GPIO50/
EQEP1A/
XD29
GPIO49/
ECAP6/
XD30
GPIO48/
ECAP5/
XD31
VDD
GPIO53
EQEP1I/
XD26
GPIO52/
EQEP1S/
XD27
GPIO51/
EQEP1B/
XD28
VDD
GPIO56/
SPICLKA/
XD23
GPIO55/
SPISOMIA/
XD24
GPIO54/
SPISIMOA/
XD25
GPIO59/
MFSRA/
XD20
GPIO58/
MCLKRA/
XD21
GPIO57/
/
XD22
SPISTEA X2
Figure 6-7. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper-Right Quadrant) (Bottom View)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
G
F
E
D
C
B
A
1 2 3 4 5 6 7
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO10/
EPWM6A/
CANRXB/
ADCSOCBO
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
VDDIO VSS VSS
VSS VSS
GPIO6/
EPWM4A/
EPWMSYNCI/
EPWMSYNCO
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO8/
EPWM5A/
CANTXB/
ADCSOCAO
VDD
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
GPIO4/
EPWM3A
GPIO5/
EPWM3B/
MFSRA/
ECAP1
VDDIO
GPIO0/
EPWM1A
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO2/
EPWM2A VDD VDD
GPIO47/
XA7 VDDIO
GPIO29/
SCITXDA/
XA19
GPIO30/
CANRXA/
XA18
GPIO39/
XA16
GPIO85/
XA13
GPIO82/
XA10
GPIO46/
XA6
GPIO43/
XA3
VDDIO
GPIO31/
CANTXA/
XA17
GPIO87/
XA15
GPIO84/
XA12
GPIO81/
XA9
GPIO45/
XA5
GPIO42/
XA2
VSS VSS
GPIO86/
XA14
GPIO83/
XA11
GPIO80/
XA8
GPIO44/
XA4
GPIO41/
XA1
Figure 6-8. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower-Left Quadrant) (Bottom View)
www.ti.com
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
w TEXAS INSTRUMENTS
G
F
E
D
C
B
A
8 9 10 11 12 13 14
X1
VSS VSS
VSS VSS
VDDIO
GPIO60/
MCLKRB/
XD19
XCLKIN
VDD
GPIO63/
SCITXDC/
XD16
GPIO62/
SCIRXDC/
XD17
GPIO61/
MFSRB/
XD18
VDD
GPIO66/
XD13
GPIO65/
XD14
GPIO64/
XD15
VDD VDD
GPIO28/
SCIRXDA/
XZCS6
VDDIO
GPIO69/
XD10
GPIO68/
XD11
GPIO67/
XD12
GPIO40/
XA0/XWE1
GPIO36/
SCIRXDA/
XZCS0
GPIO38/
XWE0
GPIO78/
XD1
GPIO75/
XD4
GPIO71/
XD8
GPIO70/
XD9
GPIO37/
ECAP2/
XZCS7
GPIO35/
SCITXDA/
XR/W
GPIO79/
XD0
GPIO77/
XD2
GPIO74/
XD5
GPIO72
XD7 VSS
VSS
XRD
GPIO34/
ECAP1/
XREADY
XCLKOUT GPIO76/
XD3
GPIO73/
XD6 VDDIO
Figure 6-9. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower-Right Quadrant) (Bottom View)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
6.2 Signal Descriptions
Table 6-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available in all
devices. See Table 5-1 and Table 5-2 for details. Inputs are not 5-V tolerant. All pins capable of producing an
XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured for
XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise indicated). All
GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin
basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 pins are not enabled at reset.
The pullups on GPIO12–GPIO87 are enabled upon reset.
Table 6-1. Signal Descriptions
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
JTAG
TRST 78 M10 L11
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during
normal device operation. An external pulldown resistor is required on this pin. The value of
this resistor should be based on drive strength of the debugger pods applicable to the
design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-
specific, TI recommends validating each target board for proper operation of the debugger
and the application. (I, ↓)
TCK 87 N12 M14 JTAG test clock with internal pullup (I, ↑)
TMS 79 P10 M12 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK. (I, ↑)
TDI 76 M9 N12 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK. (I, ↑)
TDO 77 K9 N13 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
EMU0 85 L11 N7
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should
be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to
4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the application.
EMU1 86 P12 P8
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should
be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to
4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the application.
FLASH
VDD3VFL 84 M11 L9 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST1 81 K10 M7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 82 P11 L7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
CLOCK
XCLKOUT 138 C11 A10
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half
the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16
(XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF]
to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state
during a reset. (O/Z, 8 mA drive).
XCLKIN 105 J14 G13
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this
case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V
oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
X1 104 J13 G14
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a
ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the
1.9-V/1.8-V core digital power supply. A 1.9-V/1.8-V external oscillator may be connected
to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V
external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)
X2 102 J11 H14 Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected
across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
XRS 80 L10 M13
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the
address contained at the location 0x3FFFC0. When XRS is brought to a high level,
execution begins at the location pointed to by the PC. This pin is driven low by the DSC
when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by
an external device, it should be done using an open-drain device.
ADC SIGNALS
ADCINA7 35 K4 K1 ADC Group A, Channel 7 input (I)
ADCINA6 36 J5 K2 ADC Group A, Channel 6 input (I)
ADCINA5 37 L1 L1 ADC Group A, Channel 5 input (I)
ADCINA4 38 L2 L2 ADC Group A, Channel 4 input (I)
ADCINA3 39 L3 L3 ADC Group A, Channel 3 input (I)
ADCINA2 40 M1 M1 ADC Group A, Channel 2 input (I)
ADCINA1 41 N1 M2 ADC Group A, Channel 1 input (I)
ADCINA0 42 M3 M3 ADC Group A, Channel 0 input (I)
ADCINB7 53 K5 N6 ADC Group B, Channel 7 input (I)
ADCINB6 52 P4 M6 ADC Group B, Channel 6 input (I)
ADCINB5 51 N4 N5 ADC Group B, Channel 5 input (I)
ADCINB4 50 M4 M5 ADC Group B, Channel 4 input (I)
ADCINB3 49 L4 N4 ADC Group B, Channel 3 input (I)
ADCINB2 48 P3 M4 ADC Group B, Channel 2 input (I)
ADCINB1 47 N3 N3 ADC Group B, Channel 1 input (I)
ADCINB0 46 P2 P3 ADC Group B, Channel 0 input (I)
ADCLO 43 M2 N2 Low Reference (connect to analog ground) (I)
ADCRESEXT 57 M5 P6 ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN 54 L5 P7 External reference input (I)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
ADCREFP 56 P5 P5
Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass
capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data
sheet that is used in the system.
ADCREFM 55 N5 P4
Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass
capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data
sheet that is used in the system.
CPU AND I/O POWER PINS
VDDA2 34 K2 K4 ADC Analog Power Pin
VSSA2 33 K3 P1 ADC Analog Ground Pin
VDDAIO 45 N2 L5 ADC Analog I/O Power Pin
VSSAIO 44 P1 N1 ADC Analog I/O Ground Pin
VDD1A18 31 J4 K3 ADC Analog Power Pin
VSS1AGND 32 K1 L4 ADC Analog Ground Pin
VDD2A18 59 M6 L6 ADC Analog Power Pin
VSS2AGND 58 K6 P2 ADC Analog Ground Pin
VDD 4 B1 D4
CPU and Logic Digital Power Pins
VDD 15 B5 D5
VDD 23 B11 D8
VDD 29 C8 D9
VDD 61 D13 E11
VDD 101 E9 F4
VDD 109 F3 F11
VDD 117 F13 H4
VDD 126 H1 J4
VDD 139 H12 J11
VDD 146 J2 K11
VDD 154 K14 L8
VDD 167 N6
VDDIO 9 A4 A13
Digital I/O Power Pin
VDDIO 71 B10 B1
VDDIO 93 E7 D7
VDDIO 107 E12 D11
VDDIO 121 F5 E4
VDDIO 143 L8 G4
VDDIO 159 H11 G11
VDDIO 170 N14 L10
VDDIO N14
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
VSS 3 A5 A1
Digital Ground Pins
VSS 8 A10 A2
VSS 14 A11 A14
VSS 22 B4 B14
VSS 30 C3 F6
VSS 60 C7 F7
VSS 70 C9 F8
VSS 83 D1 F9
VSS 92 D6 G6
VSS 103 D14 G7
VSS 106 E8 G8
VSS 108 E14 G9
VSS 118 F4 H6
VSS 120 F12 H7
VSS 125 G1 H8
VSS 140 H10 H9
VSS 144 H13 J6
VSS 147 J3 J7
VSS 155 J10 J8
VSS 160 J12 J9
VSS 166 M12 P13
VSS 171 N10 P14
VSS N11
VSS P6
VSS P8
GPIO AND PERIPHERAL SIGNALS
GPIO0
EPWM1A
-
-
5 C1 D1
General-purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
GPIO1
EPWM1B
ECAP6
MFSRB
6 D3 D2
General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO2
EPWM2A
-
-
7 D2 D3
General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
MCLKRB
10 E4 E1
General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
GPIO4
EPWM3A
-
-
11 E2 E2
General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021 www.ti.com
22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
GPIO5
EPWM3B
MFSRA
ECAP1
12 E3 E3
General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
13 E1 F1
General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM4B
MCLKRA
ECAP2
16 F2 F2
General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
GPIO8
EPWM5A
CANTXB
ADCSOCAO
17 F1 F3
General-purpose Input/Output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
GPIO9
EPWM5B
SCITXDB
ECAP3
18 G5 G1
General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
GPIO10
EPWM6A
CANRXB
ADCSOCBO
19 G4 G2
General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4
20 G2 G3
General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
21 G3 H1
General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
24 H3 H2
General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
25 H2 H3
General-purpose input/output 14 (I/O/Z)
TZ3/ XHOLD
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external
interface (XINTF) to release the external bus and place all buses and strobes into a high-
impedance state. To prevent this from happening when TZ3 signal goes active, disable this
function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into
high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by
default, unless they are enabled by the code. The XINTF will release the bus when any
current access is complete and there are no pending accesses on the XINTF. (I)
SCITXDB SCI-B Transmit (O)
MCLKXB McBSP-B transmit clock (I/O)
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
GPIO15
26 H4 J1
General-purpose input/output 15 (I/O/Z)
TZ4/ XHOLDA
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on
the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4
function is chosen. If the pin is configured as an output, then XHOLDA function is chosen.
XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF
buses and strobe signals will be in a high-impedance state. XHOLDA is released when the
XHOLD signal is released. External devices should only drive the external bus when
XHOLDA is active (low). (I/O)
SCIRXDB SCI-B receive (I)
MFSXB McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
27 H5 J2
General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
GPIO17
SPISOMIA
CANRXB
TZ6
28 J1 J3
General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
SPICLKA
SCITXDB
CANRXA
62 L6 N8
General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
GPIO19
SPISTEA
SCIRXDB
CANTXA
63 K7 M8
General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
CANTXB
64 L7 P9
General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
GPIO21
EQEP1B
MDRA
CANRXB
65 P7 N9
General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
GPIO22
EQEP1S
MCLKXA
SCITXDB
66 N7 M9
General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
GPIO23
EQEP1I
MFSXA
SCIRXDB
67 M7 P10
General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB
68 M8 N10
General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
69 N8 M10
General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
72 K8 P11
General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
GPIO27
ECAP4
EQEP2S
MFSXB
73 L9 N11
General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
141 E10 D10
General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19
2 C2 C1
General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
1 B2 C2
General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17
176 A2 B2
General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
74 N9 M11
General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
75 P9 P12
General-purpose Input/Output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
142 D10 A9
General-purpose Input/Output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal. Note that this pin is always (directly) connected to the
XINTF. If an application uses this pin as a GPIO while also using the XINTF, it should
configure the XINTF to ignore READY.
GPIO35
SCITXDA
XR/ W
148 A9 B9
General-purpose Input/Output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0
145 C10 C9
General-purpose Input/Output 36 (I/O/Z)
SCI receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7
150 D9 B8
General-purpose Input/Output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0
137 D11 C10
General-purpose Input/Output 38 (I/O/Z)
-
External Interface Write Enable 0 (O)
GPIO39
-
XA16
175 B3 C3
General-purpose Input/Output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0/ XWE1
151 D8 C8
General-purpose Input/Output 40 (I/O/Z)
-
External Interface Address Line 0/External Interface Write Enable 1 (O)
GPIO41
-
XA1
152 A8 A7
General-purpose Input/Output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2
153 B8 B7
General-purpose Input/Output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
GPIO43
-
XA3
156 B7 C7
General-purpose Input/Output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4
157 A7 A6
General-purpose Input/Output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
XA5
158 D7 B6
General-purpose Input/Output 45 (I/O/Z)
-
External Interface Address Line 5 (O)
GPIO46
-
XA6
161 B6 C6
General-purpose Input/Output 46 (I/O/Z)
-
External Interface Address Line 6 (O)
GPIO47
-
XA7
162 A6 D6
General-purpose Input/Output 47 (I/O/Z)
-
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
88 P13 L14
General-purpose Input/Output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (I/O/Z)
GPIO49
ECAP6
XD30
89 N13 L13
General-purpose Input/Output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (I/O/Z)
GPIO50
EQEP1A
XD29
90 P14 L12
General-purpose Input/Output 50 (I/O/Z)
Enhanced QEP1 input A (I)
External Interface Data Line 29 (I/O/Z)
GPIO51
EQEP1B
XD28
91 M13 K14
General-purpose Input/Output 51 (I/O/Z)
Enhanced QEP1 input B (I)
External Interface Data Line 28 (I/O/Z)
GPIO52
EQEP1S
XD27
94 M14 K13
General-purpose Input/Output 52 (I/O/Z)
Enhanced QEP1 Strobe (I/O)
External Interface Data Line 27 (I/O/Z)
GPIO53
EQEP1I
XD26
95 L12 K12
General-purpose Input/Output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (I/O/Z)
GPIO54
SPISIMOA
XD25
96 L13 J14
General-purpose Input/Output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (I/O/Z)
GPIO55
SPISOMIA
XD24
97 L14 J13
General-purpose Input/Output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (I/O/Z)
GPIO56
SPICLKA
XD23
98 K11 J12
General-purpose Input/Output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (I/O/Z)
GPIO57
SPISTEA
XD22
99 K13 H13
General-purpose Input/Output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (I/O/Z)
GPIO58
MCLKRA
XD21
100 K12 H12
General-purpose Input/Output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (I/O/Z)
GPIO59
MFSRA
XD20
110 H14 H11
General-purpose Input/Output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (I/O/Z)
GPIO60
MCLKRB
XD19
111 G14 G12
General-purpose Input/Output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (I/O/Z)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
GPIO61
MFSRB
XD18
112 G12 F14
General-purpose Input/Output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (I/O/Z)
GPIO62
SCIRXDC
XD17
113 G13 F13
General-purpose Input/Output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (I/O/Z)
GPIO63
SCITXDC
XD16
114 G11 F12
General-purpose Input/Output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (I/O/Z)
GPIO64
-
XD15
115 G10 E14
General-purpose Input/Output 64 (I/O/Z)
-
External Interface Data Line 15 (I/O/Z)
GPIO65
-
XD14
116 F14 E13
General-purpose Input/Output 65 (I/O/Z)
-
External Interface Data Line 14 (I/O/Z)
GPIO66
-
XD13
119 F11 E12
General-purpose Input/Output 66 (I/O/Z)
-
External Interface Data Line 13 (I/O/Z)
GPIO67
-
XD12
122 E13 D14
General-purpose Input/Output 67 (I/O/Z)
-
External Interface Data Line 12 (I/O/Z)
GPIO68
-
XD11
123 E11 D13
General-purpose Input/Output 68 (I/O/Z)
-
External Interface Data Line 11 (I/O/Z)
GPIO69
-
XD10
124 F10 D12
General-purpose Input/Output 69 (I/O/Z)
-
External Interface Data Line 10 (I/O/Z)
GPIO70
-
XD9
127 D12 C14
General-purpose Input/Output 70 (I/O/Z)
-
External Interface Data Line 9 (I/O/Z)
GPIO71
-
XD8
128 C14 C13
General-purpose Input/Output 71 (I/O/Z)
-
External Interface Data Line 8 (I/O/Z)
GPIO72
-
XD7
129 B14 B13
General-purpose Input/Output 72 (I/O/Z)
-
External Interface Data Line 7 (I/O/Z)
GPIO73
-
XD6
130 C12 A12
General-purpose Input/Output 73 (I/O/Z)
-
External Interface Data Line 6 (I/O/Z)
GPIO74
-
XD5
131 C13 B12
General-purpose Input/Output 74 (I/O/Z)
-
External Interface Data Line 5 (I/O/Z)
GPIO75
-
XD4
132 A14 C12
General-purpose Input/Output 75 (I/O/Z)
-
External Interface Data Line 4 (I/O/Z)
GPIO76
-
XD3
133 B13 A11
General-purpose Input/Output 76 (I/O/Z)
-
External Interface Data Line 3 (I/O/Z)
GPIO77
-
XD2
134 A13 B11
General-purpose Input/Output 77 (I/O/Z)
-
External Interface Data Line 2 (I/O/Z)
GPIO78
-
XD1
135 B12 C11
General-purpose Input/Output 78 (I/O/Z)
-
External Interface Data Line 1 (I/O/Z)
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
GPIO79
-
XD0
136 A12 B10
General-purpose Input/Output 79 (I/O/Z)
-
External Interface Data Line 0 (I/O/Z)
GPIO80
-
XA8
163 C6 A5
General-purpose Input/Output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9
164 E6 B5
General-purpose Input/Output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
GPIO82
-
XA10
165 C5 C5
General-purpose Input/Output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
GPIO83
-
XA11
168 D5 A4
General-purpose Input/Output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
GPIO84
-
XA12
169 E5 B4 General-purpose Input/Output 84 (I/O/Z)
External Interface Address Line 12 (O)
GPIO85
-
XA13
172 C4 C4
General-purpose Input/Output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
XA14
173 D4 A3
General-purpose Input/Output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
GPIO87
-
XA15
174 A3 B3
General-purpose Input/Output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
XRD 149 B9 A8 External Interface Read Enable
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
7 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
7.1 Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
MIN (1) (2) MAX UNIT
Supply voltage
VDDIO, VDD3VFL with respect to VSS –0.3 4.6
V
VDDA2, VDDAIO with respect to VSSA –0.3 4.6
VDD with respect to VSS –0.3 2.5
VDD1A18, VDD2A18 with respect to VSSA –0.3 2.5
VSSA2, VSSAIO, VSS1AGND, VSS2AGND
with respect to VSS
–0.3 0.3
Input voltage VIN –0.3 4.6 V
Output voltage VO–0.3 4.6 V
Input clamp current IIK (VIN < 0 or VIN > VDDIO)(3) –20 20 mA
Output clamp current IOK (VO < 0 or VO > VDDIO) –20 20 mA
Operating ambient temperature, TA
A version(4) –40 85
°C
S version –40 125
Q version –40 125
Junction temperature TJ (4) –40 150 °C
Storage temperature Tstg (4) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2.
(4) One or both of the following conditions may result in a reduction of overall device life:
long-term high-temperature storage
extended use at maximum temperature
For additional information, see Semiconductor and IC package thermal metrics.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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7.2 ESD Ratings – Automotive
VALUE UNIT
TMS320F2833x, TMS320F2823x in PTP Package
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1) ±2000
V
Charged-device model (CDM), per AEC Q100-011
All pins ±500
Corner pins on 176-pin
PTP: 1, 44, 45, 88, 89,
132, 133, 176
±750
TMS320F2833x, TMS320F2823x in ZJZ Package
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1) ±2000
V
Charged-device model (CDM), per AEC Q100-011
All pins ±500
Corner pins on 176-ball
ZJZ: A1, A14, P1, P14 ±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings – Commercial
VALUE UNIT
TMS320F2833x, TMS320F2823x in PGF Package
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±500
TMS320F2833x, TMS320F2823x in ZHH Package
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO 3.135 3.3 3.465 V
Device supply voltage CPU, VDD
Device operation @ 150 MHz 1.805 1.9 1.995 V
Device operation @ 100 MHz 1.71 1.8 1.89
Supply ground, VSS, VSSIO, VSSAIO,
VSSA2, VSS1AGND, VSS2AGND
0 V
ADC supply voltage (3.3 V),
VDDA2, VDDAIO
3.135 3.3 3.465 V
ADC supply voltage,
VDD1A18, VDD2A18
Device operation @ 150 MHz 1.805 1.9 1.995 V
Device operation @ 100 MHz 1.71 1.8 1.89
Flash supply voltage, VDD3VFL 3.135 3.3 3.465 V
Device clock frequency (system clock),
fSYSCLKOUT
F28335/F28334/F28235/F28234 2 150 MHz
F28333/F28332/F28232 2 100
High-level input voltage, VIH
All inputs except X1 2 VDDIO V
X1 0.7 * VDD – 0.05 VDD
Low-level input voltage, VIL
All inputs except X1 0.8 V
X1 0.3 * VDD + 0.05
High-level output source current,
VOH = 2.4 V, IOH
All I/Os except Group 2 –4 mA
Group 2(1) –8
Low-level output sink current,
VOL = VOL MAX, IOL
All I/Os except Group 2 4 mA
Group 2(1) 8
Ambient temperature, TA
A version –40 85
°CS version –40 125
Q version –40 125
Junction temperature, TJ125 °C
(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, EMU1, XINTF pins, GPIO35-87, XRD.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS
7.5 Power Consumption Summary
7.5.1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
MODE TEST CONDITIONS
IDD IDDIO (1) IDD3VFL (9) IDDA18 (2) IDDA33 (3)
TYP(4) MAX TYP(4) MAX TYP MAX TYP(4) MAX TYP(4) MAX
Operational
(Flash)(6)
The following peripheral clocks
are enabled:
ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6
eCAP1, eCAP2, eCAP3,
eCAP4, eCAP5, eCAP6
eQEP1, eQEP2
• eCAN-A
SCI-A, SCI-B
(FIFO mode)
SPI-A (FIFO mode)
• ADC
• I2C
CPU-Timer 0,
CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at
150 kHz.
All I/O pins are left
unconnected.(5)
290 mA 315 mA 30 mA 50 mA 35 mA 40 mA 30 mA 35 mA 1.5 mA 2 mA
IDLE
Flash is powered down.
XCLKOUT is turned off.
The following peripheral clocks
are enabled:
• eCAN-A
• SCI-A
• SPI-A
• I2C
100 mA 120 mA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
STANDBY Flash is powered down.
Peripheral clocks are off. 8 mA 15 mA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
HALT(8)
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(7)
150 μA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins. To realize the IDDA18 currents shown for IDLE, STANDBY, and HALT, clock to the
ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD =
2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
(5) The following is done in a loop:
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Multiplication/addition operations are performed.
Watchdog is reset.
ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
32-bit read/write of the XINTF is performed.
GPIO19 is toggled.
(6) When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
(8) HALT mode IDD currents will increase with temperature in a nonlinear fashion.
(9) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 7.9.7.3. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS
Note
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time. This is because more than one peripheral function may share an I/O pin.
It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a
configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
7.5.2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
MODE TEST CONDITIONS
IDD IDDIO (1) IDD3VFL (9) IDDA18 (2) IDDA33 (3)
TYP(4) MAX TYP(4) MAX TYP MAX TYP(4) MAX TYP(4) MAX
Operational
(Flash)(6)
The following peripheral
clocks are enabled:
ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6
eCAP1, eCAP2,
eCAP3, eCAP4,
eCAP5, eCAP6
eQEP1, eQEP2
• eCAN-A
SCI-A, SCI-B
(FIFO mode)
SPI-A (FIFO mode)
• ADC
• I2C
CPU-Timer 0,
CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at
150 kHz.
All I/O pins are left
unconnected. (5)
290 mA 315 mA 30 mA 50 mA 35 mA 40 mA 30 mA 35 mA 1.5 mA 2 mA
IDLE
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
• eCAN-A
• SCI-A
• SPI-A
• I2C
100 mA 120 mA 60 μA 120 mA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
STANDBY Flash is powered down.
Peripheral clocks are off. 8 mA 15 mA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
HALT(8)
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(7)
150 μA 60 μA 120 μA 2 μA 10 μA 5 μA 60 μA 15 μA 20 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins. To realize the IDDA18 currents shown for IDLE, STANDBY, and HALT, clock to the
ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD =
2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
(5) The following is done in a loop:
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Multiplication/addition operations are performed.
Watchdog is reset.
ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
32-bit read/write of the XINTF is performed.
GPIO19 is toggled.
(6) When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
(8) HALT mode IDD currents will increase with temperature in a nonlinear fashion.
(9) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 7.9.7.3. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
7.5.3 Reducing Current Consumption
The 2833x and 2823x DSCs incorporate a method to reduce the device current consumption. Because each
peripheral unit has an individual clock-enable bit, reduction in current consumption can be achieved by turning
off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 7-1
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 7-1. Typical Current Consumption by Various
Peripherals (at 150 MHz) (1)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION/MODULE (mA)(2)
ADC 8(3)
I2C 2.5
eQEP 5
ePWM 5
eCAP 2
SCI 5
SPI 4
eCAN 8
McBSP 7
CPU-Timer 2
XINTF 10(4)
DMA 10
FPU 15
(1) All peripheral clocks are disabled upon reset. Writing to or
reading from peripheral registers is possible only after the
peripheral clocks are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for
one ePWM module.
(3) This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA18) as well.
(4) Operating the XINTF bus has a significant effect on IDDIO
current. It will increase considerably based on the following:
How many address/data pins toggle from one cycle to
another
How fast they toggle
Whether 16-bit or 32-bit interface is used and
The load on these pins.
Following are other methods to reduce power consumption further:
The Flash module may be powered down if code is run off SARAM. This results in a current reduction of 35
mA (typical) in the VDD3VFL rail.
• IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Significant savings in IDDIO may be realized by disabling the pullups on pins that assume an output function
and on XINTF pins. A savings of 35 mW (typical) can be achieved by this.
The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 165
mA, (typical). To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled
by that application) must be added to the baseline IDD current.
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
7.5.4 Current Consumption Graphs
IDD IDDIO IDDA18 IDD3VFL 1.8-V Current 3.3-V Current
Figure 7-1. Typical Operational Current Versus Frequency (F28335, F28235, F28334, F28234)
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
Device Power Vs SYSCLKOUT
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
900.0
1000.0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
SYSCLKOUT (MHz)
Device Power (mW)
Figure 7-2. Typical Operational Power Versus Frequency (F28335, F28235, F28334, F28234)
Note
Typical operational current for 100-MHz devices (28x32) can be estimated from Figure 7-1. Compared
to 150-MHz devices, the analog and flash module currents remain unchanged. While a marginal
decrease in IDDIO current can be expected due to the reduced external activity of peripheral pins,
current reduction is primarily in IDD.
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = IOH MAX 2.4 V
IOH = 50 μA VDDIO – 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
IIL
Input current
(low level)
Pin with pullup
enabled VDDIO = 3.3 V, VIN = 0 V All I/Os (including XRS) –80 –140 –190
μA
Pin with pulldown
enabled VDDIO = 3.3 V, VIN = 0 V ±2
IIH
Input current
(high level)
Pin with pullup
enabled VDDIO = 3.3 V, VIN = VDDIO ±2
μA
Pin with pulldown
enabled VDDIO = 3.3 V, VIN = VDDIO 28 50 80
IOZ
Output current, pullup or pulldown
disabled VO = VDDIO or 0 V ±2 μA
CIInput capacitance 2 pF
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
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Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
7.7 Thermal Resistance Characteristics
7.7.1 PGF Package
°C/W(1) (2) AIR FLOW (lfm)(3)
JC Junction-to-case 8.2 0
JB Junction-to-board 28.1 0
JA
(High k PCB) Junction-to-free air
44 0
34.5 150
33 250
31 500
PsiJT Junction-to-package top
0.12 0
0.48 150
0.57 250
0.74 500
PsiJB Junction-to-board
28.1 0
26.3 150
25.9 250
25.2 500
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.7.2 PTP Package
°C/W(1) (2) AIR FLOW (lfm)(3)
JC Junction-to-case 12.1 0
JB Junction-to-board 5.1 0
JA
(High k PCB) Junction-to-free air
17.4 0
11.7 150
10.1 250
8.8 500
PsiJT Junction-to-package top
0.2 0
0.3 150
0.4 250
0.5 500
PsiJB Junction-to-board
5.0 0
4.7 150
4.7 250
4.6 500
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
7.7.3 ZHH Package
°C/W(1) (2) AIR FLOW (lfm)(3)
JC Junction-to-case 8.8 0
JB Junction-to-board 12.5 0
JA
(High k PCB) Junction-to-free air
32.8 0
24.1 150
22.9 250
20.9 500
PsiJT Junction-to-package top
0.09 0
0.3 150
0.36 250
0.48 500
PsiJB Junction-to-board
12.4 0
11.8 150
11.7 250
11.5 500
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.7.4 ZJZ Package
°C/W(1) (2) AIR FLOW (lfm)(3)
JC Junction-to-case 11.4 0
JB Junction-to-board 12 0
JA
(High k PCB) Junction-to-free air
29.6 0
20.9 150
19.7 250
18 500
PsiJT Junction-to-package top
0.2 0
0.78 150
0.91 250
1.11 500
PsiJB Junction-to-board
12.2 0
11.6 150
11.5 250
11.3 500
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
I TEXAS INSTRUMENTS
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems with
more than 1 Watt power dissipation may require a product level thermal design. Care should be taken to keep Tj
within specified limits. In the end applications, Tcase should be measured to estimate the operating junction
temperature Tj. Tcase is normally measured at the center of the package top side surface. The thermal
application note Semiconductor and IC package thermal metrics helps to understand the thermal metrics and
definitions.
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
7.9 Timing and Switching Characteristics
7.9.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don't care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
7.9.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.9.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Transmission Line
4.0 pF 1.85 pF
Z0 = 50 )
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
42 3.5 nH
Device Pin(B)
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-3. 3.3-V Test Load Circuit
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TEXAS INSTRUMENTS
7.9.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Section 7.9.1.3.1 and Section 7.9.1.3.2 list the cycle times of various clocks.
7.9.1.3.1 Clocking and Nomenclature (150-MHz Devices)
MIN NOM MAX UNIT
On-chip oscillator clock tc(OSC), Cycle time 28.6 50 ns
Frequency 20 35 MHz
XCLKIN(1) tc(CI), Cycle time 6.67 250 ns
Frequency 4 150 MHz
SYSCLKOUT tc(SCO), Cycle time 6.67 500 ns
Frequency 2 150 MHz
XCLKOUT tc(XCO), Cycle time 6.67 2000 ns
Frequency 0.5 150 MHz
HSPCLK(2) tc(HCO), Cycle time 6.67 13.3(3) ns
Frequency 75(3) 150 MHz
LSPCLK(2) tc(LCO), Cycle time 13.3 26.7(3) ns
Frequency 37.5(3) 75(4) MHz
ADC clock tc(ADCCLK), Cycle time 40 ns
Frequency 25 MHz
(1) This also applies to the X1 pin if a 1.9-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default value if SYSCLKOUT = 150 MHz.
(4) Although LSPCLK is capable of reaching 100 MHz, it is specified at 75 MHz because the smallest valid "Low-speed peripheral clock
prescaler register" value is "1" for 150-MHz devices.
7.9.1.3.2 Clocking and Nomenclature (100-MHz Devices)
MIN NOM MAX UNIT
On-chip oscillator clock tc(OSC), Cycle time 28.6 50 ns
Frequency 20 35 MHz
XCLKIN(1) tc(CI), Cycle time 10 250 ns
Frequency 4 100 MHz
SYSCLKOUT tc(SCO), Cycle time 10 500 ns
Frequency 2 100 MHz
XCLKOUT tc(XCO), Cycle time 10 2000 ns
Frequency 0.5 100 MHz
HSPCLK(2) tc(HCO), Cycle time 10 20(3) ns
Frequency 50(3) 100 MHz
LSPCLK(2) tc(LCO), Cycle time 10 40(3) ns
Frequency 25(3) 100 MHz
ADC clock tc(ADCCLK), Cycle time 40 ns
Frequency 25 MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default value if SYSCLKOUT = 100 MHz.
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TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS
7.9.2 Power Sequencing
No requirements are placed on the power-up and power-down sequences of the various power pins to ensure
the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of
the I/O pins are powered prior to the 1.9-V/1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or
simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach
0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see Section
7.9.2.2). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V. Meeting this
requirement is important to help prevent unintended flash program or erase.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this
value is 0.7 V above VDDA) before powering up the device. Furthermore, VDDIO and VDDA should always be
within 0.3 V of each other. Voltages applied to pins on an unpowered device can bias internal P-N junctions in
unintended ways and produce unpredictable results.
7.9.2.1 Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to the Power Management page
for a list of TI power management ICs. Click the Reference designs tab for specific power management
reference designs.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
{5‘ TEXAS INSTRUMENTS _/ _/ WM \+/ \+/ \+/\_/ mm \+/ \+/ \+/\_/ mm/ x "3;
tw(RSL1)
th(boot-mode)(B)
VDDIO,VDD3VFL
VDDA2,VDDAIO
(3.3V)
XCLKIN
X1/X2
XRS
Boot-Mode
Pins
VDD,VDD1A18,
VDD2A18
(1.9V/1.8V)
XCLKOUT
I/OPins(C)
User-CodeDependent
User-CodeDependent
Boot-ROMExecutionStarts Peripheral/GPIOFunction
BasedonBootCode
GPIOPinsasInput
OSCCLK/16(A)
GPIOPinsasInput(StateDependsonInternalPU/PD)
tOSCST
User-CodeDependent
Address/Data/
Control
(Internal)
Address/DataValid.InternalBoot-ROMCodeExecutionPhase
User-CodeExecutionPhase
td(EX)
OSCCLK/8
A. Upon power up, SYSCLKOUT is OSCCLK/4. Because both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a
reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/16 during
this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCCLK/2. Because the XTIMCLK register is unchanged by the boot
ROM, XCLKOUT is OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
C. See Section 7.9.2 for requirements to ensure a high-impedance state for GPIO pins during power up.
Figure 7-4. Power-on Reset
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fl TEXAS INSTRUMENTS \ M¥JMJMJU \_/w\+/\+/\+/\_/‘ _/ X/ \ / _f X W X/
7.9.2.2 Reset ( XRS) Timing Requirements
MIN NOM MAX UNIT
tw(RSL1) (1) Pulse duration, stable input clock to XRS high 32tc(OSCCLK) cycles
tw(RSL2) Pulse duration, XRS low Warm reset 32tc(OSCCLK) cycles
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog 512tc(OSCCLK) cycles
td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles
tOSCST (2) Oscillator start-up time 1 10 ms
th(boot-mode) Hold time for boot-mode pins 200tc(OSCCLK) cycles
(1) In addition to the tw(RSL1) requirement, XRS must be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
th(boot-mode)(A)
tw(RSL2)
XCLKIN
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
(Don’t Care)
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input Peripheral/GPIO Function
td(EX)
OSCCLK * 5
OSCCLK/8
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 7-5. Warm Reset
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS
Figure 7-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is
written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating frequency, OSCCLK ×
4.
OSCCLK
SYSCLKOUT
Write to PLLCR
OSCCLK * 2
(Current CPU
Frequency)
OSCCLK/2
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131072 OSCCLK Cycles Long.)
OSCCLK * 4
(Changed CPU Frequency)
Figure 7-6. Example of Effect of Writing Into PLLCR Register
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TEXAS INSTRUMENTS
7.9.3 Clock Requirements and Characteristics
7.9.3.1 Input Clock Frequency
PARAMETER MIN TYP MAX UNIT
fxInput clock frequency
Resonator (X1/X2) 20 35
MHz
Crystal (X1/X2) 20 35
External oscillator/clock
source (XCLKIN or X1 pin)
150-MHz device 4 150
100-MHz device 4 100
flLimp mode SYSCLKOUT frequency range (with /2 enabled) 1 - 5 MHz
7.9.3.2 XCLKIN Timing Requirements – PLL Enabled
NO. MIN MAX UNIT
C8 tc(CI) Cycle time, XCLKIN 33.3 200 ns
C9 tf(CI) Fall time, XCLKIN(1) 6 ns
C10 tr(CI) Rise time, XCLKIN(1) 6 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(CI) (1) 45% 55%
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(CI) (1) 45% 55%
(1) This applies to the X1 pin also.
7.9.3.3 XCLKIN Timing Requirements – PLL Disabled
NO. MIN MAX UNIT
C8 tc(CI) Cycle time, XCLKIN 150-MHz device 6.67 250 ns
100-MHz device 10 250
C9 tf(CI) Fall time, XCLKIN(1) Up to 30 MHz 6 ns
30 MHz to 150 MHz 2
C10 tr(CI) Rise time, XCLKIN(1) Up to 30 MHz 6 ns
30 MHz to 150 MHz 2
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(CI) (1) 45% 55%
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(CI) (1) 45% 55%
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 8-38.
7.9.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO. PARAMETER MIN TYP MAX UNIT
C1 tc(XCO) Cycle time, XCLKOUT 150-MHz device 6.67 ns
100-MHz device 10
C3 tf(XCO) Fall time, XCLKOUT 2 ns
C4 tr(XCO) Rise time, XCLKOUT 2 ns
C5 tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns
C6 tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns
tpPLL lock time 131072tc(OSCCLK) (3) cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
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I TEXAS INSTRUMENTS u p C10 \H’ ca 4 1 ‘ u :+ cs caA‘—H r7 014.1 W F m w w x ‘ x 1 1 H—» 05 \ incl: \ \ H \ XCLKOUTIEVW
7.9.3.5 Timing Diagram
C4
C3
XCLKOUT(B)
XCLKIN(A)
C5
C9
C10
C1
C8
C6
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 7-7. Clock Timing
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7.9.4 Peripherals
7.9.4.1 General-Purpose Input/Output (GPIO)
7.9.4.1.1 GPIO - Output Timing
7.9.4.1.1.1 General-Purpose Output Switching Characteristics
PARAMETER MIN MAX UNIT
tr(GPO) Rise time, GPIO switching low to high All GPIOs 8 ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 8 ns
tfGPO Toggling frequency, GPO pins 25 MHz
GPIO
tr(GPO)
tf(GPO)
Figure 7-8. General-Purpose Output Timing
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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{5‘ TEXAS INSTRUMENTS HHMHMHMMMMH Qualifier
7.9.4.1.2 GPIO - Input Timing
7.9.4.1.2.1 General-Purpose Input Timing Requirements
MIN MAX UNIT
tw(SP) Sampling period QUALPRD = 0 1tc(SCO) cycles
QUALPRD ≠ 0 2tc(SCO) * QUALPRD
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
tw(GPI) (2) Pulse duration, GPIO low/high Synchronous mode 2tc(SCO) cycles
With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
GPIO Signal
1
Sampling Window
Output From
Qualifier
1 1 1111111110000000 000
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))
(A)
GPxQSELn = 1,0 (6 samples)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
(D)
tw(SP)
tw(IQSW)
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7-9. Sampling Mode
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I TEXAS INSTRUMENTS /\_/\+/\_/\_/\_
7.9.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using three samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using six samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
GPIOxn
SYSCLK
tw(GPI)
Figure 7-10. General-Purpose Input Timing
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS Add 955 Dala '(InIe/rnal) X X X X X )C mom WWW/W — WAKE INTKAMM i y
7.9.4.1.4 Low-Power Mode Wakeup Timing
Section 7.9.4.1.4.1 shows the timing requirements, Section 7.9.4.1.4.2 shows the switching characteristics, and
Figure 7-11 shows the timing diagram for IDLE mode.
7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
MIN MAX UNIT
tw(WAKE-INT) Pulse duration, external wake-up signal Without input qualifier 2tc(SCO) cycles
With input qualifier 5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(WAKE-IDLE)
Delay time, external wake signal to
program execution resume (2)
Wake-up from flash
Flash module in active state
Without input qualifier 20tc(SCO) cycles
With input qualifier 20tc(SCO) + tw(IQSW)
Wake-up from flash
Flash module in sleep state
Without input qualifier 1050tc(SCO) cycles
With input qualifier 1050tc(SCO) + tw(IQSW)
Wake-up from SARAM Without input qualifier 20tc(SCO) cycles
With input qualifier 20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
7.9.4.1.4.3 IDLE Mode Timing Diagram
WAKE INT(A)(B)
XCLKOUT
Address/Data
(internal)
td(WAKE−IDLE)
tw(WAKE−INT)
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-11. IDLE Entry and Exit Timing
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Wake-up SignanGw mm or X1m XCLKIN XCLKOUT I TEXAS INSTRUMENTS 4 F ‘ri 4! % a‘ PWH #7 4» p7 4. \ \ K—H Mung—mom
7.9.4.1.4.4 STANDBY Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-INT)
Pulse duration, external
wake-up signal
Without input qualification 3tc(OSCCLK) cycles
With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
7.9.4.1.4.5 STANDBY Mode Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
td(WAKE-STBY)
Delay time, external wake signal to
program execution resume(1)
Wake up from flash
Flash module in active
state
Without input qualifier 100tc(SCO)
cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
Wake up from flash
Flash module in sleep
state
Without input qualifier 1125tc(SCO)
cycles
With input qualifier 1125tc(SCO) + tw(WAKE-INT)
Wake up from SARAM Without input qualifier 100tc(SCO) cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
7.9.4.1.4.6 STANDBY Mode Timing Diagram
tw(WAKE-INT)
td(WAKE-STBY)
td(IDLEXCOL)
Wake-up
Signal(G)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
STANDBY Normal ExecutionSTANDBY
Flushing Pipeline
(A)
(B)
(C)
(D)
(E)
(F)
Device
Status
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to
XINTF is in progress and its access time is longer than this number then it will fail. It is recommended to
enter STANDBY mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
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I TEXAS INSTRUMENTS
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
G. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-12. STANDBY Entry and Exit Timing Diagram
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ITEXAs INSTRUMENTS (mat F Himgd H7 44 k7 1 rimgv} Fangv} ‘P 4‘ xx xx 1 , u Xx \ XI/Xz or XCLKIN JUL
7.9.4.1.4.7 HALT Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) (1) cycles
tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles
(1) See Section 7.9.2.2 for an explanation of toscst.
7.9.4.1.4.8 HALT Mode Switching Characteristics
PARAMETER MIN MAX UNIT
td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tpPLL lock-up time 131072tc(OSCCLK) cycles
td(WAKE-HALT)
Delay time, PLL lock to program execution resume
Wake up from flash
Flash module in sleep state
1125tc(SCO) cycles
Wake up from SARAM 35tc(SCO) cycles
7.9.4.1.4.9 HALT Mode Timing Diagram
td(IDLE−XCOL)
X1/X2
or XCLKIN
XCLKOUT
HALT HALT
Wake-up Latency
Flushing Pipeline
td(WAKE−HALT)
(A)
(B)
(C)
(D)
Device
Status
(E) (G)
(F)
PLL Lock-up Time Normal
Execution
tw(WAKE-GPIO) tp
GPIOn(H)
Oscillator Start-up Time
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off
and the CLKIN to the core is stopped:
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its
access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF access in
progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this
duration even when the PLL is disabled).
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
G. Normal operation resumes.
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-13. HALT Wakeup Using GPIOn
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7.9.4.2 Enhanced Control Peripherals
7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Section 7.9.4.2.1.1 shows the ePWM timing requirements and
Section 7.9.4.2.1.2, ePWM switching characteristics.
7.9.4.2.1.1 ePWM Timing Requirements (1)
MIN MAX UNIT
tw(SYCIN) Sync input pulse width
Asynchronous 2tc(SCO)
cyclesSynchronous 2tc(SCO)
With input qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.1.2 ePWM Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low no pin load 25 ns
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns
7.9.4.2.2 Trip-Zone Input Timing
PWM(B)
TZ(A)
SYSCLK
tw(TZ)
td(TZ-PWM)HZ
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-14. PWM Hi-Z Characteristics
7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
MIN MAX UNIT
tw(TZ) Pulse duration, TZx input low
Asynchronous 1tc(SCO)
cyclesSynchronous 2tc(SCO)
With input qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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TEXAS INSTRUMENTS
7.9.4.2.3 High-Resolution PWM Timing
Section 7.9.4.2.3.1 shows the high-resolution PWM switching characteristics.
7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size(1) 150 310 ps
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
7.9.4.2.4 Enhanced Capture (eCAP) Timing
Section 7.9.4.2.4.1 shows the eCAP timing requirement and Section 7.9.4.2.4.2 shows the eCAP switching
characteristics.
7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
MIN MAX UNIT
tw(CAP) Capture input pulse width
Asynchronous 2tc(SCO)
cyclesSynchronous 2tc(SCO)
With input qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.4.2 eCAP Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns
7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Section 7.9.4.2.5.1 shows the eQEP timing requirement and Section 7.9.4.2.5.2 shows the eQEP switching
characteristics.
7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
MIN MAX UNIT
tw(QEPP) QEP input period Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2[1tc(SCO) + tw(IQSW)]
tw(INDEXH) QEP Index Input High time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
tw(INDEXL) QEP Index Input Low time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
tw(STROBH) QEP Strobe High time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
tw(STROBL) QEP Strobe Input Low time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) Refer to the TMS320F2833x, TMS320F2823x DSC silicon errata for limitations in the asynchronous mode.
7.9.4.2.5.2 eQEP Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles
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PARAMETER TEST CONDITIONS MIN MAX UNIT
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync
output 6tc(SCO) cycles
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
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I TEXAS INSTRUMENTS 9"’3’?3‘3’3%‘3‘3’3’3’3‘3’3’3’3‘3:o
7.9.4.2.6 ADC Start-of-Conversion Timing
7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO )cycles
7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
ADCSOCAO
or
ADCSOCBO
tw(ADCSOCL)
Figure 7-15. ADCSOCAO or ADCSOCBO Timing
7.9.4.3 External Interrupt Timing
7.9.4.3.1 External Interrupt Timing Requirements (1)
MIN MAX UNIT
tw(INT) (2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles
With qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
7.9.4.3.2 External Interrupt Switching Characteristics (1)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.3.3 External Interrupt Timing Diagram
XNMI, XINT1, XINT2
tw(INT)
Interrupt Vector
td(INT)
Address bus
(internal)
Figure 7-16. External Interrupt Timing
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7.9.4.4 I2C Electrical Specification and Timing
7.9.4.4.1 I2C Timing
TEST CONDITIONS MIN MAX UNIT
fSCL SCL clock frequency
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
400 kHz
vil Low level input voltage 0.3 VDDIO V
Vih High level input voltage 0.7 VDDIO V
Vhys Input hysteresis 0.05 VDDIO V
Vol Low level output voltage 3-mA sink current 0 0.4 V
tLOW Low period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3 μs
tHIGH High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6 μs
lI
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX –10 10 μA
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
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7.9.4.5 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
7.9.4.5.1 Master Mode Timing
Section 7.9.4.5.1.1 lists the master mode timing (clock phase = 0) and Section 7.9.4.5.1.2 lists the master mode
timing (clock phase = 1). Figure 7-17 and Figure 7-18 show the timing waveforms.
7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO. PARAMETER BRR EVEN BRR ODD UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns
2 tw(SPC1)M
Pulse duration, SPICLK first
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10 ns
3 tw(SPC2)M
Pulse duration, SPICLK second
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
0.5tc(LSPCLK) + 10 ns
4 td(SIMO)M
Delay time, SPICLK to
SPISIMO valid 10 10 ns
5 tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10 ns
8 tsu(SOMI)M
Setup time, SPISOMI before
SPICLK 35 35 ns
9 th(SOMI)M
Hold time, SPISOMI valid after
SPICLK 0 0 ns
23 td(SPC)M
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
3tc(SYSCLK) – 10
1.5tc(SPC)M
3tc(SYSCLK) – 10 ns
24 td(STE)M
Delay time, SPICLK to SPISTE
inactive 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10 ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
8
Master Out Data Is Valid
3
2
1
SPISTE
5
23 24
Figure 7-17. SPI Master Mode External Timing (Clock Phase = 0)