AD9694 Datasheet by Analog Devices Inc.

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ANALOG DEVICES A09694 AA JL i E uuuuuuuuuuuuuuuuuuuuu
14-Bit, 500 MSPS, JESD204B,
Quad Analog-to-Digital Converter
Data Sheet
AD9694
Rev. B Document Feedback
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Technical Support www.analog.com
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 15 Gbps
1.66 W total power at 500 MSPS
415 mW per ADC channel
SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)S
SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range)
Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)
0.975 V, 1.8 V, and 2.5 V dc supply operation
No missing codes
Internal ADC voltage reference
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
1.4 GHz analog input full power bandwidth
Amplitude detect bits for efficient AGC implementation
4 integrated wideband digital processors
48-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, W-CDMA, GSM, LTE, LTE-A
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
FUNCTIONAL BLOCK DIAGRAM
SDIO SCLK CSB
AGND
AD9694
SERDOUTAB0±
SYSREF±
14
SPI CONTROL
14
2
PDWN/STBY
JESD204B
SUBCLASS 1
CONTROL
FAST
DETECT SERDOUTAB1±
VIN+B
VIN–B
ADC
CORE
ADC
CORE
SIGNAL
MONITOR
SYNCINB±AB
VIN+C
VIN–C
FD_C
FD_D
SERDOUTCD0±
SERDOUTCD1±
VIN+D
VIN–D
Tx
OUTPUTS
JESD204B
HIGH SPEED
SERIALIZER
SYNCINB±CD
AVDD1
(0.975V) AVDD2
(1.8V) DRVDD1
(0.975V)
DVDD
(0.975V)
AVDD3
(2.5V)
AVDD1_SR
(0.975V) SPIVDD
(1.8V)
DRVDD2
(1.8V)
DIGITAL DOWN
CONVERTER
(DDC)
DIGITAL DOWN
CONVERTER
(DDC)
2
Tx
OUTPUTS
JESD204B
HIGH SPEED
SERIALIZER
AGND_SR
VIN+A
VIN–A
FD_A
FD_B
14
14
FAST
DETECT
ADC
CORE
ADC
CORE
SIGNAL
MONITOR
DIGITAL DOWN-
CONVERTER
(DDC)
DIGITAL DOWN-
CONVERTER
(DDC)
SIGNAL
MONITOR
AND FAST
DETECT
14808-001
CLK+
CLK–
CLOCK
GENERATION
÷2
÷4
÷8
BUFFER
BUFFER
BUFFER
BUFFER
DRGND
VCM_AB
VCM_CD/VREF
Figure 1.
AD9694 Data Sheet
Rev. B | Page 2 of 96
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Product Highlights ........................................................................... 4
Specifications ..................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications .......................................................................... 6
Digital Specifications ................................................................... 9
Switching Specifications ............................................................ 10
Timing Specifications ................................................................ 11
Absolute Maximum Ratings .......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution ................................................................................ 12
Pin Configuration and Function Descriptions ........................... 13
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 22
Theory of Operation ...................................................................... 24
ADC Architecture ...................................................................... 24
Analog Input Considerations .................................................... 24
Voltage Reference ....................................................................... 25
DC Offset Calibration ................................................................ 26
Clock Input Considerations ...................................................... 26
ADC Overrange and Fast Detect .................................................. 29
ADC Overrange .......................................................................... 29
Fast Threshold Detection (FD_A, FD_B, FD_C, and
FD_D) .......................................................................................... 29
Signal Monitor ................................................................................ 30
SPORT Over JESD204B ............................................................. 30
Digital Downconverter (DDC) ..................................................... 33
DDC I/Q Input Selection .......................................................... 33
DDC I/Q Output Selection ....................................................... 33
DDC General Description ........................................................ 33
Frequency Translation ................................................................... 39
Overview ...................................................................................... 39
DDC NCO and Mixer Loss and SFDR .................................... 40
Numerically Controlled Oscillator ........................................... 40
FIR Filters ........................................................................................ 42
Overview ...................................................................................... 42
Half-Band Filters ........................................................................ 43
DDC Gain Stage ......................................................................... 44
DDC Complex to Real Conversion ......................................... 44
DDC Example Configurations ................................................. 45
Digital Outputs ............................................................................... 50
Introduction to the JESD204B Interface ................................. 50
Setting Up the AD9694 Digital Interface ................................ 50
Functional Overview ................................................................. 52
JESD204B Link Establishment ................................................. 52
Physical Layer (Driver) Outputs .............................................. 53
JESD204B Tx Converter Mapping ........................................... 54
Configuring the JESD204B Link .............................................. 56
Latency ............................................................................................. 60
End to End Total Latency .......................................................... 60
Example Latency Calculations.................................................. 60
LMFC referenced Latency ......................................................... 60
Deterministic Latency .................................................................... 61
Subclass 0 Operation .................................................................. 61
Subclass 1 Operation .................................................................. 61
Multichip Synchronization ............................................................ 63
Normal Mode .............................................................................. 63
Timestamp Mode ....................................................................... 63
SYSREF± Input ........................................................................... 65
SYSREF± Setup/Hold Window Monitor ................................. 66
Test Modes ....................................................................................... 68
ADC Test Modes ........................................................................ 68
JESD204B Block Test Modes .................................................... 69
Serial Port Interface ........................................................................ 71
Configuration Using the SPI ..................................................... 71
Hardware Interface ..................................................................... 71
SPI Accessible Features .............................................................. 71
Memory Map .................................................................................. 72
Reading the Memory Map Register Table ............................... 72
Memory Map Register TableDetails .................................... 73
Applications Information .............................................................. 95
Power Supply Recommendations ............................................. 95
Exposed Pad Thermal Heat Slug Recommendations ............ 95
AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) ... 95
Outline Dimensions ....................................................................... 96
Ordering Guide .......................................................................... 96
Data Sheet AD9694
Rev. B | Page 3 of 96
REVISION HISTORY
2/2018—Rev. A to Rev. B
Changed Document Title from Dual 14-Bit, 1.25 GSPS, 1.2 V/
2.5 V Analog-to-Digital Converter to 14-Bit, 500 MSPS,
JESD204B Analog-to-Digital Converter ......................... Universal
Change to Table 10 .......................................................................... 14
Moved Temperature Diode Section .............................................. 28
12/2017—Rev. 0 to Rev. A
Changed 1.8 V p-p to 1.80 V p-p ................................ Throughout
Changes to Figure 1 ........................................................................... 1
Changes to Endnote 3, Table 2 ........................................................ 7
Changes to Logic Outputs (FD_A, FD_B, FD_C, FD_D)
Parameter and DIGITAL OUTPUTS (SERDOUTABx±/
SERDOUTCDx±, x = 0 OR 1) Parameter, Table 5 ....................... 9
Changes to Output Parameter and Wake-Up Time Parameter,
Table 6 ............................................................................................... 10
Changes to Table 9 .......................................................................... 12
Changes to Table 10 ........................................................................ 13
Changes to Figure 18, Figure 19, Figure 20, and Figure 23 ....... 17
Changes to Figure 47 and Figure 48 ............................................. 22
Changes to Analog Input Considerations Section and
Differential Input Configurations Section ................................... 24
Changes to Table 11 ........................................................................ 25
Changes to Voltage Reference Section, DC Offset Calibration
Section, and Figure 62 .................................................................... 26
Changes to Clock Duty Cycle Considerations Section and
Figure 65 ........................................................................................... 27
Added Input Clock Detect Section ............................................... 27
Changes to Temperature Diode Section ....................................... 28
Changed General Description Section to Overview Section .... 39
Changes to Overview Section ........................................................ 42
Change to Phase-Locked Loop (PLL) Section ............................ 54
Change to Table 26 .......................................................................... 56
Changes to Table 27 ........................................................................ 57
Changes to Example 2: ADC with DDC Option (Two ADCs
Plus Two DDCs in Each Pair Section and Figure 92 .................. 58
Added Example Latency Calculations Section, Example
Configuration 1 Section, Example Configuration 2 Section,
Table 29, and Table 30; Renumbered Sequentially ..................... 60
Added Deterministic Latency Section, Subclass 0 Operation
Section, Subclass 1 Operation Section, Deterministic Latency
Requirements Section, Setting Deterministic Latency Registers
Section, and Figure 94; Renumbered Sequentially ..................... 61
Added Figure 95 and Figure 96 ..................................................... 62
Added Multichip Synchronization Section, Normal Mode
Section, Timestamp Mode Section, Figure 97 ............................. 63
Added Figure 98 .............................................................................. 64
Added SYSREF± Input Section, SYSREF± Control Features
Section, Figure 99, Figure 100, Figure 101, and Figure 102 ...... 65
Changes to SYSREF± Setup/Hold Window Monitor Section ... 66
Changes to ADC Test Modes Section .......................................... 68
Deleted Register Table Summary Section and Table 38;
Renumbered Sequentially ...................................................................... 69
Changes to Reading the Memory Map Register Table Section ....... 72
Changes to Table 39 ........................................................................ 73
Changes to Power Supply Recommendations Section and
Figure 106 ......................................................................................... 95
10/2016—Revision 0: Initial Version
AD9694 Data Sheet
Rev. B | Page 4 of 96
GENERAL DESCRIPTION
The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital
converter (ADC). The device has an on-chip buffer and a
sample-and-hold circuit designed for low power, small size, and
ease of use. This device is designed for sampling wide bandwidth
analog signals of up to 1.4 GHz. The AD9694 is optimized for
wide input bandwidth, high sampling rate, excellent linearity,
and low power in a small package.
The quad ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The analog inputs and clock signals are differential inputs. Each
pair of ADC data outputs is internally connected to two DDCs
through a crossbar mux. Each DDC consists of up to five cascaded
signal processing stages: a 48-bit frequency translator, NCO,
and up to four half-band decimation filters.
In addition to the DDC blocks, the AD9694 has several
functions that simplify the automatic gain control (AGC)
function in the communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
Users can configure each pair of intermediate frequency (IF)
receiver outputs onto either one or two lanes of Subclass 1
JESD204B-based high speed serialized outputs, depending on
the decimation ratio and the acceptable lane rate of the receiving
logic device. Multiple device synchronization is supported through
the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.
The AD9694 has flexible power-down options that allow significant
power savings when desired. All of these features can be pro-
grammed using the 1.8 V capable, 3-wire SPI.
The AD9694 is available in a Pb-free, 72-lead LFCSP and is
specified over the 40°C to +105°C junction temperature range.
This product may be protected by one or more U.S. or
international patents.
PRODUCT HIGHLIGHTS
1. Low power consumption per channel.
2. JESD204B lane rate support up to 15 Gbps.
3. Wide full power bandwidth supports IF sampling of signals
up to 1.4 GHz.
4. Buffered inputs ease filter design and implementation.
5. Four integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
6. Programmable fast overrange detection.
7. On-chip temperature diode for system thermal management.
Data Sheet AD9694
Rev. B | Page 5 of 96
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default
SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error 0 % FSR
Offset Matching 0 % FSR
Gain Error −5.0 +5.0 % FSR
Gain Matching 1.0 3.7 % FSR
Differential Nonlinearity (DNL) −0.7 ±0.4 +0.7 LSB
Integral Nonlinearity (INL) −5.1 ±1.0 +5.1 LSB
TEMPERATURE DRIFT
Offset Error 8 ppm/°C
Gain Error 214 ppm/°C
INTERNAL VOLTAGE REFERENCE 0.5 V
INPUT REFERRED NOISE 2.6 LSB rms
ANALOG INPUTS
Differential Input Voltage Range (Programmable)
1.44
2.16
V p-p
Common-Mode Voltage (VCM) 1.34 V
Differential Input Capacitance1 1.75 pF
Differential Input Resistance 200
Analog Input Full Power Bandwidth 1.4 GHz
POWER SUPPLY
AVDD1 0.95 0.975 1.00 V
AVDD1_SR 0.95 0.975 1.00 V
AVDD2
1.71
1.89
V
AVDD3 2.44 2.5 2.56 V
DVDD 0.95 0.975 1.00 V
DRVDD1 0.95 0.975 1.00 V
DRVDD2 1.71 1.8 1.89 V
SPIVDD 1.71 1.8 1.89 V
IAVDD1 319 482 mA
IAVDD1_SR 21 53 mA
IAVDD2 438 473 mA
IAVDD3 87 103 mA
IDVDD2 121 180 mA
IDRVDD11 162 207 mA
IDRVDD21 23 29 mA
ISPIVDD 1 1.6 mA
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)2 1.66 2.07 W
Power-Down Dissipation 325 mW
Standby3 1.20 W
1 All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.
2 Full bandwidth mode.
3 Standby mode is controlled by the SPI.
AD9694 Data Sheet
Rev. B | Page 6 of 96
AC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference,
AIN = −1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full
operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 2. 500 MSPS AC Specifications
Analog Input Full Scale =
1.44 V p-p
Analog Input Full Scale =
1.80 V p-p
Analog Input Full Scale =
2.16 V p-p
Parameter1 Min Typ Max Min Typ Max Min Typ Max Unit
ANALOG INPUT FULL SCALE 1.44 1.80 2.16 V p-p
NOISE DENSITY2 −149.7 −151.5 −153.0 dBFS/Hz
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 10 MHz 65.4 67.1 68.4 dBFS
fIN = 155 MHz 65.3 64.8 67.0 68.3 dBFS
fIN = 305 MHz 65.2 66.8 68.0 dBFS
fIN = 450 MHz 65.0 66.6 67.8 dBFS
fIN = 765 MHz 64.8 66.5 67.5 dBFS
fIN = 985 MHz 64.5 66.0 66.9 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
fIN = 10 MHz 65.3 67.0 68.2 dBFS
fIN = 155 MHz 65.2 64.5 66.8 67.9 dBFS
fIN = 305 MHz 65.1 66.6 67.6 dBFS
fIN = 450 MHz 65.0 66.4 67.3 dBFS
fIN = 765 MHz 64.7 66.1 66.9 dBFS
fIN = 985 MHz 64.2 65.5 66.2 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz 10.5 10.8 11.0 Bits
fIN = 155 MHz 10.5 10.4 10.8 10.9 Bits
fIN = 305 MHz 10.5 10.7 10.9 Bits
fIN = 450 MHz 10.5 10.7 10.8 Bits
fIN = 765 MHz 10.4 10.6 10.8 Bits
fIN = 985 MHz 10.3 10.6 10.7 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz 89 90 80 dBFS
fIN = 155 MHz 89 75 85 77 dBFS
fIN = 305 MHz 82 82 78 dBFS
fIN = 450 MHz 82 83 77 dBFS
fIN = 765 MHz 77 75 72 dBFS
fIN = 985 MHz 82 79 76 dBFS
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
AT −3 dBFS
fIN = 10 MHz 94 94 86 dBFS
fIN = 155 MHz 94 90 82 dBFS
fIN = 305 MHz 89 90 83 dBFS
fIN = 450 MHz 87 86 84 dBFS
fIN = 765 MHz 82 80 77 dBFS
fIN = 985 MHz 85 82 79 dBFS
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz 89 −90 80 dBFS
fIN = 155 MHz −89 −85 −75 −77 dBFS
fIN = 305 MHz 82 −82 78 dBFS
fIN = 450 MHz 82 −83 77 dBFS
fIN = 765 MHz 77 −75 72 dBFS
fIN = 985 MHz 82 −79 76 dBFS
Data Sheet AD9694
Rev. B | Page 7 of 96
Analog Input Full Scale =
1.44 V p-p
Analog Input Full Scale =
1.80 V p-p
Analog Input Full Scale =
2.16 V p-p
Parameter1 Min Typ Max Min Typ Max Min Typ Max Unit
WORST HARMONIC, SECOND OR THIRD AT
−3 dBFS
fIN = 10 MHz 94 −94 86 dBFS
f
IN
= 155 MHz
−94
−90
−82
dBFS
fIN = 305 MHz 89 −90 83 dBFS
fIN = 450 MHz 87 −86 84 dBFS
fIN = 765 MHz 82 −80 77 dBFS
fIN = 985 MHz 85 −82 79 dBFS
WORST OTHER, EXCLUDING SECOND OR
THIRD HARMONIC
fIN = 10 MHz 96 −98 99 dBFS
fIN = 155 MHz −97 −97 −86 −97 dBFS
fIN = 305 MHz 97 −98 97 dBFS
fIN = 450 MHz 95 −96 96 dBFS
fIN = 765 MHz 92 −91 88 dBFS
fIN = 985 MHz 90 −89 86 dBFS
TWO-TONE INTERMODULATION
DISTORTION (IMD), AIN1 AND AIN2 =
−7 dBFS
fIN1 = 154 MHz, fIN2 = 157 MHz −93 −90 −84 dBFS
fIN1 = 302 MHz, fIN2 = 305 MHz −90 −90 −84 dBFS
CROSSTALK4 82 82 82 dB
FULL POWER BANDWIDTH5 1.4 1.4 1.4 GHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Noise density is measured at a low analog input frequency (30 MHz).
3 See Table 11 for recommended settings for the buffer current setting.
4 Crosstalk is measured at 155 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.
5 Measured with the circuit shown in Figure 56.
Table 3. 600 MSPS AC Specifications, Analog Input = 1.80 V p-p
Parameter1 Min Typ Max Unit
ANALOG INPUT FULL SCALE 1.80 V p-p
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz 66.6 dBFS
fIN = 155 MHz 67 dBFS
f
IN
= 305 MHz
66.8
dBFS
fIN = 450 MHz 66.4 dBFS
fIN = 765 MHz 66 dBFS
fIN = 985 MHz 65.5 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 10 MHz 66.5 dBFS
fIN = 155 MHz 66.8 dBFS
fIN = 305 MHz 66.5 dBFS
fIN = 450 MHz 66.3 dBFS
fIN = 765 MHz 65.4 dBFS
fIN = 985 MHz 64.8 dBFS
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz 86 dBFS
fIN = 155 MHz 81 dBFS
fIN = 305 MHz 81 dBFS
fIN = 450 MHz 84 dBFS
fIN = 765 MHz 76 dBFS
fIN = 985 MHz 75 dBFS
AD9694 Data Sheet
Rev. B | Page 8 of 96
Parameter1 Min Typ Max Unit
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz 86 dBFS
fIN = 155 MHz 81 dBFS
fIN = 305 MHz 81 dBFS
fIN = 450 MHz 84 dBFS
fIN = 765 MHz 76 dBFS
fIN = 985 MHz 75 dBFS
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Table 4. 600 MSPS Power Consumption
Parameter Min Typ Max Unit
POWER SUPPLY
AVDD1 0.95 0.975 1.00 V
AVDD1_SR 0.95 0.975 1.00 V
AVDD2
1.71
1.8
1.89
V
AVDD3 2.44 2.5 2.56 V
DVDD 0.95 0.975 1.00 V
DRVDD1 0.95 0.975 1.00 V
DRVDD2 1.71 1.8 1.89 V
SPIVDD 1.71 1.8 1.89 V
IAVDD1 352 513 mA
IAVDD1_SR 23 55 mA
IAVDD2 443 478 mA
IAVDD3 87 104 mA
IDVDD1 146 200 mA
IDRVDD1 2 183 235 mA
IDRVDD22 23 28 mA
ISPIVDD 1 1.6 mA
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers) 1.75 2.16 W
1 Full bandwidth mode.
2 All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.
Data Sheet AD9694
Rev. B | Page 9 of 96
DIGITAL SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default
SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 5.
Parameter Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance LVDS/LVPECL
Differential Input Voltage 600 800 1600 mV p-p
Input Common-Mode Voltage 0.69 V
Input Resistance (Differential) 32 kΩ
Input Capacitance
0.9
pF
SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−)1
Logic Compliance LVDS/LVPECL
Differential Input Voltage 400 800 1800 mV p-p
Input Common-Mode Voltage 0.6 0.69 2.2 V
Input Resistance (Differential) 18 22 kΩ
Input Capacitance (Single-Ended per Pin) 0.7 pF
LOGIC INPUTS (PDWN/STBY)
Logic Compliance CMOS
Logic 1 Voltage 0.65 × SPIVDD V
Logic 0 Voltage 0 0.35 × SPIVDD V
Input Resistance 10 MΩ
LOGIC INPUTS (SDIO, SCLK, CSB)
Logic Compliance CMOS
Logic 1 Voltage 0.65 × SPIVDD V
Logic 0 Voltage 0 0.35 × SPIVDD V
Input Resistance 56 kΩ
LOGIC OUTPUT (SDIO)
Logic Compliance CMOS
Logic 1 Voltage (IOH = 800 µA) SPIVDD − 0.45 V V
Logic 0 Voltage (IOL = 50 µA) 0 0.45 V
SYNCIN INPUT (SYNCINB+AB/SYNCINB−AB/
SYNCINB+CD/SYNCINB−CD)
Logic Compliance LVDS/LVPECL/CMOS
Differential Input Voltage 400 800 1800 mV p-p
Input Common-Mode Voltage 0.6 0.69 2.2 V
Input Resistance (Differential) 18 22 kΩ
Input Capacitance (Single Ended per Pin) 0.7 pF
LOGIC OUTPUTS (FD_A, FD_B, FD_C, FD_D)
Logic Compliance CMOS
Logic 1 Voltage 0.8 × SPIVDD V
Logic 0 Voltage
0
0.5
V
Input Resistance 56 kΩ
DIGITAL OUTPUTS (SERDOUTAB/SERDOUTCD, x = 0 OR 1)
Logic Compliance CML
Differential Output Voltage
455.8
mV p-p
Short-Circuit Current (ID SHORT) 15 mA
Differential Termination Impedance 100
1 DC-coupled input only.
AD9694 Data Sheet
Rev. B | Page 10 of 96
SWITCHING SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default
SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 6.
Parameter Min Typ Max Unit
CLOCK
Clock Rate (at CLK+/CLK− Pins) 0.3 2.4 GHz
Maximum Sample Rate1 600 MSPS
Minimum Sample Rate
2
240
MSPS
Clock Pulse Width High 125 ps
Clock Pulse Width Low 125 ps
OUTPUT
Unit Interval (UI)3 66.67 100 593 ps
Rise Time (tR) (20% to 80% into 100 Ω Load) 31.25 ps
Fall Time (tF) (20% to 80% into 100 Ω Load) 31.37 ps
PLL Lock Time 5 ms
Data Rate per Channel (Nonreturn-to-Zero (NRZ))4
1.6875
10
15
Gbps
LATENCY5
Pipeline Latency 54 Sample clock cycles
Fast Detect Latency
30
Sample clock cycles
WAKE-UP TIME
From Standby 3 ms
From Power-Down
10
ms
APERTURE
Aperture Delay (tA) 160 ps
Aperture Uncertainty (Jitter, t
j
)
44
fs rms
Out of Range Recovery Time 1 Sample clock cycles
1 The maximum sample rate is the clock rate after the divider.
2 The minimum sample rate operates at 240 MSPS with L = 2 or L = 1. See SPI Register 0x011A to reduce the threshold of the clock detection circuit.
3 Baud rate = 1/UI. A subset of this range can be supported.
4 Default L = 2 for each link. This number can be changed based on the sample rate and decimation ratio.
5 No DDCs used. L = 2, M = 2, F = 2 for each link.
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Data Sheet AD9694
Rev. B | Page 11 of 96
TIMING SPECIFICATIONS
Table 7.
Parameter Test Conditions/Comments Min Typ Max Unit
CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 3
tSU_SR Device clock to SYSREF+ setup time −44.8 ps
tH_SR Device clock to SYSREF+ hold time 64.4 ps
SPI TIMING REQUIREMENTS See Figure 4
tDS Setup time between the data and the rising edge of SCLK 4 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
tCLK Period of the SCLK 40 ns
t
S
Setup time between CSB and SCLK
2
ns
tH Hold time between CSB and SCLK 2 ns
tHIGH Minimum period that SCLK must be in a logic high state 10 ns
tLOW Minimum period that SCLK must be in a logic low state 10 ns
tACCESS Maximum time delay between falling edge of SCLK and output
data valid for a read operation
6 10 ns
tDIS_SDIO Time required for the SDIO pin to switch from an output to an
input relative to the CSB rising edge (not shown in Figure 4)
10 ns
Timing Diagrams
N – 53
N – 52 N – 51 N – 50 N – 1
SAMPLE N
N + 1
APERTURE
DELAY
N 54
CLK+
CLK–
ANALOG
INPUT
SIGNAL
14808-002
Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4, M = 2, F = 1)
CLK+
CLK–
SYSREF+
SYSREF–
t
SU_SR
t
H_SR
14808-003
Figure 3. SYSREF± Setup and Hold Timing
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
SDIO
SCLK
t
S
t
DH
t
CLK
t
DS
t
ACCESS
t
H
R/W A14 A13 A12 A11 A10 A9 A8 A7 D7 D6 D3 D2 D1 D0
t
LOW
t
HIGH
CSB
14808-004
Figure 4. Serial Port Interface Timing Diagram
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AD9694 Data Sheet
Rev. B | Page 12 of 96
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
Electrical
AVDD1 to AGND
1.05 V
AVDD1_SR to AGND 1.05 V
AVDD2 to AGND 2.00 V
AVDD3 to AGND 2.70 V
DVDD to DGND 1.05 V
DRVDD1 to DRGND 1.05 V
DRVDD2 to DRGND
2.00 V
SPIVDD to AGND 2.00 V
VIN±x to AGND −0.3 V to AVDD3 + 0.3 V
CLK± to AGND −0.3 V to AVDD1 + 0.3 V
SCLK, SDIO, CSB to DGND −0.3 V to SPIVDD + 0.3 V
PDWN/STBY to DGND −0.3 V to SPIVDD + 0.3 V
SYSREF± to AGND_SR
0 V to 2.5 V
SYNCINB±AB/SYNCINB±CD to
DRGND
0 V to 2.5 V
Environmental
Operating Junction Temperature
Range
−40°C to +105°C
Maximum Junction Temperature 125°C
Storage Temperature Range
(Ambient)
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC_BOT is the bottom junction to case thermal resistance.
Table 9. Thermal Resistance
PCB Type Airflow Velocity (m/sec) θJA θJC_BOT Unit
JEDEC
2s2p Board
0.0 21.581, 2 1.951, 4 °C/W
1.0 17.941, 2 N/A3 °C/W
2.5 16.581, 2 N/A3 °C/W
10-Layer Board 0.0 9.74 1.00 °C/W
1 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 N/A means not applicable.
4 Per MIL-STD 883, Method 1012.1.
ESD CAUTION
AD9694 10:: VIEW mm to Scam
Data Sheet AD9694
Rev. B | Page 13 of 96
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. EXPOSED PAD. ANALOG GROUND. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE GROUND REFERENCE FOR AVDDx, SPIVDD, DVDD, DRVDD1, AND DRVDD2.
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD3
VIN–A
VIN+A
AVDD2
AVDD2
AVDD3
VIN+B
VIN–B
AVDD2
AVDD1
AVDD1
VCM_AB
DVDD
DGND
DRVDD2
PDWN/STBY17FD_A18FD_B
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
SYNCINB–AB
SYNCINB+AB
DRGND
DRVDD1
SERDOUTAB0–
SERDOUTAB0+
SERDOUTAB1–
SERDOUTAB1+
SERDOUTCD1+
SERDOUTCD1–
SERDOUTCD0+
SERDOUTCD0–
DRVDD1
SYNCINB+CD
SYNCINB–CD
DRGND
35FD_D 36FD_C
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
AVDD3
VIN–C
VIN+C
AVDD2
AVDD2
AVDD3
VIN+D
VIN–D
AVDD2
AVDD1
AVDD1
VCM_CD/VREF
DVDD
DGND
SPIVDD
CSB
SCLK
SDIO
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD2
AVDD1
AVDD1
AVDD1
AVDD1
AGND_SR
SYSREF–
SYSREF+
AVDD1_SR
AGND_SR
AVDD1
CLK–
CLK+
AVDD1
AVDD1
AVDD1
AVDD1
AVDD2
AD9694
TOP VIEW
(Not to Scale)
14808-005
Figure 5. Pin Configuration (Top View)
Table 10. Pin Function Descriptions
Pin No. Mnemonic Type Description
0 AGND/EPAD Ground Exposed Pad. Analog Ground. The exposed thermal pad on
the bottom of the package provides the ground reference for
AVDDx, SPIVDD, DVDD, DRVDD1, and DRVDD2. This exposed
pad must be connected to ground for proper operation.
1, 6, 49, 54
AVDD3
Supply
Analog Power Supply (2.5 V Nominal).
2, 3 VIN−A, VIN+A Input ADC A Analog Input Complement/True.
4, 5, 9, 46, 50, 51, 55, 72 AVDD2 Supply Analog Power Supply (1.8 V Nominal).
7, 8 VIN+B, VIN−B Input ADC B Analog Input True/Complement.
10, 11, 44, 45, 56, 57, 58, 59,
62, 68, 69, 70, 71
AVDD1 Supply Analog Power Supply (0.975 V Nominal).
12 VCM_AB Output Common-Mode Level Bias Output for Analog Input Channel A
and Channel B.
13, 42 DVDD Supply Digital Power Supply (0.975 V Nominal).
14, 41 DGND Ground Ground Reference for DVDD and SPIVDD.
15 DRVDD2 Supply Digital Power Supply for JESD204B PLL (1.8 V Nominal).
16 PDWN/STBY Input Power-Down Input/Standby (Active High). The operation of
this pin depends on the SPI mode and can be configured as
power-down or standby. This pin requires external 10 kΩ pull-
down resistor.
17, 18, 35, 36 FD_A, FD_B, FD_D, FD_C Output Fast Detect Outputs for Channel A, Channel B, Channel C, and
Channel D.
19 SYNCINB−AB Input Active Low JESD204B LVDS Sync Input Complement for
Channel A and Channel B.
20 SYNCINB+AB Input Active Low JESD204B LVDS/CMOS Sync Input True for Channel A
and Channel B.
AD9694 Data Sheet
Rev. B | Page 14 of 96
Pin No. Mnemonic Type Description
21, 32 DRGND Ground Ground Reference for DRVDD1 and DRVDD2.
22, 31 DRVDD1 Supply Digital Power Supply for SERDOUTABx±/SERDOUTCDx± Pins
(0.975 V Nominal).
23, 24 SERDOUTAB0−,
SERDOUTAB0+
Output Lane 0 Output Data Complement/True for Channel A and
Channel B.
25, 26 SERDOUTAB1−,
SERDOUTAB1+
Output Lane 1 Output Data Complement/True for Channel A and
Channel B.
27, 28 SERDOUTCD1+,
SERDOUTCD1−
Output Lane 1 Output Data True/Complement for Channel C and
Channel D.
29, 30 SERDOUTCD0+,
SERDOUTCD0−
Output Lane 0 Output Data True/Complement for Channel C and
Channel D.
33 SYNCINB+CD Input
Active Low JESD204B LVDS/CMOS/LVPECL Sync Input True for
Channel C and Channel D.
34 SYNCINB−CD Input
Active Low JESD204B LVDS/CMOS/LVPECL Sync Input
Complement for Channel C and Channel D.
37 SDIO Input/output SPI Serial Data Input/Output.
38 SCLK Input SPI Serial Clock.
39 CSB Input SPI Chip Select (Active Low).
40 SPIVDD Supply Digital Power Supply for SPI (1.8 V Nominal).
43 VCM_CD/VREF Output/input
Common-Mode Level Bias Output for Analog Input Channel C
and Channel D/0.5 V Reference Voltage Input. This pin is
configurable through the SPI as an output or an input. Use
this pin as the common-mode level bias output if using the
internal reference. This pin requires a 0.5 V reference voltage
input if using an external voltage reference source.
47, 48 VIN−D, VIN+D Input ADC D Analog Input Complement/True.
52, 53 VIN+C, VIN−C Input ADC C Analog Input True/Complement.
60, 61 CLK+, CLK− Input Clock Input True/Complement.
63, 67 AGND_SR Ground Ground Reference for SYSREF±.
64 AVDD1_SR Supply Analog Power Supply for SYSREF± (0.975 V Nominal).
65, 66 SYSREF+, SYSREF− Input Active Low JESD204B LVDS System Reference Input
True/Complement. DC-coupled input only.
EPAD
Exposed Pad. Analog ground. The exposed thermal pad on the
bottom of the package provides the ground reference for
AVDDX, SPIVDD, DVDD, DRVDD1, and DRVDD2. This exposed
pad must be connected to ground for proper operation.
Data Sheet AD9694
Rev. B | Page 15 of 96
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.80 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference,
AIN = −1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full
operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
AIN = –1dBFS
SNR = 67.10dB
SFDR = 90dBFS
ENOB = 10.8 BITS
14808-100
Figure 6. Single-Tone FFT with fIN = 10.3 MHz
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
AIN = –1dBFS
SNR = 67.0dB
SFDR = 85dBFS
ENOB = 10.8 BITS
14808-101
Figure 7. Single-Tone FFT with fIN = 155 MHz
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
AIN = –1dBFS
SNR = 66.8dB
SFDR = 82dBFS
ENOB = 10.7 BITS
14808-102
Figure 8. Single-Tone FFT with fIN = 305 MHz
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
AIN = –1dBFS
SNR = 66.6dB
SFDR = 83dBFS
ENOB = 10.7 BITS
14808-103
Figure 9. Single-Tone FFT with fIN = 453 MHz
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
AIN = –1dBFS
SNR = 66.5dB
SFDR = 75dBFS
ENOB = 10.6 BITS
14808-104
Figure 10. Single-Tone FFT with fIN = 765 MHz
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
AIN = –1dBFS
SNR = 66.0dB
SFDR = 79dBFS
ENOB = 10.6 BITS
14808-105
Figure 11. Single-Tone FFT with fIN = 985 MHz
AD9694 Data Sheet
Rev. B | Page 16 of 96
60
65
70
75
80
85
90
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
14808-106
SAMPLE RATE (MHz)
SNR/SFDR (dBFS)
SFDR
SNR
Figure 12. SNR/SFDR vs. Sample Rate (fS), fIN = 155 MHz
60
65
70
SNR/SFDR (dBFS)
75
ANALOG INPUT FREQUENCY (MHz)
80
85
95
90
10
65
85
105
125
145
165
185
205
225
245
265
365
465
565
14808-107
SFDR (dBFS), –40°C
SFDR (dBFS), +105°C
SFDR (dBFS), +50°C SNRFS, –40°C
SNRFS, +105°C
SNRFS, +50°C
Figure 13. SNR/SFDR vs. Analog Input Frequency (fIN)
66.0
66.1
66.2
66.3
ANALOG INPUT FREQUENCY (MHz)
SNR (dBFS)
66.4
66.5
66.6
66.7
66.8
66.9
67.0
67.1
67.2
67.3
67.4
67.5
10
65
85
105
125
145
165
185
205
225
245
265
365
465
14808-108
Figure 14. SNR vs. Analog Input Frequency (fIN), First and Second Nyquist
Zones; AIN at −3 dBFS
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
10
65
85
105
125
145
165
185
205
225
245
265
365
465
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
14808-109
Figure 15. SFDR vs. Analog Input Frequency (fIN), First and Second Nyquist
Zones; AIN at −3 dBFS
465
495
525
555
585
615
645
675
705
735
765
795
66.0
ANALOG INPUT FREQUENCY (MHz)
SNR (dBFS)
66.5
67.0
67.5
14808-110
Figure 16. SNR vs. Analog Input Frequency (fIN), Third Nyquist Zone
AIN at −3 dBFS
465
495
525
555
585
615
645
675
705
735
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
14808-111
Figure 17. SFDR vs. Analog Input Frequency (fIN), Third Nyquist Zone; AIN
at −3 dBFS
fi A.“ AND AN = 4.1an 7 SFDR = «5.44375 W A.“ AND AN = 4.1an 7 SFDR = 353an /\P~ \ \ W‘M‘A‘ \ V , \ PM ‘ ‘ ‘ V M ¥ V N V‘VWM \ \ \
Data Sheet AD9694
Rev. B | Page 17 of 96
–160
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
A
IN1
AND A
IN2
= –7dBFS
SFDR = 86.4dBFS
14808-112
Figure 18. Two-Tone FFT; fIN1 = 153.5 MHz, fIN2 = 156.5 MHz
–160
–140
–120
–100
–80
–60
–40
–20
0
050 100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
150 200 250
A
IN1
AND A
IN2
= –7dBFS
SFDR = 85.9dFS
14808-113
Figure 19. Two-Tone FFT; fIN1 = 303.5 MHz, fIN2 = 306.5 MHz
–140
–120
–100
–80
–60
–40
–20
0
–90 –84 –78 –72 –66 –60 –54 –48
ANALOG INPUT AMPLITUDE (dBFS)
SFDR/IMD3 (dBc AND dBFS)
–42 –36 –30 –24 –18 –12 0
IMD3 (dBc)
IMD3 (dBFS)
SFDR (dBFS)
SFDR (dBc)
14808-114
Figure 20. Two-Tone SFDR/IMD3 vs. Analog Input Amplitude (AIN) with
fIN1 = 303.5 MHz and fIN2 = 306.5 MHz
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
–100 –90 –80 –70 –60 –50
ANALOG INPUT FREQUENCY (MHz)
–40 –30 –20 –10 0
SFDR (dBFS)
SNRFS
SFDR (dBc)
SNR
SNR/SFDR (dB)
14808-115
Figure 21. SNR/SFDR vs. Analog Input Frequency, fIN = 155 MHz
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
–100 –90 –80 –70 –60 –50
ANALOG INPUT FREQUENCY (MHz)
–40 –30 –20 –10 0
SFDR (dBFS)
SNRFS
SFDR (dBc)
SNR
14808-116
SNR/SFDR (dB)
Figure 22. SNR/SFDR vs. Analog Input Frequency, fIN = 305 MHz
60
65
70
75
SNR/SFRDR (dBFS)
80
85
90
JUNCTION TEMPERATUREC)
14808-117
–54
–31
–10
11
31
51
71
91
111
122
129
SFDR
SNR
Figure 23. SNR/SFDR vs. Junction Temperature, fIN = 155 MHz
AD9694 Data Sheet
Rev. B | Page 18 of 96
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL (LSB)
0
1024
2048
3072
4096
5120
6144
7168
8192
OUTPUT CODE
9216
10240
11264
12288
13312
14336
15360
16384
14808-118
Figure 24. INL, fIN = 10.3 MHz
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
DNL (LSB)
0.6
0.8
1.0
0
1024
2048
3072
4096
5120
6144
7168
8192
OUTPUT CODE
9216
10240
11264
12288
13312
14336
15360
16384
14808-119
Figure 25. DNL, fIN = 10.3 MHz
NUMBER OF HITS
CODE
6000
5000
4000
3000
2000
1000
0
N – 10
N – 9
N – 8
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
0
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N + 10
14808-120
Figure 26. Input Referred Noise Histogram
1.40
1.45
1.50
1.55
1.60
1.65
POWER DISSIPATION (W)
1.70
1.75
1.80
1.85
250 300 350 400 450
SAMPLE RATE (MSPS)
500 550 600 650
14808-122
Figure 27. Power Dissipation vs. Sample Rate (fS)
–160
–140
–120
–100
–80
–60
–40
–20
0
–125 –75 –25 25 75 125
FREQUENCY (MHz)
AMPLITUDE (dBFS)
A
IN
= –1dBFS
SNRFS = 65.94dB
SFDR = 89.01dBFS
14808-123
Figure 28. DDC Mode (Four DDCs; Decimate by 2; L = 2, M = 4, and F = 4)
with fIN = 305 MHz
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
A
IN
= –1dBFS
SNRFS = 71.80dB
SFDR = 98.27dBFS
–62.5
62.5
–42.5
–22.5
0
17.5
37.5
57.5
14808-124
Figure 29. DDC Mode (Four DDCs; Decimate by 4; L = 1, M = 4, and F = 8)
with fIN = 305 MHz
Data Sheet AD9694
Rev. B | Page 19 of 96
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
AIN = –1dBFS
SNRFS = 71.80dB
SFDR = 98.27dBFS
–31.25 –21.25 –11.25 –1.25 8.75 18.75 28.75
14808-125
Figure 30. DDC Mode (Four DDCs; Decimate by 8; L = 1, M = 4, and F = 8)
with fIN = 305 MHz
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
AIN = –1dBFS
SNRFS = 74.50dB
SFDR = 100.68dBFS
–15.625 –10.625 –5.625 –0.625 4.375 9.375 14.375
14808-126
Figure 31. DDC Mode (Four DDCs, Decimate by 16, L = 1, M = 4, and F = 8)
with fIN = 305 MHz
65.5
65.6
65.7
65.8
65.9
66.0
66.1
66.2
66.3
66.4
66.5
66.6
66.7
66.8
66.9
67.0
0.118
0.132
0.148
0.166
0.185
0.207
0.234
0.262
0.293
0.328
0.370
0.416
DIFFERENTIAL VOLTAGE (V)
0.468
0.526
0.587
0.693
0.778
0.873
0.979
1.091
1.209
1.322
1.482
1.653
1.833
SNR (dBFS)
14808-129
Figure 32. SNR vs. Differential Voltage (Clock Amplitude), fIN = 155.3 MHz
–95
–94
–93
–92
–91
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
10
65
85
105
125
145
165
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
185
205
225
245
265
365
465
BUFFER CURRENT = 160µA
BUFFER CURRENT = 200µA
BUFFER CURRENT = 240µA
BUFFER CURRENT = 280µA
14808-130
Figure 33. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (First and Second Nyquist Zones)
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
–69
–68
–67
–66
–65
465
495
525
555
585
615
645
675
705
735
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
BUFFER CURRENT = 200µA
BUFFER CURRENT = 240µA
BUFFER CURRENT = 280µA
BUFFER CURRENT = 320µA
14808-131
Figure 34. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (Third Nyquist Zone)
–80
–78
–76
–74
–72
–70
–68
–66
–64
–62
–60
–58
–56
–54
–52
–50
–48
–46
–44
–42
–40
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
730
760
790
820
850
880
910
940
970
1030
1060
1090
1120
1150
1180
1210
1240
1270
1300
1330
1360
1390
1420
1450
1480
1510
1540
1570
1600
1630
1660
1690
1720
1750
1780
1810
BUFFER CURRENT = 320µA
BUFFER CURRENT = 360µA
BUFFER CURRENT = 400µA
BUFFER CURRENT = 440µA
14808-132
Figure 35. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (Fourth Nyquist Zone)
AD9694 Data Sheet
Rev. B | Page 20 of 96
ANALOG INPUT FREQUENCY (MHz)
64
65
66
67
68
69
10
65
85
105
125
SNR (dBFS)
145
165
185
205
225
245
265
365
465
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 1.44V
14808-133
Figure 36. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (First and Second Nyquist Zones)
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 1.44V
465.3
495.3
525.3
555.3
585.3
615.3
645.3
675.3
705.3
735.3
ANALOG INPUT FREQUENCY (MHz)
64.0
64.2
64.4
64.6
64.8
65.0
65.2
65.4
65.6
65.8
66.0
66.2
66.4
66.6
66.8
67.0
67.2
67.4
67.6
67.8
68.0
68.2
68.4
68.6
68.8
69.0
SNR (dBFS)
14808-134
Figure 37. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (Third Nyquist Zone)
62
63
64
65
66
67
68
730
760
790
820
850
880
910
940
970
1000
1030
1060
1090
1120
1150
1180
1210
1240
1270
1300
1330
1360
1390
1420
1450
1480
1510
1540
1570
1600
1630
1660
1690
1720
1750
1780
1810
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 1.44V
ANALOG INPUT FREQUENCY (MHz)
SNR (dBFS)
14808-135
Figure 38. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (Fourth Nyquist Zone)
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
10
65
85
105
125
145
165
185
205
225
245
265
365
465
565
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 1.44V
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
14808-136
Figure 39. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (First and Second Nyquist Zones)
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
465
495
525
555
585
615
645
675
705
735
765
795
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 1.44V
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
14808-137
Figure 40. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (Third Nyquist Zone)
–81
–79
–77
–75
–73
–71
–69
–67
–65
–63
–61
–59
–57
–55
730
790
850
910
970
1060
1120
1180
1240
1300
1360
1420
1480
1540
1600
1660
1720
1780
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBFS)
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 1.44V
14808-138
Figure 41. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (Fourth Nyquist Zone)
Data Sheet AD9694
Rev. B | Page 21 of 96
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
100 150 200 250 300 350 400 450 500 550 600
BUFFER CURRENT SETTING (µA)
AVDD3 POWER (W)
14808-139
Figure 42. AVDD3 Power vs. Buffer Current Setting
–20
–18
ANALOG INPUT FREQUENCY (MHz)
POWER (dB)
–16
–14
–12
–10
–8
–6
–4
–2
0
2
325
0
575
825
1075
1145
1195
1245
1295
1345
1495
1445
1495
1545
1595
1800
14808-200
Figure 43. Full Power Bandwidth
v «PM 4»+H u u é“. éhp—I
AD9694 Data Sheet
Rev. B | Page 22 of 96
EQUIVALENT CIRCUITS
A
IN
CONTROL
(SPI)
10pF
VIN+x
100Ω
VIN–x
AVDD3
AVDD3
V
CM
BUFFER
400Ω
100Ω
AVDD3
AVDD3
3.5pF
AVDD3
3.5pF
14808-024
Figure 44. Analog Inputs
AVDD1
25Ω
AVDD1
25Ω
16kΩ
16kΩ
V
CM
= 0.95V
CLK+
CLK–
14808-025
Figure 45. Clock Inputs
130kΩ
130kΩ
LEVEL
TRANSLATOR
SYSREF+ 10kΩ
AVDD1_SR
1.9pF
1.9pF
100Ω
SYSREF– 10kΩ
100Ω
AVDD1_SR
14808-026
Figure 46. SYSREF± Inputs
DRVDD1
DRGND
DRVDD1
DRGND
OUTPUT
DRIVER
EMPHASIS/SWING
CONTROL (SPI)
DATA+
DATA–
SERDOUTABx+/SERDOUTCDx+
x = 0, 1
SERDOUTABx–/SERDOUTCDx–
x = 0, 1
14808-027
Figure 47. Digital Outputs
130kΩ
130kΩ
LEVEL
TRANSLATOR
SYNCINB+AB/
SYNCINB+CD
SYNCINB–AB/
SYNCINB–CD
10kΩ
1.9pF
1.9pF
100Ω
2.5kΩ
10kΩ
100Ω
DRVDD1
DRGND
DRVDD1
DRGND
DRVDD1
DRGND
DRGND
DRGND
CMOS
PATH
SYNCINB PIN
CONTROL (SPI)
14808-028
Figure 48. SYNCINB±AB, SYNCINB±CD Inputs
56kΩ
DGND DGND
SPIVDD
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
SCLK
14808-029
Figure 49. SCLK Input
Data Sheet AD9694
Rev. B | Page 23 of 96
56kΩ
DGND
DGND
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
CSB
14808-030
Figure 50. CSB Input
56kΩ
SPIVDD
SDI
DGND
DGND
DGNDDGND
SDO
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
SPIVDD
SDIO
14808-031
Figure 51. SDIO Input
FD_A/FD_B/
FD_C/FD_D
FD
FD_x PIN CONTROL (SPI)
JESD204B LMFC
56kΩ
SPIVDD
DGNDDGND
DGND
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
14808-032
JESD204B SYNC
Figure 52. FD_A/FD_B/FD_C/FD_D Outputs
ESD
PROTECTED
ESD
PROTECTED
SPIVDD
DGND
DGND
PDWN/
STBY
PDWN
CONTROL (SPI)
14808-033
Figure 53. PDWN/STBY Input
VREF PIN
CONTROL (SPI)
VCM_CD/VREF
AGND
AVDD2 TEMPERATURE
DIODE VOLTAGE
EXTERNAL REFERENCE
VOLTAGE INPUT
14808-034
Figure 54. VCM_CD/VREF Input/Output
L3|=I§‘LI,_
AD9694 Data Sheet
Rev. B | Page 24 of 96
THEORY OF OPERATION
ADC ARCHITECTURE
The architecture of the AD9694 consists of an input buffered
pipelined ADC. The input buffer is designed to provide a 200 Ω
termination impedance to the analog input signal. The equivalent
circuit diagram of the analog input termination is shown in
Figure 44.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The buffer
is optimized for high linearity, low noise, and low power. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample while the remaining stages operate with the preceding
samples at the same time. Sampling occurs on the rising edge of
the clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9694 is a differential buffer with an
internal common-mode voltage of 1.34 V. The clock signal
alternately switches the input circuit between sample mode and
hold mode. Either a differential capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This configuration ultimately creates a low-pass
filter at the input, which limits unwanted broadband noise. See
Figure 55 and Figure 56 for details on input network
recommendations.
For best dynamic performance, the source impedances driving
VIN+x and VIN−x must be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9694, the available span is programmable through the SPI
port from 1.44 V p-p to 2.16 V p-p differential, with 1.80 V p-p
differential being the default.
Dither
The AD9694 has internal on-chip dither circuitry that improves
the ADC linearity and SFDR, particularly at smaller signal
levels. A known but random amount of white noise is injected
into the input of the AD9694. This dither improves the small
signal linearity within the ADC transfer function and is precisely
subtracted out digitally. The dither is turned on by default and
does not reduce the ADC input dynamic range. The data sheet
specifications and limits are obtained with the dither turned on.
The dither can be disabled using SPI writes to Register 0x0922.
Disabling the dither can slightly improve the SNR (by about 0.2 dB)
at the expense of the small signal SFDR.
Differential Input Configurations
There are several ways to drive the AD9694, either actively or
passively. However, optimum performance is achieved by
driving the analog input differentially.
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 55 and Figure 56) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD9694.
For low to midrange frequencies, a double balun or double
transformer network (see Figure 55) is recommended for
optimum performance of the AD9694. For higher frequencies
in the third or fourth Nyquist zones, remove some of the front-
end passive components to ensure wideband operation (see
Figure 56).
10Ω
0.1µF
VIN+x
VIN–x
0.1µF
0.1µF
BALUN
50Ω
AGND
AGND
AGND
10Ω
50Ω 10Ω
10Ω0Ω
2pF
2pF
2pF
10Ω 10Ω0Ω
14808-038
Figure 55. Differential Transformer Coupled Configuration for First and
Second Nyquist Frequencies
10Ω
0.1µF
VIN+x
VIN–x
0.1µF
0.1µF
50Ω
AGND
AGND
AGND
DNI
50Ω DNI
10Ω0Ω
DNI
DNI
DNI
10Ω 10Ω
0Ω
14808-039
BALUN
Figure 56. Differential Transformer Coupled Configuration for Third and
Fourth Nyquist Zones
Data Sheet AD9694
Rev. B | Page 25 of 96
Input Common Mode
The analog inputs of the AD9694 are internally biased to the
common mode as shown in Figure 57.
For dc-coupled applications, the recommended operation procedure
is to export the common-mode voltage to the VCM_CD/VREF
pin using the SPI writes listed in this section. The common-mode
voltage must be set by the exported value to ensure proper ADC
operation. Disconnect the internal common-mode buffer from
the analog input using Register 0x1908.
When performing SPI writes for dc coupling operation, use the
following register settings in order:
1. Set Register 0x1908, Bit 2 to 1 to disconnect the internal
common-mode buffer from the analog input.
2. Set Register 0x18A6 to 0x00 to turn off the voltage
reference.
3. Set Register 0x18E6 to 0x00 to turn off the temperature
diode export.
4. Set Register 0x18E0 to 0x04.
5. Set Register 0x18E1 to 0x1C.
6. Set Register 0x18E2 to 0x14.
7. Set Register 0x18E3, Bit 6 to 0x01 to turn on the VCM export.
8. Set Register 0x18E3, Bits[5:0] to the buffer current setting
(copy the buffer current setting from Register 0x1A4C and
Register 0x1A4D to improve the accuracy of the common-
mode export).
Analog Input Controls and SFDR Optimization
The AD9694 offers flexible controls for the analog inputs, such
as buffer current and input full-scale adjustment. All of the
available controls are shown in Figure 57.
A
IN
CONTROL
(SPI)
10pF
VIN+x
100Ω
VIN–x
AVDD3
AVDD3
V
CM
BUFFER
400Ω
100Ω
AVDD3
AVDD3
3.5pF
AVDD3
3.5pF
14808-037
Figure 57. Analog Input Controls
Using Register 0x1A4C and Register 0x1A4D, the buffer currents
on each channel can be scaled to optimize the SFDR over various
input frequencies and bandwidths of interest. As the input
buffer currents are set, the amount of current required by the
AVDD3 supply changes. This relationship is shown in Figure 58.
For a complete list of buffer current settings, see Table 39.
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
100 150 200 250 300 350 400 450 500 550 600
BUFFER CURRENT SETTING (µA)
AVDD3 POWER (W)
14808-139
Figure 58. AVDD3 Power vs. Buffer Current Setting
In certain high frequency applications, the SFDR can be
improved by reducing the full-scale setting.
Table 11 shows the recommended buffer current settings for the
different analog input frequency ranges.
Table 11. SFDR Optimization for Input Frequencies
Nyquist Zone
Input Buffer Current Control Setting,
Register 0x1A4C and Register 0x1A4D
First, Second, and
Third Nyquist
240 µA (Register 0x1A4C, Bits[5:0] =
Register 0x1A4D, Bits[5:0] = 01100)
Fourth Nyquist 400 µA (Register 0x1A4C, Bits[5:0] =
Register 0x1A4D, Bits[5:0] = 10100)
Absolute Maximum Input Swing
The absolute maximum input swing allowed at the inputs of the
AD9694 is 4.3 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9694. This internal 0.5 V reference is used to set the full-
scale input range of the ADC. The full-scale input range can be
adjusted via Register 0x1910. For more information on adjusting
the input swing, see Table 39. Figure 59 shows the block diagram
of the internal 0.5 V reference controls.
ADC
CORE
FULL-SCALE
VOLTAGE
ADJUST
VREF PIN
CONTROL SPI
REGISTER
(0x18A6)
VREF
VIN–A/
VIN–B
VIN+A/
VIN+B
INTERNAL
VREF
GENERATOR
INPUT FULL-SCALE
RANGE ADJUST
SPI REGISTER
(0x1910)
14808-040
Figure 59. Internal Reference Configuration and Controls
AD9694 Data Sheet
Rev. B | Page 26 of 96
FULL-SCALE
VOLTAGE
ADJUST
VREF
0.1µF
V
OUT 4
SET
5
NC
6
V
IN
3
GND
2
NC
1
ADR130
0.1µF
INPUT
VREF PIN AND
FULL-SCALE
VOLTAGE
CONTROL
INTERNAL
VREF
GENERATOR
14808-042
Figure 60. External Reference Using the ADR130
Register 0x18A6 enables the user to either use this internal 0.5 V
reference, or to provide an external 0.5 V reference. When using
an external voltage reference, provide a 0.5 V reference. The
full-scale adjustment is made using the SPI, irrespective of the
reference voltage. For more information on adjusting the full-
scale level of the AD9694, refer to the Memory Map section.
The SPI writes required to use the external voltage reference, in
order, are as follows:
1. Set Register 0x18E3 to 0x00 to turn off VCM export.
2. Set Register 0x18E6 to 0x00 to turn off temperature diode
export.
3. Set Register 0x18A6 to 0x01 to turn on the external voltage
reference.
The use of an external reference can be necessary, in some
applications, to enhance the gain accuracy of the ADC or to
improve thermal drift characteristics.
The external reference must be a stable 0.5 V reference. The
ADR130 is a sufficient option for providing the 0.5 V reference.
Figure 60 shows how the ADR130 provides the external 0.5 V
reference to the AD9694. The dashed lines show unused blocks
within the AD9694 while using the ADR130 to provide the
external reference.
DC OFFSET CALIBRATION
The AD9694 contains a digital filter to remove the dc offset
from the output of the ADC. For ac-coupled applications, this
filter can be enabled by setting Register 0x0701, Bit 7 to 1 and
setting Register 0x073B, Bit 7 to 0. The filter computes the
average dc signal, and it is digitally subtracted from the ADC
output. As a result, the dc offset is improved to better than
70 dBFS at the output. Because the filter does not distinguish
between the source of dc signals, this feature can be used when
the signal content at dc is not of interest. The filter corrects dc
up to ±512 codes and saturates beyond that.
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9694 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally
and require no additional biasing.
Figure 61 shows a preferred method for clocking the AD9694. The
low jitter clock source is converted from a single-ended signal to
a differential signal using an RF transformer.
ADC
CLK+
CLK–
0.1µF
0.1µF
100Ω
50Ω
CLOCK
INPUT 1:1Z
14808-043
Figure 61. Transformer Coupled Differential Clock
Another option is to ac couple a differential CML or LVDS
signal to the sample clock input pins, as shown in Figure 62 and
Figure 63.
ADC
CLK+
CLK–
0.1µF
0.1µF
Z
0
= 50Ω
Z
0
= 50Ω
33Ω 33Ω
71Ω 10pF
3.3V
14808-044
Figure 62. Differential CML Sample Clock
ADC
CLK+
CLK–
0.1µF
0.1µF
0.1µF
0.1µF
50Ω
1
50Ω
1
100Ω
CLOCK INPUT
LVDS
DRIVER
CLK+
CLK–
1
50Ω RESISTORS ARE OPTIONAL.
CLOCK INPUT
14808-045
Figure 63. Differential LVDS Sample Clock
Data Sheet AD9694
Rev. B | Page 27 of 96
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals. The AD9694 contains an internal clock
divider and a duty cycle stabilizer (DCS). In applications where the
clock duty cycle cannot be guaranteed to be 50%, a higher multiple
frequency clock along with the usage of the clock divider is recom-
mended. When it is not possible to provide a higher frequency
clock, it is recommended to turn on the DCS. The output of the
divider offers a 50% duty cycle, high slew rate (fast edge) clock
signal to the internal ADC. The following SPI writes are
required to turn on DCS (see the Memory Map section for
more details on using this feature):
1. Write 0x81 to 0x011F.
2. Write 0x09 to 0x011C.
3. Write 0x09 to 0x011E.
4. Write 0x0B to 0x011C.
5. Write 0x0B to 0x011E.
Input Clock Divider
The AD9694 contains an input clock divider with the ability to
divide the input clock by 1, 2, 4, or 8. The divider ratios can be
selected using Register 0x0108 (see Figure 64).
In applications where the clock input is a multiple of the sample
clock, care must be taken to program the appropriate divider ratio
into the clock divider before applying the clock signal, which
ensures that the current transients during device startup are
controlled.
CLK+
CLK– ÷2
÷4
REG 0x0108
÷8
14808-046
Figure 64. Clock Divider Circuit
The AD9694 clock divider can be synchronized using the external
SYSREF± input. A valid SYSREF± causes the clock divider to
reset to a programmable state. This synchronization feature
allows multiple devices to have their clock dividers aligned to
guarantee simultaneous input sampling.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fA) due only to aperture jitter (tJ) can be calculated by
SNR = −20 × log (2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications. IF
undersampling applications are particularly sensitive to jitter
(see Figure 65).
130
120
110
100
90
80
70
60
50
40
3010 100 1000 10000
IDEAL SNR (dB)
ANALOG INPUT FREQUENCY (MHz)
12.5
f
S
25
f
S
50
f
S
100
f
S
200
f
S
400
f
S
800
f
S
14808-047
Figure 65. Ideal SNR vs. Analog Input Frequency over Jitter
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9694. Separate the
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
If the clock is generated from another type of source (by gating,
dividing, or other methods), retime the clock by the original clock
at the last step. Refer to the AN-501 Application Note and the
AN-756 Application Note for more in depth information about
jitter performance as it relates to ADCs.
Figure 65 shows the estimated SNR of the AD9694 across input
frequency for different clock induced jitter values. The SNR can
be estimated by using the following equation:
+=
10
10 101010log(dBFS)
JITTER
ADC
SNR
SNR
SNR
Input Clock Detect
The AD9694 contains input clock detection circuitry to detect
the signal on the input clock pins. If the clock amplitude or the
sample rate is lower than the specified minimum value, the
AD9694 enters power-down mode. When the input clock detect
bit in Register 0x011B is set to 0, the input clock is not detected.
See Register 0x011A and Register 0x011B for more details on
the input clock detect feature.
Power-Down/Standby Mode
The AD9694 has a PDWN/STBY pin that configures the
device in power-down or standby mode. The default operation
is power-down. The PDWN/STBY pin is a logic high pin. When
in power-down mode, the JESD204B link is disrupted. The
power-down option can also be set via Register 0x003F and
Register 0x0040.
In standby mode, the JESD204B link is not disrupted and
transmits zeros for all converter samples. This state can be
changed using Register 0x0571, Bit 7 to select /K/ characters.
AD9694 Data Sheet
Rev. B | Page 28 of 96
Temperature Diode
The AD9694 contains a diode-based temperature sensor for
measuring the temperature of the die. This diode can output a
voltage and serve as a coarse temperature sensor to monitor the
internal die temperature.
The temperature diode voltage can be output to the VCM_CD/
VREF pin using the SPI. Use Register 0x18E6 to enable or disable
the diode. Register 0x18E6 is a local register. Both cores must be
selected in the pair index register (Register 0x0009 = 0x03) to
enable the temperature diode readout. It is important to note
that other voltages may be exported to the same pin at the same
time, which can result in undefined behavior. Thus, to ensure a
proper readout, switch off all other voltage exporting circuits as
detailed as follows.
The SPI writes required to export the temperature diode are as
follows (see Table 39 for more information):
1. Set Register 0x0009 to 0x03 to select both cores.
2. Set Register 0x18E3 to 0x00 to turn off VCM export.
3. Set Register 0x18A6 to 0x00 to turn off voltage reference
export.
4. Set Register 0x18E6 to 0x01 to turn on voltage export of
the central 1× temperature diode. The typical voltage
response of the temperature diode is shown in Figure 66.
Although this voltage represents the die temperature, it is
recommended to take measurements from a pair of diodes
for improved accuracy. The next step explains how to
enable the 20× diode.
5. Set Register 0x18E6 to 0x02 to turn on the second central
temperature diode of the pair, which is 20× the size of the
first. For the method using two diodes simultaneously to
achieve a more accurate result, see the AN-1432 Application
Note, Practical Thermal Modeling and Measurements in
High Power ICs.
0.80
0.75
0.70
0.65
0.60
0.55
0.50
–40 –20 020
JUNCTION TEMPERATURE (°C)
TEMPERATURE DIODE VOLTAGE (V)
40 60 80 100
14808-048
Figure 66. Temperature Diode Voltage vs. Junction Temperature
Data Sheet AD9694
Rev. B | Page 29 of 96
ADC OVERRANGE AND FAST DETECT
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit in the JESD204B outputs provides
information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input
signals can have significant slew rates, the latency of this
function is of major concern. Highly pipelined converters can
have significant latency. The AD9694 contains fast detect
circuitry for individual channels to monitor the threshold and
to assert the FD_A, FD_B, FD_C, and FD_D pins.
ADC OVERRANGE
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be embedded within the JESD204B link as a control bit (when
CSB > 0). The latency of this overrange indicator matches the
sample latency.
FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C,
AND FD_D)
The fast detect (FD) bits in Register 0x0040 are immediately set
whenever the absolute value of the input signal exceeds the
programmable upper threshold level. The FD bits are cleared
only when the absolute value of the input signal drops below the
lower threshold level for greater than the programmable dwell
time. This feature provides hysteresis and prevents the FD bits
from excessively toggling.
The operation of the upper threshold and lower threshold
registers, along with the dwell time registers, is shown in
Figure 67.
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located at Register 0x0247 and Register 0x0248. The selected
threshold register is compared with the signal magnitude at the
output of the ADC. The fast upper threshold detection has a
latency of 30 clock cycles (maximum). The approximate upper
threshold magnitude is defined by
Upper Threshold Magnitude (dBFS) = 20log (Threshold
Magnitude/213)
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x0249 and Register 0x024A. The
fast detect lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency, but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
Lower Threshold Magnitude (dBFS) = 20log (Threshold
Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x0247 and Register 0x0248. To set a lower threshold of
−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x024B and Register 0x024C. See
the Memory Map section (Register 0x0040, and Register 0x0245 to
Register 0x024C in Table 39) for more details.
UPPER THRESHOLD
LOWER THRESHOLD
FD_A OR FD_B
MIDSCALE
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
DWELL TIME
14808-050
Figure 67. Threshold Settings for the FD_A and FD_B Signals
AD9694 Data Sheet
Rev. B | Page 30 of 96
SIGNAL MONITOR
The signal monitor block provides additional information about
the signal being digitized by the ADC. The signal monitor
computes the peak magnitude of the digitized signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
The results of the signal monitor block can be obtained either
by reading back the internal values from the SPI port or by
embedding the signal monitoring information into the
JESD204B interface as special control bits. A global, 24-bit
programmable period controls the duration of the measurement.
Figure 68 shows the simplified block diagram of the signal
monitor block.
FROM
MEMORY
MAP
DOWN
COUNTER IS
COUNT = 1?
MAGNITUDE
STORAGE
REGISTER
FROM
INPUT
SIGNAL
MONITOR
HOLDING
REGISTER
LOAD
CLEAR
COMPARE
A > B
LOAD
LOAD
TO SPORT OVER
JESD204B AND
MEMORY MAP
SIGNAL MONITOR
PERIOD REGISTER
(SMPR)
0x0271, 0x0272, 0x0273
14808-051
Figure 68. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 of Register 0x0270 in the signal monitor
control register. The 24-bit SMPR must be programmed before
activating this mode.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
decimated clock rate. The magnitude of the input signal is
compared with the value in the internal magnitude storage register
(not accessible to the user), and the greater of the two is updated
as the current peak level. The initial value of the magnitude
storage register is set to the current ADC input signal magnitude.
This comparison continues until the monitor period timer reaches
a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained in the Fast
Threshold Detection (FD_A, FD_B, FD_C, and FD_D) section,
continues.
SPORT OVER JESD204B
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bit 0 of
Register 0x0279 and Bit 1 of Register 0x027A. Figure 69 shows
two different example configurations for the signal monitor control
bit locations inside the JESD204B samples. A maximum of three
control bits can be inserted into the JESD204B samples; however,
only one control bit is required for the signal monitor. Control
bits are inserted from MSB to LSB. If only one control bit is to be
inserted (CS = 1), only the most significant control bit is used (see
thed Example Configuration 1 and the Example Configuration 2 in
Figure 69). To select the SPORT over JESD204B (signal monitor)
option, program Register 0x0559, Register 0x055A, and
Register 0x058F. See Table 39 for more information on setting
these bits.
Figure 70 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 71 shows the SPORT over JESD204B signal monitor data
with a monitor period timer set to 80 samples.
Data Sheet AD9694
Rev. B | Page 31 of 96
15
14-BIT CONVERTER RESOLUTION (N = 14)
TAIL
X
1
CONTROL
BIT
(CS = 1)
1-BIT
CONTROL
BIT
(CS = 1)
14 13 12 11 10 9876543210
15 14 13 12 11 10 9876543210
1 TAIL
BIT
SERIALIZED SIGNAL MONITOR
FRAME DATA
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
SERIALIZED SIGNAL MONITOR
FRAME DATA
16-BIT JESD204B SAMPLE SIZE (N' = 16)
S[13]
XS[12]
XS[11]
XS[10]
XS[9]
XS[8]
XS[7]
XS[6]
XS[5]
XS[4]
XS[3]
XS[2]
XS[1]
XS[0]
X
CTRL
[BIT 2]
X
CTRL
[BIT 2]
X
S[14]
XS[13]
XS[12]
XS[11]
XS[10]
XS[9]
XS[8]
XS[7]
XS[6]
XS[5]
XS[4]
XS[3]
XS[2]
XS[1]
XS[0]
X
15-BIT CONVERTER RESOLUTION (N = 15)
16-BIT JESD204B SAMPLE SIZE (N' = 16)
14808-052
Figure 69. Signal Monitor Control Bit Locations
25-BIT
FRAME
5-BIT IDLE
SUBFRAME
(OPTIONAL)
5-BIT IDENTIFIER
SUBFRAME
5-BIT DATA
MSB
SUBFRAME
5-BIT DATA
SUBFRAME
5-BIT DATA
SUBFRAME
5-BIT DATA
LSB
SUBFRAME
5-BIT SUBFRAMES
P[ ] = PEAK MAGNITUDE VALUE
IDLE
1IDLE
1IDLE
1IDLE
1IDLE
1
START
0P[0] 0 0 0
START
0P[4] P[3] P[2] P[1]
START
0P[8] P[7] P[6] P[5]
START
0P[12] P[11] P[10] P[9]
START
0ID[3]
0ID[2]
0ID[1]
0ID[0]
1
14808-053
Figure 70. SPORT over JESD204B Signal Monitor Frame Data
M53 um um 53 uni um: um um um m: uni um: um um um “new a asan FRAME m . n Bu-SAMPLE PERIOD an M53 DIVA lSB um um uni um: um um um um uni um: um um um “new a asan FRAME m . 2) Bu-SAMPLE PERIOD ”A” um um W“ uni um: um um um ms uni um: um um um
AD9694 Data Sheet
Rev. B | Page 32 of 96
PAYLOAD 3
25-BIT FRAME (N)
PAYLOAD 3
25-BIT FRAME (N + 1)
PAYLOAD 3
25-BIT FRAME (N + 2)
IDLE IDLE IDLE IDLE IDLE IDLEIDLE IDLE IDLE IDLE IDLE
DATA
MSB DATA DATA DATA
LSB
IDLE IDLE IDLE IDLE IDLE IDLEIDLE IDLE IDLE IDLE IDLE
DATA
MSB DATA DATA DATA
LSB
IDLE IDLE IDLE IDLE IDLE IDLEIDLE IDLE IDLE IDLE IDLE
DATA
MSB DATA DATA DATA
LSB
SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00)
80-SAMPLE PERIOD
80-SAMPLE PERIOD
80-SAMPLE PERIOD
14808-054
IDENT-
IFIER
IDENT-
IFIER
IDENT-
IFIER
Figure 71. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples
Data Sheet AD9694
Rev. B | Page 33 of 96
DIGITAL DOWNCONVERTER (DDC)
The AD9694 includes four digital downconverters (DDCs) that
provide filtering and reduce the output data rate. This digital
processing section includes an NCO, a half-band decimating
filter, a finite impulse response (FIR filter, a gain stage, and a
complex to real conversion stage. Each of these processing blocks
has control lines that allow it to be independently enabled and
disabled to provide the desired processing function. Each pair
of ADC channels has two DDCs (DDC0 and DDC1) for a total
of four DDCs. The digital downconverter can be configured to
output either real data or complex output data.
The DDCs output a 16-bit stream. To enable this operation, the
converter number of bits, N, is set to a default value of 16, even
though the analog core only outputs 14 bits. In full bandwidth
operation, the ADC outputs are the 14-bit word followed by two
zeros, unless the tail bits are enabled.
DDC I/Q INPUT SELECTION
The AD9694 has four ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real and complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (that is, DDC Input Port I = ADC Channel A
and DDC Input Port Q = ADC Channel A). For complex
signals, each DDC input port must select different ADC
channels (that is, DDC Input Port I = ADC Channel A and
DDC Input Port Q = ADC Channel B or DDC Input Port I =
ADC Channel C and DDC Input Port Q = ADC Channel D).
The inputs to each DDC are controlled by the DDC input selec-
tion registers (Register 0x0311 and Register 0x0331) in conjunction
with the pair index register (Register 0x0009). See Table 39 for
information on how to configure the DDCs.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real and complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC x complex to real enable bit, Bit 3, in the DDC control
registers (Register 0x0310 and Register 0x0330) in conjunction
with the pair index register (Register 0x0009).
The Chip Q ignore bit in the chip mode register (Register 0x0200,
Bit 5) controls the chip output muxing of all the DDC channels.
When all DDC channels use real outputs, set this bit high to
ignore all DDC Q output ports. When any of the DDC channels
are set to use complex I/Q outputs, the user must clear this bit
to use both DDC Output Port I and DDC Output Port Q. For
more information, see Figure 80.
DDC GENERAL DESCRIPTION
The four DDC blocks are used to extract a portion of the full
digital spectrum captured by the ADC(s). The DDC blocks are
intended for IF sampling or oversampled baseband radios
requiring wide bandwidth input signals.
Each DDC block contains the following signal processing stages:
Frequency translation stage (optional)
Filtering stage
Gain stage (optional)
Complex to real conversion stage (optional)
Frequency Translation Stage (Optional)
This stage consists of a 48-bit complex NCO and quadrature
mixers that can be used for frequency translation of both real
and complex input signals. This stage shifts a portion of the
available digital spectrum down to baseband.
Filtering Stage
After shifting down to baseband, this stage decimates the frequency
spectrum using a chain of up to four half-band low-pass filters
for rate conversion. The decimation process lowers the output
data rate, which in turn reduces the output interface rate.
Gain Stage (Optional)
To compensate for losses associated with mixing a real input
signal down to baseband, this stage adds an additional 0 dB or
6 dB of gain.
Complex to Real Conversion Stage (Optional)
When real outputs are necessary, this stage converts the complex
outputs back to real by performing an fS/4 mixing operation
plus a filter to remove the complex component of the signal.
Figure 72 shows the detailed block diagram of the DDCs
implemented in the AD9694.
AD9694 Data Sheet
Rev. B | Page 34 of 96
L
JESD204B
LANES
AT UP TO
15Gbps
JESD204B TRANSMIT INTERFACE
L
JESD204B
LANES
AT UP TO
15Gbps
JESD204B TRANSMIT INTERFACE
NCO
+
MIXER
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
HB4 FIR
DCM = BYPASS OR 2
HB3 FIR
DCM = BYPASS OR 2
HB2 FIR
DCM = BYPASS OR 2
HB1 FIR
DCM = 2
GAIN = 0dB
OR 6dB
DDC 1
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 2
Q CONVERTER 3
I
Q
NCO
+
MIXER
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
HB4 FIR
DCM = BYPASS OR 2
HB3 FIR
DCM = BYPASS OR 2
HB2 FIR
DCM = BYPASS OR 2
HB1 FIR
DCM = 2
GAIN = 0dB
OR 6dB
DDC 0
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 0
Q CONVERTER 1
I
Q
NCO
+
MIXER
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
HB4 FIR
DCM = BYPASS OR 2
HB3 FIR
DCM = BYPASS OR 2
HB2 FIR
DCM = BYPASS OR 2
HB1 FIR
DCM = 2
GAIN = 0dB
OR 6dB
DDC 1
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 2
Q CONVERTER 3
I
Q
NCO
+
MIXER
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
HB4 FIR
DCM = BYPASS OR 2
HB3 FIR
DCM = BYPASS OR 2
HB2 FIR
DCM = BYPASS OR 2
HB1 FIR
DCM = 2
GAIN = 0dB
OR 6dB
DDC 0
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 0
Q CONVERTER 1
I
Q
I/Q CROSSBAR MUXI/Q CROSSBAR MUX
ADC
SAMPLING
AT
f
S
REAL/I
ADC
SAMPLING
AT
f
S
REAL/Q
ADC
SAMPLING
AT
f
S
REAL/I
ADC
SAMPLING
AT
f
S
REAL/Q
SYNCHRONIZATION
CONTROL CIRCUITS
SYSREF
14808-055
Figure 72. DDC Detailed Block Diagram
Figure 73 shows an example usage of one of the four DDC blocks
with a real input signal and four half-band filters (HB4 + HB3 +
HB2 + HB1). It shows both complex (decimate by 16) and real
(decimate by 8) output options.
When DDCs have different decimation ratios, the chip decimation
ratio register (Register 0x0201) must be set to the lowest decima-
tion ratio of all the DDC blocks on a per pair basis in conjunction
with the pair index register (Register 0x0009). In this scenario,
samples of higher decimation ratio DDCs are repeated to match
the chip decimation ratio sample rate. Whenever the NCO
frequency is set or changed, the DDC soft reset must be issued.
If the DDC soft reset is not issued, the output may potentially
show amplitude variations.
Table 12 through Table 16 show the DDC samples when the chip
decimation ratio is set to 1, 2, 4, 8, or 16, respectively. When
DDCs have different decimation ratios, the chip decimation
ratio must be set to the lowest decimation ratio of all the DDC
channels. In this scenario, samples of higher decimation ratio
DDCs are repeated to match the chip decimation ratio sample
rate.
WM WWW E W 1 ‘ ‘ , ‘0‘ 7 ‘X‘D’ ’x ’1 X
Data Sheet AD9694
Rev. B | Page 35 of 96
cos(ωt)
90°
I
Q
REAL
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
DIGITAL FILTER
RESPONSE
DC
DC
ADC
SAMPLING
AT
f
S
REAL REAL
HALF-
BAND
FILTER
HB4 FIR
2
HALF-
BAND
FILTER
HB3 FIR
2
HALF-
BAND
FILTER
HB2 FIR
2
HALF-
BAND
FILTER
HB1 FIR
I I
HALF-
BAND
FILTER
HB4 FIR
2
HALF-
BAND
FILTER
HB3 FIR
2
HALF-
BAND
FILTER
HB2 FIR
2
HALF-
BAND
FILTER
HB1 FIR
Q Q
ADC
REAL INPUT—SAMPLED AT
f
S
FILTERING STAGE
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
FREQUENCY TRANSLATION STAGE (OPTIONAL)
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
f
S
/2
f
S
/3
f
S
/4
f
S
/8
f
S
/16
f
S
/8
f
S
/4
f
S
/3
f
S
/2
f
S
/16
f
S
/32
f
S
/32
f
S
/2
f
S
/3
f
S
/4
f
S
/8
f
S
/16
f
S
/8
f
S
/4
f
S
/3
f
S
/2
f
S
/16
f
S
/32
f
S
/32
–sin(ωt)
48-BIT
NCO
DC
DIGITAL FILTER
RESPONSE
DC
DC
I
Q
I
Q
2
2
I
Q
REAL/I
COMPLEX
TO
REAL
I
Q
GAIN STAGE (OPTIONAL)
0dB OR 6dB GAIN
GAIN STAGE (OPTIONAL)
0dB OR 6dB GAIN
COMPLEX (I/Q) OUTPUTS
DECIMATE BY 16
REAL (I) OUTPUTS
DECIMATE BY 8
COMPLEX TO REAL
CONVERSION STAGE (OPTIONAL)
f
S
/4 MIXING + COMPLEX FILTER TO REMOVE Q
f
S
/8
f
S
/16
f
S
/8
f
S
/16
f
S
/32
f
S
/32
f
S
/8
f
S
/16
f
S
/8
f
S
/16
f
S
/32
f
S
/32
f
S
/16
f
S
/16
f
S
/32
f
S
/32
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
DOWNSAMPLE BY 2
+6dB
+6dB
+6dB
+6dB
DIGITAL MIXER + NCO
FOR
f
S
/3 TUNING, THE FREQUENCY TUNING WORD = ROUND
((
f
S
/3)/
f
S
× 2
48
) = +9.3825
13
(0x5555_5555_5555)
14808-056
Figure 73. DDC Theory of Operation Example (Real Input, Decimate by 16)
AD9694 Data Sheet
Rev. B | Page 36 of 96
Table 12. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 1
Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB1 FIR
(DCM1 = 1)
HB2 FIR +
HB1 FIR
(DCM1 = 2)
HB3 FIR + HB2
FIR + HB1 FIR
(DCM1 = 4)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 8)
HB1 FIR
(DCM1 = 2)
HB2 FIR +
HB1 FIR
(DCM1 = 4)
HB3 FIR + HB2
FIR + HB1 FIR
(DCM1 = 8)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 16)
N N N N N N N N
N + 1 N N N N N N N
N + 2 N + 1 N N N + 1 N N N
N + 3 N + 1 N N N + 1 N N N
N + 4 N + 2 N + 1 N N + 2 N + 1 N N
N + 5 N + 2 N + 1 N N + 2 N + 1 N N
N + 6 N + 3 N + 1 N N + 3 N + 1 N N
N + 7 N + 3 N + 1 N N + 3 N + 1 N N
N + 8 N + 4 N + 2 N + 1 N + 4 N + 2 N + 1 N
N + 9 N + 4 N + 2 N + 1 N + 4 N + 2 N + 1 N
N + 10 N + 5 N + 2 N + 1 N + 5 N + 2 N + 1 N
N + 11 N + 5 N + 2 N + 1 N + 5 N + 2 N + 1 N
N + 12 N + 6 N + 3 N + 1 N + 6 N + 3 N + 1 N
N + 13 N + 6 N + 3 N + 1 N + 6 N + 3 N + 1 N
N + 14 N + 7 N + 3 N + 1 N + 7 N + 3 N + 1 N
N + 15 N + 7 N + 3 N + 1 N + 7 N + 3 N + 1 N
N + 16 N + 8 N + 4 N + 2 N + 8 N + 4 N + 2 N + 1
N + 17 N + 8 N + 4 N + 2 N + 8 N + 4 N + 2 N + 1
N + 18 N + 9 N + 4 N + 2 N + 9 N + 4 N + 2 N + 1
N + 19 N + 9 N + 4 N + 2 N + 9 N + 4 N + 2 N + 1
N + 20 N + 10 N + 5 N + 2 N + 10 N + 5 N + 2 N + 1
N + 21 N + 10 N + 5 N + 2 N + 10 N + 5 N + 2 N + 1
N + 22 N + 11 N + 5 N + 2 N + 11 N + 5 N + 2 N + 1
N + 23 N + 11 N + 5 N + 2 N + 11 N + 5 N + 2 N + 1
N + 24 N + 12 N + 6 N + 3 N + 12 N + 6 N + 3 N + 1
N + 25 N + 12 N + 6 N + 3 N + 12 N + 6 N + 3 N + 1
N + 26 N + 13 N + 6 N + 3 N + 13 N + 6 N + 3 N + 1
N + 27 N + 13 N + 6 N + 3 N + 13 N + 6 N + 3 N + 1
N + 28 N + 14 N + 7 N + 3 N + 14 N + 7 N + 3 N + 1
N + 29 N + 14 N + 7 N + 3 N + 14 N + 7 N + 3 N + 1
N + 30 N + 15 N + 7 N + 3 N + 15 N + 7 N + 3 N + 1
N + 31 N + 15 N + 7 N + 3 N + 15 N + 7 N + 3 N + 1
1 DCM means decimation.
Table 13. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 2
Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB2 FIR +
HB1 FIR
(DCM1 = 2)
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 4)
HB4 FIR +
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 8)
HB1 FIR
(DCM1 = 2)
HB2 FIR +
HB1 FIR
(DCM1 = 4)
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 8)
HB4 FIR +
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 16)
N N N N N N N
N + 1 N N N + 1 N N N
N + 2 N + 1 N N + 2 N + 1 N N
N + 3 N + 1 N N + 3 N + 1 N N
N + 4 N + 2 N + 1 N + 4 N + 2 N + 1 N
N + 5 N + 2 N + 1 N + 5 N + 2 N + 1 N
N + 6 N + 3 N + 1 N + 6 N + 3 N + 1 N
N + 7 N + 3 N + 1 N + 7 N + 3 N + 1 N
N + 8 N + 4 N + 2 N + 8 N + 4 N + 2 N + 1
N + 9 N + 4 N + 2 N + 9 N + 4 N + 2 N + 1
Data Sheet AD9694
Rev. B | Page 37 of 96
Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB2 FIR +
HB1 FIR
(DCM1 = 2)
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 4)
HB4 FIR +
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 8)
HB1 FIR
(DCM1 = 2)
HB2 FIR +
HB1 FIR
(DCM1 = 4)
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 8)
HB4 FIR +
HB3 FIR +
HB2 FIR +
HB1 FIR
(DCM1 = 16)
N + 10 N + 5 N + 2 N + 10 N + 5 N + 2 N + 1
N + 11 N + 5 N + 2 N + 11 N + 5 N + 2 N + 1
N + 12 N + 6 N + 3 N + 12 N + 6 N + 3 N + 1
N + 13 N + 6 N + 3 N + 13 N + 6 N + 3 N + 1
N + 14 N + 7 N + 3 N + 14 N + 7 N + 3 N + 1
N + 15 N + 7 N + 3 N + 15 N + 7 N + 3 N + 1
1 DCM means decimation.
Table 14. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 4
Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB3 FIR + HB2 FIR +
HB1 FIR (DCM1 = 4)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 8)
HB2 FIR + HB1 FIR
(DCM1 = 4)
HB3 FIR + HB2 FIR +
HB1 FIR (DCM1 = 8)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 16)
N N N N N
N + 1 N N + 1 N N
N + 2 N + 1 N + 2 N + 1 N
N + 3 N + 1 N + 3 N + 1 N
N + 4 N + 2 N + 4 N + 2 N + 1
N + 5
N + 2
N + 5
N + 2
N + 1
N + 6 N + 3 N + 6 N + 3 N + 1
N + 7 N + 3 N + 7 N + 3 N + 1
1 DCM means decimation.
Table 15. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 8
Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8)
HB3 FIR + HB2 FIR + HB1 FIR
(DCM1 = 8)
HB4 FIR + HB3 FIR + HB2 FIR +
HB1 FIR (DCM1 = 16)
N
N
N
N + 1 N + 1 N
N + 2 N + 2 N + 1
N + 3 N + 3 N + 1
N + 4 N + 4 N + 2
N + 5
N + 5
N + 2
N + 6 N + 6 N + 3
N + 7 N + 7 N + 3
1 DCM means decimation.
Table 16. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 16
Real (I) Output (Complex to Real Enabled)
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
Not applicable N
Not applicable N + 1
Not applicable
N + 2
Not applicable N + 3
1 DCM means decimation.
AD9694 Data Sheet
Rev. B | Page 38 of 96
For example, if the chip decimation ratio is set to decimate by 4,
DDC 0 is set to use the HB2 + HB1 filters (complex outputs,
decimate by 4) and DDC 1 is set to use the HB4 + HB3 + HB2 +
HB1 filters (real outputs, decimate by 8). DDC 1 repeats its
output data two times for every one DDC 0 output. The resulting
output samples are shown in Table 17.
Table 17. DDC Output Samples in Each JESD204B Link When Chip DCM1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)
DDC 0 DDC 1
DDC Input Samples
Output Port I Output Port Q Output Port I Output Port Q
N I0 (N) Q0 (N) I1 (N) Not applicable
N + 1
N + 2
N + 3
N + 4 I0 (N + 1) Q0 (N + 1)
N + 5
N + 6
N + 7
N + 8 I0 (N + 2) Q0 (N + 2) I1 (N + 1) Not applicable
N + 9
N + 10
N + 11
N + 12 I0 (N + 3) Q0 (N + 3)
N + 13
N + 14
N + 15
1 DCM means decimation.
Data Sheet AD9694
Rev. B | Page 39 of 96
FREQUENCY TRANSLATION
OVERVIEW
Frequency translation is accomplished by using a 48-bit
complex NCO with a digital quadrature mixer. This stage
translates either a real or complex input signal from an IF to a
baseband complex digital output (carrier frequency = 0 Hz).
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x0310 and Register 0x0330)
in conjunction with the pair index register (Register 0x0009).
These IF modes are
Variable IF mode
0 Hz IF or zero IF (ZIF) mode
fS/4 Hz IF mode
Test mode
Variable IF Mode
The NCO and mixers are enabled. NCO output frequency can
be used to digitally tune the IF frequency.
0 Hz IF (ZIF) Mode
The mixers are bypassed, and the NCO is disabled.
fS/4 Hz IF Mode
The mixers and the NCO are enabled in special downmixing by
fS/4 mode to save power.
Test Mode
Input samples are forced to 0.9599 to positive full scale. The
NCO is enabled. This test mode allows the NCOs to directly
drive the decimation filters.
Figure 74 and Figure 75 show examples of the frequency
translation stage for both real and complex inputs.
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 2
48
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT
f
S
DC
f
S
/32
f
S
/32
cos(ωt)
90°
I
Q
ADC
SAMPLING
AT
f
S
REAL REAL
–sin(ωt)
48-BIT
NCO
POSITIVE FTW VALUES
NEGATIVE FTW VALUES
COMPLEX
–6dB LOSS DUE TO
NCO + MIXER
48-BIT NCO FTW =
ROUND ((
f
S
/3)/
f
S
× 2
48
) =
+9.3825
13
(0x555555555555)
48-BIT NCO FTW =
ROUND ((–
f
S
/3)/
f
S
× 2
48
) =
–9.3825
13
(0xFFFF000000000000)
14808-057
f
S
/2
f
S
/3
f
S
/4
f
S
/8
f
S
/16
f
S
/8
f
S
/4
f
S
/3
f
S
/2
f
S
/16
f
S
/32
f
S
/32
DC
f
S
/32
f
S
/32
DC
Figure 74. DDC NCO Frequency Tuning Word SelectionReal Inputs
AD9694 Data Sheet
Rev. B | Page 40 of 96
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 2
48
QUADRATURE ANALOG MIXER +
2 ADCs + QUADRATURE DIGITAL
MIXER + NCO
COMPLEX INPUT—SAMPLED AT f
S
f
S
/32 f
S
/32
DC
BANDWIDTH OF
INTEREST
POSITIVE FTW VALUES
IMAGE DUE TO
ANALOG I/Q
MISMATCH
REAL
I
Q
QUADRATURE MIXER
I
Q
I
+
Q
Q
I
Q+
+
Q
I
I
COMPLEX
I
Q
–sin(ωt)
ADC
SAMPLING
AT f
S
ADC
SAMPLING
AT f
S
90°
PHASE
48-BIT
NCO 90°
48-BIT NCO FTW =
ROUND ((f
S
/3)/f
S
× 2
48
) =
+9.3825
13
(0x555555555555)
14808-058
f
S
/2 f
S
/3 f
S
/4 f
S
/8 f
S
/16 f
S
/8 f
S
/4 f
S
/3 f
S
/2f
S
/16
f
S
/32 f
S
/32
DC
Figure 75. DDC NCO Frequency Tuning Word SelectionComplex Inputs
DDC NCO AND MIXER LOSS AND SFDR
When mixing a real input signal down to baseband, 6 dB of loss
is introduced in the signal due to filtering of the negative image.
An additional 0.05 dB of loss is introduced by the NCO. The total
loss of a real input signal mixed down to baseband is 6.05 dB. For
this reason, it is recommended that the user compensate for this
loss by enabling the 6 dB of gain in the gain stage of the DDC to
recenter the dynamic range of the signal within the full scale of
the output bits.
When mixing a complex input signal down to baseband, the
maximum value that each I/Q sample can reach is 1.414 × full
scale after it passes through the complex mixer. To avoid over-
range of the I/Q samples and to keep the data bit widths aligned
with real mixing, 3.06 dB of loss is introduced in the mixer for
complex signals. An additional 0.05 dB of loss is introduced by
the NCO. The total loss of a complex input signal mixed down
to baseband is −3.11 dB.
The worst case spurious signal from the NCO is greater than
102 dBc SFDR for all output frequencies.
NUMERICALLY CONTROLLED OSCILLATOR
The AD9694 has a 48-bit NCO for each DDC that enables the
frequency translation process. The NCO allows the input spectrum
to be tuned to dc, where it can be effectively filtered by the subse-
quent filter blocks to prevent aliasing. The NCO can be set up
by providing a frequency tuning word (FTW) and a phase offset
word (POW).
Setting Up the NCO FTW and POW
The NCO frequency value is given by the 32-bit twos
complement number entered in the NCO FTW. Frequencies
between −fS/2 and +fS/2 (fS/2 excluded) are represented using
the following frequency words:
0x800 represents a frequency of −fS/2.
0x000 represents dc (frequency is 0 Hz).
0x7FF represents a frequency of +fS/2 − fS/212.
The NCO frequency tuning word can be calculated using the
following equation:
( )
=
S
S
C
f
ff
FTWNCO ,
mod
2round_
48
where:
NCO_FTW is a 48-bit twos complement number representing
the NCO FTW.
fC is the desired carrier frequency in Hz.
fS is the AD9694 sampling frequency (clock rate) in Hz.
round( ) is a rounding function. For example, round(3.6) = 4
and for negative numbers, round(3.4) = −3.
mod( ) is a remainder function. For example, mod(110,100) =
10 and for negative numbers, mod(–32,10) = −2.
This equation applies to the aliasing of signals in the digital
domain (that is, aliasing introduced when digitizing analog
signals).
Data Sheet AD9694
Rev. B | Page 41 of 96
For example, if the ADC sampling frequency (fS) is 500 MSPS
and the carrier frequency (fC) is 140.312 MHz, then
( )
Hz1089886.7
500
500,312.140mod
2round_
13
48
×
=
=FTWNCO
This, in turn, converts to 0x47D in the 12-bit twos complement
representation for NCO_FTW. The actual carrier frequency,
fC_ACTUAL, is calculated based on the following equation:
MHz312.140
2
_
48
_
=
×
=
S
ACTUAL
C
fFTWNCO
f
A 48-bit POW is available for each NCO to create a known phase
relationship between multiple AD9694 chips or individual DDC
channels inside one AD9694 chip.
Use the following procedure to update the FTW and/or POW
registers to ensure proper operation of the NCO:
1. Write to the FTW registers for all the DDCs.
2. Write to the POW registers for all the DDCs.
3. Synchronize the NCOs either through the DDC NCO soft
reset bit (Register 0x0300, Bit 4), which is accessible through
the SPI or through the assertion of the SYSREF± pin.
It is important to note that the NCOs must be synchronized
either through the SPI or through the SYSREF± pin after all
writes to the FTW or POW registers are complete. This step is
necessary to ensure the proper operation of the NCO.
NCO Synchronization
Each NCO contains a separate phase accumulator word (PAW).
The initial reset value of each PAW is set to zero and the phase
increment value of each PAW is determined by the FTW. The
POW is added to the PAW to produce the instantaneous phase
of the NCO. See the Setting Up the NCO FTW and POW section
for more information.
Use the following two methods to synchronize multiple PAWs
within the chip:
Using the SPI. Use the DDC NCO soft reset bit in the DDC
synchronization control register (Register 0x0300, Bit 4) to
reset all the PAWs in the chip, which is accomplished by
setting the DDC NCO soft reset bit high and then setting
this bit low. This method can only be used to synchronize
DDC channels within the same pair (A/B or C/D) of a
AD9694 chip.
Using the SYSREF± pin. When the SYSREF± pin is enabled
in the SYSREF± control registers (Register 0x0120 and
Register 0x0121) and the DDC synchronization is enabled
in the DDC synchronization control register (Register 0x0300,
Bits[1:0]), any subsequent SYSREF± event resets all the
PAWs in the chip. This method can be used to synchronize
DDC channels within the same AD9694 chip or DDC
channels within separate AD9694 chips.
Mixer
The NCO is accompanied by a mixer. The NCO mixer operation
is similar to that of an analog quadrature mixer. It performs the
downconversion of input signals (real or complex) by using the
NCO frequency as a local oscillator. For real input signals, this
mixer performs a real mixer operation (with two multipliers). For
complex input signals, the mixer performs a complex mixer
operation (with four multipliers and two adders). The mixer
adjusts its operation based on the input signal (real or complex)
provided to each individual channel. The selection of real or
complex inputs can be controlled individually for each DDC
block using Bit 7 of the DDC control registers (Register 0x0310
and Register 0x0330) in conjunction with the pair index register
(Register 0x0009).
AD9694 Data Sheet
Rev. B | Page 42 of 96
FIR FILTERS
OVERVIEW
Four sets of decimate by 2, low-pass, half-band, finite impulse
response (FIR) filters (labeled HB1 FIR, HB2 FIR, HB3 FIR,
and HB4 FIR in Figure 72) follow the frequency translation
stage. After the carrier of interest is tuned down to dc (carrier
frequency = 0 Hz), these filters efficiently lower the sample rate,
while providing sufficient alias rejection from unwanted adjacent
carriers around the bandwidth of interest.
HB1 FIR is always enabled and cannot be bypassed in DDC
mode. The HB2, HB3, and HB4 FIR filters are optional and can
be bypassed for higher output sample rates.
Table 18 shows the different bandwidths selectable by including
different half-band filters. In all cases, the DDC filtering stage
on the AD9694 provides <−0.001 dB of pass-band ripple and
>100 dB of stop band alias rejection.
Table 19 shows the amount of stop band alias rejection for multiple
pass-band ripple/cutoff points. The decimation ratio of the filtering
stage of each DDC can be controlled individually through Bits[1:0]
of the DDC control registers (Register 0x0310 and Register 0x0330)
in conjunction with the pair index register (Register 0x0009).
Table 18. DDC Filter Characteristics
Half-Band
Filter
Selection
Real Output Complex (I/Q) Output
Alias
Protected
Bandwidth
(MHz)
Ideal SNR
Improvement1
(dB)
Pass-
Band
Ripple
(dB)
Alias
Rejection
(dB)
Decimation
Ratio
Output
Sample
Rate
(MSPS)
Decimation
Ratio
Output Sample
Rate (MSPS)
HB1 1 500 2 250 (I) + 250 (Q) 200 1 <−0.0001 >100
HB1 + HB2 2 250 4 125 (I) + 125 (Q) 100 4
HB1 + HB2 +
HB3
4 125 8 62.5 (I) + 62.5 (Q) 50 7
HB1 + HB2 +
HB3 + HB4
8 62.5 16 31.25 (I) + 31.25 (Q) 25 10
1 Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).
Table 19. DDC Filter Alias Rejection
Alias Rejection
(dB)
Pass-Band Ripple/Cutoff
Point (dB)
Alias Protected Bandwidth for Real
(I) Outputs1
Alias Protected Bandwidth for Complex
(I/Q) Outputs
>100 <−0.0001 <40% × fOUT <80% × fOUT
95 <−0.0002 <40.12% × fOUT <80.12% × fOUT
90 <−0.0003 <40.23% × fOUT <80.46% × fOUT
85 <−0.0005 <40.36% × fOUT <80.72% × fOUT
80 <−0.0009 <40.53% × fOUT <81.06% × fOUT
25.07
−0.5
45.17% × f
OUT
90.34% × f
OUT
19.3 −1.0 46.2% × fOUT 92.4% × fOUT
10.7 −3.0 48.29% × fOUT 96.58% × fOUT
1 fOUT = ADC input sample rate ÷ DDC decimation.
Data Sheet AD9694
Rev. B | Page 43 of 96
HALF-BAND FILTERS
The AD9694 offers four half-band filters to enable digital signal
processing of the ADC converted data. These half-band filters
are bypassable and can be individually selected.
HB4 Filter
The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses
an 11-tap, symmetrical, fixed coefficient filter implementation
that is optimized for low power consumption. The HB4 filter is
only used when complex outputs (decimate by 16) or real outputs
(decimate by 8) are enabled; otherwise, it is bypassed. Table 20
and Figure 76 show the coefficients and response of the HB4 filter.
Table 20. HB4 Filter Coefficients
HB4 Coefficient
Number
Normalized
Coefficient
Decimal
Coefficient (15-Bit)
C1, C11 0.006042 99
C2, C10
0
0
C3, C9 −0.049377 −809
C4, C8 0 0
C5, C7 0.293334 4806
C6 0.500000 8192
–250
–200
–150
–100
–50
0
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAGNITUDE (dB)
NORMALIZED FREQUENCY RAD/SAMPLE)
14808-059
Figure 76. HB4 Filter Response
HB3 Filter
The second decimate by 2, half-band, low-pass, FIR filter (HB3)
uses an 11-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption. The HB3 filter
is only used when complex outputs (decimate by 8 or 16) or real
outputs (decimate by 4 or 8) are enabled; otherwise, it is bypassed.
Table 21 and Figure 77 show the coefficients and response of
the HB3 filter.
Table 21. HB3 Filter Coefficients
HB3 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(17-Bit)
C1, C11 0.006638 435
C2, C10 0 0
C3, C9 −0.051055 −3346
C4, C8 0 0
C5, C7 0.294418 19,295
C6 0.500000 32,768
–180
–100
–60
–40
–20
–160
–140
–120
–80
0
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAGNITUDE (dB)
NORMALIZED FREQUENCY RAD/SAMPLE)
14808-060
Figure 77. HB3 Filter Response
HB2 Filter
The third decimate by 2, half-band, low-pass, FIR filter (HB2)
uses a 19-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption.
The HB2 filter is only used when complex or real outputs
(decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed.
Table 22 and Figure 78 show the coefficients and response of
the HB2 filter.
Table 22. HB2 Filter Coefficients
HB2 Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(18-Bit)
C1, C19 0.000671 88
C2, C18 0 0
C3, C17
−0.005325
−698
C4, C16 0 0
C5, C15 0.022743 2981
C6, C14 0 0
C7, C13 −0.074181 −9723
C8, C12 0 0
C9, C11 0.306091 40,120
C10 0.500000 65,536
–180
–100
–60
–40
–20
–160
–140
–120
–80
0
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAGNITUDE (dB)
NORMALIZED FREQUENCY RAD/SAMPLE)
14808-061
Figure 78. HB2 Filter Response
AD9694 Data Sheet
Rev. B | Page 44 of 96
HB1 Filter
The fourth and final decimate by 2, half-band, low-pass, FIR
filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter
implementation that is optimized for low power consumption.
The HB1 filter is always enabled and cannot be bypassed.
Table 23 and Figure 79 show the coefficients and response of
the HB1 filter.
Table 23. HB1 Filter Coefficients
HB1 Coefficient
Number
Normalized
Coefficient
Decimal
Coefficient (20-Bit)
C1, C63 −0.000019 −10
C2, C62
0
0
C3, C61 0.000072 38
C4, C60 0 0
C5, C59 −0.000194 −102
C6, C58 0 0
C7, C57 0.000442 232
C8, C56 0 0
C9, C55 −0.000891 −467
C10, C54 0 0
C11, C53 0.001644 862
C12, C52 0 0
C13, C51
−0.002840
−1489
C14, C50 0 0
C15, C49 0.004653 2440
C16, C48 0 0
C17, C47 −0.007311 −3833
C18, C46 0 0
C19, C45 0.011121 5831
C20, C44 0 0
C21, C43 −0.016553 −8679
C22, C42 0 0
C23, C41 0.024420 12,803
C24, C40
0
0
C25, C39 −0.036404 −19,086
C26, C38 0 0
C27, C37 0.056866 29,814
C28, C36 0 0
C29, C35 −0.101892 −53,421
C30, C34 0 0
C31, C33 0.316883 166,138
C32 0.500000 262,144
–100
–60
–40
–20
–160
–140
–120
–80
0
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
MAGNITUDE (dB)
NORMALIZED FREQUENCY RAD/SAMPLE)
14808-062
Figure 79. HB1 Filter Response
DDC GAIN STAGE
Each DDC contains an independently controlled gain stage. The
gain is selectable as either 0 dB or 6 dB. When mixing a real input
signal down to baseband, it is recommended that the user enable
the 6 dB of gain to recenter the dynamic range of the signal
within the full scale of the output bits.
When mixing a complex input signal down to baseband, the mixer
has already recentered the dynamic range of the signal within the
full scale of the output bits, and no additional gain is necessary.
However, the optional 6 dB gain compensates for low signal
strengths. The downsample by 2 portion of the HB1 FIR filter is
bypassed when using the complex to real conversion stage.
DDC COMPLEX TO REAL CONVERSION
Each DDC contains an independently controlled complex to
real conversion block. The complex to real conversion block
reuses the last filter (HB1 FIR) in the filtering stage and an fS/4
complex mixer to upconvert the signal. After upconverting the
signal, the Q portion of the complex mixer is no longer needed
and is dropped.
Figure 80 shows a simplified block diagram of the complex to
real conversion.
E1 "$69 a
Data Sheet AD9694
Rev. B | Page 45 of 96
LOW-PASS
FILTER
2
I
Q
REAL
HB1 FIR
LOW-PASS
FILTER
2
HB1 FIR
0
1
COMPLEX TO
REAL ENABLE
Q
90°
+
COMPLEX TO REAL CONVERSION
I
Q
I
Q
GAIN STAGE
cos(ωt)
sin(ωt)
f
S
/4
I/REAL
0dB
OR
6dB
0dB
OR
6dB
0dB
OR
6dB
0dB
OR
6dB
14808-063
Figure 80. Complex to Real Conversion Block
DDC EXAMPLE CONFIGURATIONS
Table 24 describes the register settings for multiple DDC example configurations.
Table 24. DDC Example Configurations
Chip
Application
Layer
Chip
Decimation
Ratio
DDC Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of
Virtual
Converters
Required Register Settings2
One DDC 2 Complex Complex 40% × fS 2 Register 0x0009 = 0x01, 0x02, or 0x03 (pair
selection)
Register 0x0200 = 0x01 (one DDC; I/Q selected)
Register 0x0201 = 0x01 (chip decimate by 2)
Register 0x0310 = 0x83 (complex mixer; 0 dB gain;
variable IF; complex outputs; HB1 filter)
Register 0x0311 = 0x04 (DDC I input = ADC
Channel A/Channel C; DDC Q input = ADC
Channel B/Channel D
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
One DDC 4 Complex Complex 20% × fS 2 Register 0x0009 = 0x01, 0x02, or 0x03 (pair
selection)
Register 0x0200 = 0x01 (one DDC; I/Q selected)
Register 0x0201 = 0x02 (chip decimate by 4)
Register 0x0310 = 0x80 (complex mixer; 0 dB gain;
variable IF; complex outputs; HB2 + HB1 filters)
AD9694 Data Sheet
Rev. B | Page 46 of 96
Chip
Application
Layer
Chip
Decimation
Ratio
DDC Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of
Virtual
Converters
Required Register Settings2
Register 0x0311 = 0x04 (DDC I input = ADC
Channel A/C; DDC Q input = ADC Channel B/
Channel D)
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Two DDCs 2 Real Real 20% × fS 2 Register 0x0009 = 0x01, 0x02, or 0x03 (pair
selection)
Register 0x0200 = 0x22 (two DDCs; I only selected)
Register 0x0201 = 0x01 (chip decimate by 2)
Register 0x0310, Register 0x0330 = 0x48 (real
mixer; 6 dB gain; variable IF; real output; HB2 +
HB1 filters)
Register 0x0311 = 0x00 (DDC 0 I input = ADC
Channel A/Channel C; DDC 0 Q input = ADC
Channel A/Channel C)
Register 0x0331 = 0x05 (DDC 1 I input = ADC
Channel B/Channel D; DDC 1 Q input = ADC
Channel B/Channel D
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Register 0x0334, Register 0x0335, Register 0x0336,
Register 0x0337, Register 0x0338, Register 0x033A,
Register 0x033D, Register 0x033E, Register 0x033F,
Register 0x0340, Register 0x0341, Register 0x0342 =
FTW and POW set as required by application for
DDC 1
Two DDCs 2 Complex Complex 40% × fS 4 Register 0x0009 = 0x01, 0x02, or 0x03 (pair
selection)
Register 0x0200 = 0x22 (two DDCs; I only
selected)
Register 0x0201 = 0x01 (chip decimate by 2)
Register 0x0310, Register 0x0330 = 0x4B (complex
mixer; 6 dB gain; variable IF; complex output; HB1
filter)
Register 0x0311, Register 0x0331 = 0x04 (DDC 0 I
input = ADC Channel A/Channel C; DDC 0 Q input =
ADC Channel B/Channel D)
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Register 0x0334, Register 0x0335, Register 0x0336,
Register 0x0337, Register 0x0338, Register 0x033A,
Register 0x033D, Register 0x033E, Register 0x033F,
Register 0x0340, Register 0x0341, Register 0x0342 =
FTW and POW set as required by application for
DDC 1
Data Sheet AD9694
Rev. B | Page 47 of 96
Chip
Application
Layer
Chip
Decimation
Ratio
DDC Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of
Virtual
Converters
Required Register Settings2
Two DDCs 4 Complex Complex 20% × fS 4 Register 0x0009 = 0x01, 0x02, or 0x03 (pair selection)
Register 0x0200 = 0x02 (two DDCs; I/Q selected)
Register 0x0201 = 0x02 (chip decimate by 4)
Register 0x0310, Register 0x0330 = 0x80 (complex
mixer; 0 dB gain; variable IF; complex outputs;
HB2 + HB1 filters)
Register 0x0311, Register 0x0331 = 0x04 (DDC I
input = ADC Channel A/Channel C; DDC Q input =
ADC Channel B/Channel D)
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Register 0x0334, Register 0x0335, Register 0x0336,
Register 0x0337, Register 0x0338, Register 0x033A,
Register 0x033D, Register 0x033E, Register 0x033F,
Register 0x0340, Register 0x0341, Register 0x0342 =
FTW and POW set as required by application for
DDC 1
Two DDCs 4 Complex Real 10% × fS 2 Register 0x0009 = 0x01, 0x02, or 0x03 (pair
selection)
Register 0x0200 = 0x22 (two DDCs; I only
selected)
Register 0x0201 = 0x02 (chip decimate by 4)
Register 0x0310, Register 0x0330 = 0x89 (complex
mixer; 0 dB gain; variable IF; real output; HB3 +
HB2 + HB1 filters)
Register 0x0311, Register 0x0331 = 0x04 (DDC I
input = ADC Channel A/Channel C; DDC Q input =
ADC Channel B/Channel D)
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Register 0x0334, Register 0x0335, Register 0x0336,
Register 0x0337, Register 0x0338, Register 0x033A,
Register 0x033D, Register 0x033E, Register 0x033F,
Register 0x0340, Register 0x0341, Register 0x0342 =
FTW and POW set as required by application for
DDC 1
Two DDCs 4 Real Real 10% × fS 2 Register 0x0009 = 0x01, 0x02, or 0x03 (pair
selection)
Register 0x0200 = 0x22 (two DDCs; I only
selected)
Register 0x0201 = 0x02 (chip decimate by 4)
Register 0x0310, Register 0x0330 = 0x49 (real
mixer; 6 dB gain; variable IF; real output; HB3 +
HB2 + HB1 filters)
Register 0x0311 = 0x00 (DDC 0 I input = ADC
Channel A/Channel C; DDC 0 Q input = ADC
Channel A/Channel C)
AD9694 Data Sheet
Rev. B | Page 48 of 96
Chip
Application
Layer
Chip
Decimation
Ratio
DDC Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of
Virtual
Converters
Required Register Settings2
Register 0x0331 = 0x05 (DDC 1 I input = ADC
Channel B/Channel D; DDC 1 Q input = ADC
Channel B/Channel D)
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Register 0x0334, Register 0x0335, Register 0x0336,
Register 0x0337, Register 0x0338, Register 0x033A,
Register 0x033D, Register 0x033E, Register 0x033F,
Register 0x0340, Register 0x0341, Register 0x0342 =
FTW and POW set as required by application for
DDC 1
Two DDCs 4 Real Complex 20% × fS 4 Register 0x0009 = 0x01, 0x02, or 0x03 (pair
selection)
Register 0x0200 = 0x02 (two DDCs; I/Q selected)
Register 0x0201 = 0x02 (chip decimate by 4)
Register 0x0310, Register 0x0330 = 0x40 (real
mixer; 6 dB gain; variable IF; complex output;
HB2 + HB1 filters)
Register 0x0311 = 0x00 (DDC 0 I input = ADC
Channel A/Channel C; DDC 0 Q input = ADC
Channel A/Channel C)
Register 0x0331 = 0x05 (DDC 1 I input = ADC
Channel B/Channel D; DDC 1 Q input = ADC
Channel B/Channel D)
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Register 0x0334, Register 0x0335, Register 0x0336,
Register 0x0337, Register 0x0338, Register 0x033A,
Register 0x033D, Register 0x033E, Register 0x033F,
Register 0x0340, Register 0x0341, Register 0x0342 =
FTW and POW set as required by application for
DDC 1
Two DDCs 8 Real Real 5% × fS 2 Register 0x0009 = 0x01, 0x02, or 0x03 (pair selection)
Register 0x0200 = 0x22 (two DDCs; I only selected)
Register 0x0201 = 0x03 (chip decimate by 8)
Register 0x0310, Register 0x0330 = 0x4A (real
mixer; 6 dB gain; variable IF; real output; HB4 +
HB3 + HB2 + HB1 filters)
Register 0x0311 = 0x00 (DDC 0 I input = ADC
Channel A/Channel C; DDC 0 Q input = ADC
Channel A/Channel C)
Register 0x0331 = 0x05 (DDC 1 I input = ADC
Channel B/Channel D; DDC 1 Q input = ADC
Channel B/Channel D)
Data Sheet AD9694
Rev. B | Page 49 of 96
Chip
Application
Layer
Chip
Decimation
Ratio
DDC Input
Type
DDC
Output
Type
Bandwidth
Per DDC1
No. of
Virtual
Converters
Required Register Settings2
Register 0x0314, Register 0x0315, Register 0x0316,
Register 0x0317, Register 0x0318, Register 0x031A,
Register 0x031D, Register 0x031E, Register 0x031F,
Register 0x0320, Register 0x0321, Register 0x0322 =
FTW and POW set as required by application for
DDC 0
Register 0x0334, Register 0x0335, Register 0x0336,
Register 0x0337, Register 0x0338, Register 0x033A,
Register 0x033D, Register 0x033E, Register 0x033F,
Register 0x0340, Register 0x0341, Register 0x0342 =
FTW and POW set as required by application for
DDC 1
1 fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop band alias rejection.
2 The NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed. This synchronization
is necessary to ensure the proper operation of the NCO. See the NCO Synchronization section for more information.
AD9694 Data Sheet
Rev. B | Page 50 of 96
DIGITAL OUTPUTS
INTRODUCTION TO THE JESD204B INTERFACE
The AD9694 digital outputs are designed to the JEDEC standard,
JESD204B, serial interface for data converters. JESD204B is a
protocol to link the AD9694 to a digital processing device over
a serial interface with lane rates of up to 15 Gbps. The benefits
of the JESD204B interface over LVDS include a reduction in
required board area for data interface routing, and an ability to
enable smaller packages for converter and logic devices.
SETTING UP THE AD9694 DIGITAL INTERFACE
The following SPI writes are required for the AD9694 at startup
and each time the ADC is reset (datapath reset, soft reset, link
power-down/power-up, or hard reset):
1. Write 0x4F to Register 0x1228.
2. Write 0x0F to Register 0x1228.
3. Write 0x04 to Register 0x1222.
4. Write 0x00 to Register 0x1222.
5. Write 0x08 to Register 0x1262.
6. Write 0x00 to Register 0x1262.
The JESD204B data transmit blocks, JTX, assemble the parallel
data from the ADC into frames and uses 8-bit/10-bit encoding
as well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of special control
characters during the initial establishment of the link. Additional
control characters are embedded in the data stream to maintain
synchronization thereafter. A JESD204B receiver is required to
complete the serial link. For additional details on the JESD204B
interface, refer to the JESD204B standard.
The JESD204B data transmit blocks in the AD9694 map up to
two physical ADCs or up to four virtual converters (when the
DDCs are enabled) over each of the two JESD204B links. Each
link can be configured to use one or two JESD204B lanes for up
to a total of four lanes for the AD9694 chip. The JESD204B
specification refers to a number of parameters to define the
link, and these parameters must match between the JESD204B
transmitter (the AD9694 output) and the JESD204B receiver
(the logic device input). The JESD204B outputs of the AD9694
function effectively as two individual JESD204B links. The two
JESD204B links can be synchronized if desired using the
SYSREF± input.
Each JESD204B link is described according to the following
parameters:
L is the number of lanes per converter device (lanes per
link) (AD9694 value = 1 or 2)
M is the number of converters per converter device (virtual
converters per link) (AD9694 value = 1, 2, or 4)
F is the number of octets per frame (AD9694 value = 1, 2,
4, or 8)
is the number of bits per sample (JESD204B word size)
(AD9694 value = 8 or 16)
N is the converter resolution (AD9694 value = 7 to 16)
CS is the number of control bits per sample (AD9694 value =
0, 1, 2, or 3)
K is the number of frames per multiframe (AD9694 value = 4,
8, 12, 16, 20, 24, 28, or 32 )
S is the samples transmitted per single converter per frame
cycle (AD9694 value is set automatically based on L, M, F,
and N΄)
HD is high density mode (AD9694 value is set automatically
based on L, M, F, and )
CF is the number of control words per frame clock cycle per
converter device (AD9694 value = 0)
Figure 81 shows a simplified block diagram of the AD9694
JESD204B link. By default, the AD9694 is configured to use four
converters and four lanes. The Converter A and Converter B data
is output to SERDOUTAB and SERDOUTAB, and the
Converter C and Converter D data is output to SERDOUTCD0±
and SERDOUTCD1±. The AD9694 allows other configurations,
such as combining the outputs of each pair of converters into a
single lane, or changing the mapping of the digital output paths.
These modes are set up via a quick configuration register in the
SPI register map, including additional customizable options.
By default in the AD9694, the 14-bit converter word from each
converter is separated into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or a pseudorandom number sequence.
The tail bits can also be replaced with control bits indicating
overrange, SYSREF±, or fast detect output. Control bits are
filled and inserted MSB first such that enabling CS = 1 activates
Control Bit 2, enabling CS = 2 activates Control Bit 2 and
Control Bit 1, and enabling CS = 3 activates Control Bit 2,
Control Bit 1, and Control Bit 0.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is recommended to avoid spectral peaks
when transmitting similar digital data patterns. The scrambler
uses a self synchronizing, polynomial-based algorithm defined
by the equation 1 + x14 + x15. The descrambler in the receiver is
a self synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8-bit/10-bit encoder.
The 8-bit/10-bit encoder works by taking eight bits of data (an
octet) and encoding them into a 10-bit symbol. Figure 82 shows
how the 14-bit data is taken from the ADC, the tail bits are added,
the two octets are scrambled, and how the octets are encoded
into two 10-bit symbols. Figure 82 shows the default data format.
Data Sheet AD9694
Rev. B | Page 51 of 96
CONVERTER A
INPUT
CONVERTER B
INPUT
CONVERTER C
INPUT
CONVERTER D
INPUT
ADC A
ADC B
ADC C
ADC D
SERDOUTAB0+
SERDOUTAB0–
SERDOUTAB1+
SERDOUTAB1–
SERDOUTCD0+
SERDOUTCD0–
SERDOUTCD1+
SERDOUTCD1–
SYSREF±
SYNCINAB±
SYNCINCD±
14808-064
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
0x05B2,
0x05B3)
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
0x05B2,
0x05B3)
Figure 81. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)
JESD204B SAMPLE
CONSTRUCTION
SERDOUT0±
SERDOUT1±
TAIL BITS
REG 0x0571[6]
FRAME
CONSTRUCTION
SCRAMBLER
1 +
x
14
+
x
15
(OPTIONAL)
8-BIT/10-BIT
ENCODER
SERIALIZER
ADC
ADC TEST PATTERNS
(REG 0x0550,
REG 0x0551 TO REG 0x0558)
JESD204B LONG
TRANSPORT TEST
PATTERN
REG 0x0571[5]
JESD204B DATA
LINK LAYER TEST
PATTERNS
REG 0x0574[2:0]
MSB
LSB
SYMBOL0 SYMBOL1
OCTET0
OCTET1
OCTET0
OCTET1
MSB
LSB
MSB
LSB
CONTROL BITS
JESD204B
INTERFACE TEST
PATTERNS
(REG 0x0573,
REG 0x0551 TO REG 0x0558)
14808-065
a
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C2
T
S7
S6
S5
S4
S3
S2
S1
S0
b c d e f g h i j
ab. . . . . . . .a bi j i j
a b c d e f g h i j
C2
C1
C0
S7
S6
S5
S4
S3
S2
S1
S0
Figure 82. ADC Output Data Path Showing Data Framing
TRANSPORT
LAYER PHYSICAL
LAYER
DATA LINK
LAYER
Tx OUTPUT
SAMPLE
CONSTRUCTION FRAME
CONSTRUCTION SCRAMBLER ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER CROSSBAR
MUX SERIALIZER
PROCESSED
SAMPLES
FROM ADC
SYSREF±
SYNCINB±x
14808-066
Figure 83. Data Flow
H|H~~||H\|~~~|\|-~~||\H-"HIHmIH\ e—e_+_e_
AD9694 Data Sheet
Rev. B | Page 52 of 96
FUNCTIONAL OVERVIEW
The block diagram in Figure 83 shows the flow of data through
each of the two JESD204B links from the sample input to the
physical output. The processing can be divided into layers that
are derived from the open source initiative (OSI) model widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer, and
physical layer (serializer and output driver).
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. These octets are sent to the data link
layer. The transport layer mapping is controlled by rules derived
from the link parameters. Tail bits are added to fill gaps where
required. Use the following equation to determine the number
of tail bits within a sample (JESD204B word):
T = NCS
Data Link Layer
The data link layer is responsible for the low level functions of
passing data across the link. These functions include optionally
scrambling the data, inserting control characters for multichip
synchronization, lane alignment, or monitoring, and encoding
8-bit octets into 10-bit symbols. The data link layer is also
responsible for sending the initial lane alignment sequence
(ILAS), which contains the link configuration data used by the
receiver to verify the settings in the transport layer.
Physical Layer (PHY)
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data.
JESD204B LINK ESTABLISHMENT
The AD9694 JESD204B transmitter (