LTM8023 Datasheet by Analog Devices Inc.

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LTLII‘IM TECHNOLOGY M L7 LJUW 1
LTM8023
1
8023fj
For more information www.linear.com/LTM8023
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
POWER LOSS (W)
55
50
0.1 1 10
8023 TA01b
65
60
90
80
70
85
75
0.2
0.4
0.6
0.8
0
1.2
1.0
1.8
1.6
1.4
VIN = 12V
VOUT = 3.3V
f = 650 kHz
FEATURES
APPLICATIONS
DESCRIPTION
2A, 36V DC/DC
Step-Down µModule
Regulator
The LT M
®
8023 is a complete 2A, DC/DC step-down power
supply. Included in the package are the switching controller,
power switches, inductor, and all support components.
Operating over an input voltage range of 3.6V to 36V, the
LTM8023 supports an output voltage range of 0.8V to 10V,
and a switching frequency range of 200kHz to 2.4MHz,
each set by a single resistor. Only the bulk input and output
filter capacitors are needed to finish the design.
The low profile package enables utilization of unused
space on the bottom of PC boards for high density point
of load regulation.
The LTM8023 is packaged in a thermally enhanced, com-
pact and low profile over-molded land grid array (LGA)
and ball grid array (BGA) packages suitable for automated
assembly by standard surface mount equipment. The
LTM8023 is available with SnPb (BGA) or RoHS compli-
ant terminal finish.
5.5VIN to 36VIN, 3.3V/2A DC/DC µModule
®
Converter
n Complete Step-Down Switch Mode Power Supply
n Wide Input Voltage Range: 3.6V to 36V
n 2A Output Current
n 0.8V to 10V Output Voltage
n Selectable Switching Frequency: 200kHz to 2.4MHz
n Current Mode Control
n Programmable Soft-Start
n SnPb (BGA) or RoHS Compliant (LGA and BGA)
Finish
n Tiny, Low Profile, Surface Mount LGA (9mm ×
11.25mm × 2.82mm) and BGA (9mm × 11.25mm ×
3.42mm) Packages
n Automotive Battery Regulation
n Power for Portable Products
n Distributed Supply Regulation
n Industrial Supplies
n Wall Transformer Regulation
Efficiency and Power Loss
L, LT , LT C , LT M , Linear Technology, the Linear logo, Burst Mode and µModule are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
VOUT
VIN
RUN/SS
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
PGOOD
SHARE
BIAS
RT
ADJ
LTM8023
154k49.9k
8023 TA01
VOUT
3.3V
2A
SYNC
VIN*
5.5V TO 36V
SELECTABLE
OPERATING
FREQUENCY
2.2µF AUX
GND
22µF
LTM8023 , .0. 0.. 0" .0. O. 0...... 0...... 0...... 0...... 0.0.0.0; L7LJCUEN2
LTM8023
2
8023fj
For more information www.linear.com/LTM8023
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN, RUN/SS Voltage ................................................. 40V
ADJ, RT, SHARE Voltage .............................................5V
VOUT, AUX .................................................................10V
PGOOD, SYNC...........................................................30V
BIAS ..........................................................................16V
(Note 1)
VIN + BIAS ................................................................. 56V
Internal Operating Temperature
(Note 2) .................................................. 40°C to 125°C
Storage Temperature.............................. –55°C to 125°C
Solder Temperature ............................................... 250°C
GND (BANK 3)
VOUT
(BANK 2)
AUX
VIN
(BANK 1)
RT
HBA D
LGA PACKAGE
50-LEAD (11.25mm × 9mm × 2.82mm)
C
6
7
5
1
2
3
4
E F G
ADJ
BIAS
RUN/SS
SHARE
PGOOD
SYNC
GND (BANK 3)
VOUT
(BANK 2)
AUX
VIN
(BANK 1)
RT
HBA D
BGA PACKAGE
50-LEAD (11.25mm × 9mm × 3.42mm)
C
6
7
5
1
2
3
4
E F G
ADJ
BIAS
RUN/SS
SHARE
PGOOD
SYNC
TJMAX = 125°C, θJA = 30.4°C/W, θJCbottom = 12.2°C/W,
θJCtop = 23.9°C/W, θJB = 12.1°C/W, WEIGHT = 0.9g
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
TJMAX = 125°C, θJA = 32.1°C/W, θJCbottom = 14.8°C/W,
θJCtop = 23.7°C/W, θJB = 14.6°C/W, WEIGHT = 0.9g
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ORDER INFORMATION
PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
DEVICE FINISH CODE
LTM8023EV#PBF Au (RoHS) LTM8023V e4 LGA 3 –40°C to 85°C
LTM8023IV#PBF Au (RoHS) LTM8023V e4 LGA 3 –40°C to 85°C
LTM8023MPV#PBF Au (RoHS) LTM8023MPV e4 LGA 3 –55°C to 125°C
LTM8023EY#PBF SAC305 (RoHS) LTM8023Y e1 BGA 3 –40°C to 85°C
LTM8023IY#PBF SAC305 (RoHS) LTM8023Y e1 BGA 3 –40°C to 85°C
LTM8023IY SnPb (63/37) LTM8023Y e0 BGA 3 –40°C to 85°C
LTM8023MPY#PBF SAC305 (RoHS) LTM8023Y e1 BGA 3 –55°C to 125°C
LTM8023MPY SnPb (63/37) LTM8023Y e0 BGA 3 –55°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking:
www.linear.com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
LTM8023 L7 LJUW 3
LTM8023
3
8023fj
For more information www.linear.com/LTM8023
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VRUN/SS = 10V, VBIAS = 3V, RT = 60.4k, COUT = 4.7µF unless
otherwise specified.
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM8023E is guaranteed to meet performance specifications
from 0°C to 85°C ambient. Specifications over the full –40°C to
85°C ambient operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM8023I is guaranteed to meet specifications over the full –40°C to 85°C
ambient operating temperature range. The LTM8023MP is guaranteed to
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input DC Voltage l3.6 36 V
VOUT Output DC Voltage 0A < IOUT ≤ 2A, RADJ Open, COUT = 51µF (Note 3)
0A < IOUT ≤ 2A, RADJ = 43.2k, COUT = 51µF (Note 3)
0.8
10
V
V
RADJ(MIN) Minimum Allowable RADJ (Note 4) 42.2 kΩ
IOUT Continuous Output DC Current 4 ≤ VIN ≤ 36, COUT = 51µF 0 2 A
IQVIN VIN Quiescent Current VRUN/SS = 0.2V, RT = 174k
VBIAS = 3V, Not Switching, RT = 174k (E, I)
VBIAS = 3V, Not Switching, RT = 174k (MP)
VBIAS = 0V, Not Switching, RT = 174k
l
l
0.1
25
25
85
0.5
60
350
120
µA
µA
µA
µA
IQBIAS BIAS Quiescent Current VRUN/SS = 0.2V, RT = 174k
VBIAS = 3V, Not Switching, RT = 174k (E, I)
VBIAS = 3V, Not Switching, RT = 174k (MP)
VBIAS = 0V, Not Switching, RT = 174k
l
l
0.03
50
50
1
0.5
120
200
5
µA
µA
µA
µA
ΔVOUT/VOUT Line Regulation 5 ≤ VIN ≤ 36, IOUT = 1A, VOUT = 3.3V, COUT = 51µF 0.1 %
ΔVOUT/VOUT Load Regulation VIN = 24V, 0 ≤ IOUT ≤ 2A, VOUT = 3.3V, COUT = 51µF 0.4 %
VOUT(AC_RMS) Output Ripple (RMS) VIN = 24V, IOUT = 2A, VOUT = 3.3V, COUT = 51µF 10 mV
fSW Switching Frequency RT = 113k, COUT = 51µF 325 kHz
ISC(OUT) Output Short Circuit Current VIN = 36V, VOUT = 0V (Note 5) 2.9 A
VADJ Voltage at ADJ Pin COUT = 51µF l765 790 805 mV
VBIAS(MIN) Minimum BIAS Voltage for Proper
Operation
2.3 2.8 V
IADJ Current Out of ADJ Pin ADJ = 1V, COUT = 51µF 2 µA
IRUN/SS RUN/SS Pin Current VRUN/SS = 2.5V 5 10 µA
VIH(RUN/SS) RUN/SS Input High Voltage COUT = 51µF 2.5 V
VIL(RUN/SS) RUN/SS Input Low Voltage COUT = 51µF 0.2 V
VPGOOD(TH) PGOOD Threshold VOUT Rising 730 mV
IPGOOD(O) PGOOD Leakage VPGOOD = 30V 0.1 1 µA
IPGOOD(SINK) PGOOD Sink Current VPGOOD = 0.4V 200 800 µA
VSYNCIL SYNC Input Low Threshold fSYNC = 550kHz, COUT = 51µF 0.5 V
VSYNCIH SYNC Input High Threshold fSYNC = 550kHz, COUT = 51µF 0.7 V
ISYNCBIAS SYNC Pin Bias Current VSYNC = 0V 0.1 µA
meet specifications over the full –55°C to 125°C temperature range. Note
that the maximum internal temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 3: COUT = 51µF is composed of a 4.7µF ceramic capacitor in parallel
with a 47µF electrolytic.
Note 4: Guaranteed by design.
Note 5: Short circuit current at VIN = 36V is guaranteed by characterization
and correlation. 100% tested at VIN = 10V
LTM8023 FREQUENCY DMMENDED N TAELH
LTM8023
4
8023fj
For more information www.linear.com/LTM8023
OUTPUT CURRENT (mA)
INPUT CURRENT (mA)
400
0
200
8023 G09
800
600
2000
1800
1400
1200
1600
1000
VOUT = 3.3V
0 500 1000 1500 2000
5VIN
12VIN
24VIN
36VIN
OUTPUT CURRENT (mA)
INPUT CURRENT (mA)
400
0
200
8023 G08
800
600
1200
1000
VOUT = 5V
0 500 1000 1500 2000
12VIN
24VIN
36VIN
OUTPUT CURRENT (mA)
INPUT CURRENT (mA)
400
0
200
8023 G07
800
600
1600
1400
1200
1000
VOUT = 8V
0 500 1000 1500 2000
12VIN
24VIN
36VIN
OUTPUT CURRENT (A)
0.01 0.1 1
EFFICIENCY (%)
60
50
55
8023 G03
70
65
90
85
80
75
VOUT = 3.3V
5VIN
12VIN
24VIN
36VIN
OUTPUT CURRENT (A)
EFFICIENCY (%)
40
20
30
8023 G01
60
50
100
90
80
70
VOUT = 8V
0.01 0.1 1
12VIN
24VIN
36VIN
OUTPUT CURRENT (A)
0.01 0.1 1
EFFICIENCY (%)
60
50
55
8023 G02
70
65
90
85
80
75
VOUT = 5V
12VIN
24VIN
36VIN
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Required Input Voltage
vs Output Voltage
36VIN Start-Up Waveforms
(5VOUT)
36VIN Start-Up Waveforms
(3.3VOUT)
Input Current vs Output Current
Input Current vs Output Current
Input Current vs Output Current
Efficiency (8VOUT)
Efficiency (5VOUT)
Efficiency (3.3VOUT)
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
6
2
4
8023 G04
10
8
20
18
16
14
12
IOUT = 2A
OPERATING FREQUENCY
AS RECOMMENDED
IN TABLE 1
0 108642
8023 G05
RUN/SS
5V/DIV
VIN = 36V
IOUT = 2A
VBIAS = 3V
50µs/DIV
VOUT
2V/DIV
IIN
0.2A/DIV
8023 G06
VIN = 36V
IOUT = 2A
VBIAS = 3V
RUN/SS
5V/DIV
50µs/DIV
VOUT
2V/DIV
IIN
0.2A/DIV
TA = 25°C unless otherwise noted
LTM8023 , , I /_ ____________ ____ , ’ ." ’z’ '52,” / _ ., __ / .*'/ x2; I : L7 LJUW 5
LTM8023
5
8023fj
For more information www.linear.com/LTM8023
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
0
8023 G13
500
2500
2000
1500
1000
0 10 20 30 40
25°C
40°C
85°C
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
2000
1600
1800
8023 G10
2400
2200
3200
3000
2800
2600
0 10 20 30 40
BIAS Current vs Load Current
TYPICAL PERFORMANCE CHARACTERISTICS
Output Short-Circuit Current
vs Input Voltage
LOAD CURRENT (mA)
BIAS CURRENT (mA)
10
0
5
8023 G11
20
15
30
25
0 500 1000 1500 2000
3.3VOUT
5VOUT
8VOUT
TA = 25°C unless otherwise noted
Load Current
vs Input Voltage (5VOUT, LGA)
Load Current
vs Input Voltage (3.3VOUT, LGA)
Maximum Load Current
vs Input Voltage (8VOUT, LGA)
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
0
8023 G14
500
2500
2000
1500
1000
0 10 20 30 40
25°C
40°C
85°C
INPUT VOLTAGE (V)
0
8023 G15
500
2500
2000
1500
1000
0 10 20 30 40
25°C
40°C
85°C
3.3VOUT Junction Temperature
vs Load (LGA)
5VOUT Junction Temperature
vs Load (LGA)
8VOUT Junction Temperature
vs Load (LGA)
CURRENT (mA)
TEMPERATURE RISE (°C)
0
8023 G16
5
50
45
40
35
30
25
20
15
10
0 500 1000 1500 2000 2500
12VIN
24VIN
36VIN
CURRENT (mA)
TEMPERATURE RISE (°C)
0
8023 G17
60
50
40
30
20
10
0 500 1000 1500 2000 2500
12VIN
24VIN
36VIN
CURRENT (mA)
TEMPERATURE RISE (°C)
0
8023 G18
80
50
60
70
40
30
20
10
0 500 1000 1500 2000 2500
16VIN
24VIN
36VIN
LTM8023 6 L7LJ1‘JW
LTM8023
6
8023fj
For more information www.linear.com/LTM8023
TYPICAL PERFORMANCE CHARACTERISTICS
3.3VOUT Temperature Rise vs
Load Current (BGA)
TA = 25°C unless otherwise noted
LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
0
10
8023 G19
30
20
60
50
40
0 200015001000500 2500
12VIN
24VIN
36VIN
LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
0
10
8023 G20
30
20
60
50
40
0 200015001000500 2500
12VIN
24VIN
36VIN
LOAD CURRENT (mA)
TEMPERATURE RISE (°C)
0
20
10
8023 G21
50
60
30
40
90
80
70
0 200015001000500 2500
18VIN
24VIN
36VIN
5VOUT Temperature Rise vs
Load Current (BGA)
8VOUT Temperature Rise vs
Load Current (BGA)
LTM8023 L7 LJUW 7
LTM8023
7
8023fj
For more information www.linear.com/LTM8023
VIN (Bank 1): The VIN pin supplies current to the LTM8023’s
internal regulator and to the internal power switch. This
pin must be locally bypassed with an external, low ESR
capacitor of at least 2.2µF.
VOUT (Bank 2): Power Output Pins. Apply the output filter
capacitor and the output load between these pins and
GND pins.
AUX (Pin F5): Low Current Voltage Source for BIAS. The
VAUX pin is internally connected to VOUT and is placed
adjacent to the BIAS pin to ease printed circuit board
routing. Although this pin is internally connected to VOUT,
do NOT connect this pin to the load. If this pin is not tied
to BIAS, leave it floating.
BIAS (Pin G5): The BIAS pin connects to the internal power
bus. Connect to a power source greater than 2.8V. If the
output is greater than 2.8V, connect this pin there. If the
output voltage is less, connect this to a voltage source
between 2.8V and 16V. Also, make sure that BIAS + VIN
is less than 56V.
RUN/SS (Pin H5): Tie RUN/SS pin to ground to shut down
the LTM8023. Tie to 2.5V or more for normal operation.
If the shutdown feature is not used, tie this pin to the VIN
pin. RUN/SS also provides a soft-start function; see the
Applications Information section.
GND (Bank 3): Tie these GND pins to a local ground plane
below the LTM8023 and the circuit components. In most
applications, the bulk of the heat flow out of the LTM8023
is through these pads, so the printed circuit design has a
PIN FUNCTIONS
large impact on the thermal performance of the part. See
the PCB Layout and Thermal Consideration sections for
more details. Return the feedback divider (RADJ) to this net.
RT (Pin G7): The RT pin is used to program the switching
frequency of the LTM8023 by connecting a resistor from
this pin to ground. The Applications Information section of
the data sheet includes a table to determine the resistance
value based on the desired switching frequency. Minimize
capacitance at this pin.
SHARE (Pin F7): Tie this to the SHARE pin of another
LTM8023 when paralleling the outputs. Otherwise, do not
connect (leave floating).
SYNC (Pin G6): This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode
®
operation
at low output loads. Tie to a stable voltage source greater
than 0.7V to disable Burst Mode operation.
Do not leave
this pin floating
. Tie to a clock source for synchronization.
Clock edges should have rise and fall times faster than 1µs.
See synchronizing section in Applications Information.
PGOOD (Pin H6): The PGOOD pin is the open-collector
output of an internal comparator. PG remains low until
the ADJ pin is within 10% of the final regulation voltage.
PG output is valid when VIN is above 3.6V and RUN/SS is
high. If this function is not used, leave this pin floating.
ADJ (Pin H7): The LTM8023 regulates its ADJ pin to 0.79V.
Connect the adjust resistor from this pin to ground. The
value of RADJ is given by the equation RADJ = 394.21/
(VOUT – 0.79), where RADJ is in kΩ.
LTM8023 8 L7LJ1‘JW
LTM8023
8
8023fj
For more information www.linear.com/LTM8023
BLOCK DIAGRAM
VIN
8023 BD
BIAS
AUX
PGOOD
CURRENT MODE
CONTROLLER
VOUT
10µF4.7pF
4.7µH
0.1µF
RUN/SS
SHARE
499k
SYNC
RTADJGND
LTM8023 L7 LJUW 9
LTM8023
9
8023fj
For more information www.linear.com/LTM8023
OPERATION
The LTM8023 is a standalone nonisolated step-down
switching DC/DC power supply. It can deliver up to 2A of
DC output current with only bulk external input and output
capacitors. This module provides a precisely regulated
output voltage programmable via one external resistor
from 0.8VDC to 10VDC. The input voltage range is 3.6V to
36V. Given that the LTM8023 is a step-down converter,
make sure that the input voltage is high enough to support
the desired output voltage and load current. A simplified
Block Diagram is given on the previous page.
The LTM8023 contains a current mode controller, power
switching element, power inductor, power Schottky diode
and a modest amount of input and output capacitance.
The LTM8023 is a fixed frequency PWM regulator. The
switching frequency is set by simply connecting the
appropriate resistor value from the RT pin to GND.
An internal regulator provides power to the control cir-
cuitry. The bias regulator normally draws power from the
VIN pin, but if the BIAS pin is connected to an external
voltage higher than 2.8V, bias power will be drawn from
the external source (typically the regulated output volt-
age). This improves efficiency. The RUN/SS pin is used
to place the LTM8023 in shutdown, disconnecting the
output and reducing the input current to less than 1µA.
To further optimize efficiency, the LTM8023 automatically
switches to Burst Mode operation in light load situations.
Between bursts, all circuitry associated with controlling
the output switch is shut down reducing the input supply
current to 50µA in a typical application. The oscillator
reduces the LTM8023’s operating frequency when the
voltage at the ADJ pin is low. This frequency foldback helps
to control the output current during start-up and overload.
The LTM8023 contains a power good comparator which
trips when the ADJ pin is at 92% of its regulated value.
The PGOOD output is an open-collector transistor that is
off when the output is in regulation, allowing an external
resistor to pull the PGOOD pin high. Power good is valid
when the LTM8023 is enabled and VIN is above 3.6V.
For most applications, the design process is straight
forward, summarized as follows:
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
2. Apply the recommended CIN, COUT, RADJ and RT values.
3. Connect BIAS as indicated.
While these component combinations have been tested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Capacitor Selection Considerations
The CIN and COUT capacitor values in Table 1 are the
minimum recommended values for the associated oper-
ating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir-
cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
APPLICATIONS INFORMATION
LTM8023
LTM8023
10
8023fj
For more information www.linear.com/LTM8023
APPLICATIONS INFORMATION
Table 1. Recommended Component Values and Configuration (TA = 25°C)
VIN VOUT CIN COUT RADJ BIAS fOPTIMAL (kHz) RT(OPTIMAL) fMAX (kHz) RT(MIN)
3.6V to 36V 0.82V 10µF 200µF 1206 13M ≥2.8V, <16V 250 150k 250 150k
3.6V to 36V 1.00V 10µF 147µF 1206 1.87M ≥2.8V, <16V 300 124k 300 124k
3.6V to 36V 1.20V 10µF 100µF 1206 953k ≥2.8V, <16V 350 105k 350 105k
3.6V to 36V 1.50V 10µF 100µF 1206 549k ≥2.8V, <16V 400 88.7k 400 88.7k
3.6V to 36V 1.80V 4.7µF 100µF 1206 383k ≥2.8V, <16V 450 79k 450 79k
3.6V to 36V 2.00V 2.2µF 68µF 1206 324k ≥2.8V, <16V 450 79k 500 69.8k
3.6V to 36V 2.20V 2.2µF 47µF 1206 274k ≥2.8V, <16V 500 69.8k 550 61.9k
4.1V to 36V 2.50V 2.2µF 47µF 1206 226k ≥2.8V, <16V 550 61.9k 615 54.9k
5.5V to 36V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 750 42.2k
7.5V to 36V 5.00V 2.2µF 10µF 0805 93.1k AUX 650 49.9k 890 34.8k
3.6V to 15V 0.82V 10µF 200µF 1206 13M VIN 350 105k 650 49.9k
3.6V to 15V 1.00V 10µF 147µF 1206 1.87M VIN 400 88.7k 725 43.2k
3.6V to 15V 1.20V 10µF 100µF 1206 953k VIN 450 79k 800 39.2k
3.6V to 15V 1.50V 10µF 100µF 1206 549k VIN 450 79k 1000 29.4k
3.6V to 15V 1.80V 4.7µF 100µF 1206 383k VIN 450 79k 1100 26.7k
3.6V to 15V 2.00V 2.2µF 68µF 1206 324k VIN 450 79k 1200 23.7k
3.6V to 15V 2.20V 2.2µF 47µF 1206 274k VIN 500 69.8k 1300 21.0k
3.6V to 15V 2.50V 2.2µF 47µF 1206 226k VIN 550 61.9k 1450 18.2k
5.5V to 15V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 1400 19.6k
7.5V to 15V 5.00V 2.2µF 10µF 0805 93.1k AUX 650 49.9k 1200 23.7k
9V to 24V 0.82V 10µF 200µF 1206 13M ≥2.8V, <16V 250 150k 250 150k
9V to 24V 1.00V 10µF 147µF 1206 1.87M ≥2.8V, <16V 300 124k 450 79k
9V to 24V 1.20V 2.2µF 100µF 1206 953k ≥2.8V, <16V 450 79k 500 69.8k
9V to 24V 1.50V 2.2µF 100µF 1206 549k ≥2.8V, <16V 450 79k 615 54.9k
9V to 24V 1.80V 2.2µF 100µF 1206 383k ≥2.8V, <16V 450 79k 700 44.2k
9V to 24V 2.00V 2.2µF 68µF 1206 324k ≥2.8V, <16V 450 79k 750 42.2k
9V to 24V 2.20V 2.2µF 47µF 1206 274k ≥2.8V, <16V 500 69.8k 800 39.2k
9V to 24V 2.50V 2.2µF 47µF 1206 226k ≥2.8V, <16V 550 61.9k 890 34.8k
9V to 24V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 1150 25.5k
9V to 24V 5.00V 2.2µF 10µF 0805 93.1k AUX 650 49.9k 1000 29.4k
14.5V to 24V 8.00V 2.2µF 10µF 0805 53.6k AUX 650 49.9k 800 39.2k
18V to 36V 0.82V 10µF 200µF 1206 13M ≥2.8V, <16V 250 150k 250 150k
18V to 36V 1.00V 10µF 147µF 1206 1.87M ≥2.8V, <16V 300 124k 300 124k
18V to 36V 1.20V 2.2µF 100µF 1206 953k ≥2.8V, <16V 350 105k 350 105k
18V to 36V 1.50V 2.2µF 100µF 1206 549k ≥2.8V, <16V 400 88.7k 400 88.7k
18V to 36V 1.80V 2.2µF 100µF 1206 383k ≥2.8V, <16V 450 79k 450 79k
18V to 36V 2.00V 2.2µF 68µF 1206 324k ≥2.8V, <16V 450 79k 500 69.8k
18V to 36V 2.20V 2.2µF 47µF 1206 274k ≥2.8V, <16V 450 79k 550 61.9k
18V to 36V 2.50V 2.2µF 47µF 1206 226k ≥2.8V, <16V 500 69.8k 615 54.9k
18V to 36V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 750 42.2k
18V to 36V 5.00V 2.2µF 10µF 0805 93.1k AUX 800 39.2k 890 34.8k
18V to 36V 8.00V 2.2µF 10µF 0805 53.6k AUX 650 49.9k 800 39.2k
20V to 36V 10.00V 2.2µF 10µF 0805 42.2k AUX 615 54.9k 750 42.2k
4.75V to 32V –3.30V 2.2µF 22µF 1206 154k AUX 550 61.9k 800 39.2k
7V to 31V –5.00V 2.2µF 10µF 0805 93.1k AUX 800 39.2k 1100 26.7k
15V to 28V –8.00V 2.2µF 10µF 0805 53.6k AUX 800 39.2k 1600 15.8k
A bulk input capacitor is required.
LTM8023 L7 LJUW 1 1
LTM8023
11
8023fj
For more information www.linear.com/LTM8023
APPLICATIONS INFORMATION
Ceramic capacitors are also piezoelectric. In Burst Mode
operation, the LTM8023’s switching frequency depends
on the load current, and can excite a ceramic capacitor
at audio frequencies, generating audible noise. Since the
LTM8023 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet to a
casual ear.
If this audible noise is unacceptable, use a high performance
electrolytic capacitor at the output. The input capacitor can
be a parallel combination of a 2.2µF ceramic capacitor and
a low cost electrolytic capacitor.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8023. A
ceramic input capacitor combined with trace or cable
inductance forms a high Q (under damped) tank circuit.
If the LTM8023 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possi-
bly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Frequency Selection
The LTM8023 uses a constant frequency PWM architecture
that can be programmed to switch from 200kHz to 2.4MHz
by using a resistor tied from the RT pin to ground. Table 2
provides a list of RT resistor values and their resultant
frequencies.
Table 2. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz) RT VALUE (kΩ)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
187
124
88.7
69.8
56.2
46.4
39.2
34.6
29.4
23.7
19.6
15.8
13.3
11.5
9.76
8.66
Operating Frequency Trade-Offs
It is recommended that the user apply the optimal RT
value given in Table 1 for the input and output operating
condition. System level or other considerations, however,
may necessitate another operating frequency. While the
LTM8023 is flexible enough to accommodate a wide range
of operating frequencies, a haphazardly chosen one may
result in undesirable operation under certain operating or
fault conditions. A frequency that is too high can reduce
efficiency, generate excessive heat or even damage the
LTM8023 if the output is overloaded or short circuited. A
frequency that is too low can result in a final design that has
too much output ripple or too large of an output capacitor.
The maximum frequency (and attendant RT value) at which
the LTM8023 should be allowed to switch is given in Table 1
in the f(MAX) column, while the recommended frequency
(and RT value) for optimal efficiency over the given input
condition is given in the fOPTIMAL column.
There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Synchronization section for details.
BIAS Pin Considerations
The BIAS pin is used to provide drive power for the internal
power switching stage and operate internal circuitry. For
proper operation, it must be powered by at least 2.8V. If
the output voltage is programmed to be 2.8V or higher,
simply tie BIAS to VOUT. If VOUT is less than 2.8V, BIAS
can be tied to VIN or some other voltage source. In all
cases, ensure that the maximum voltage at the BIAS pin
is both less than 16V and the sum of VIN and BIAS is less
than 56V. If BIAS power is applied from a remote or noisy
voltage source, it may be necessary to apply a decoupling
capacitor locally to the LTM8023.
LTM8023 M
LTM8023
12
8023fj
For more information www.linear.com/LTM8023
APPLICATIONS INFORMATION
Load Sharing
Two or more LTM8023’s may be paralleled to produce
higher currents. To do this, tie the VIN, ADJ, VOUT and
SHARE pins of all the paralleled LTM8023’s together. To
ensure that paralleled modules start up together, the RUN/
SS pins may be tied together, as well. If the RUN/SS pins
are not tied together, make sure that the same valued soft-
start capacitors are used for each module. An example
of two LTM8023 modules configured for load sharing is
given in the Typical Applications section.
For current sharing applications using multiple LTM8023s,
the ADJ pins for all regulators may be combined using
one resistor to ground as determined by:
RADJ =
394.21
N
V
OUT
– 0.79
where N is the number of paralleled modules and RADJ
is in kΩ.
Burst Mode Operation
To enhance efficiency at light loads, the LTM8023 auto-
matically switches to Burst Mode operation which keeps
the output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst Mode
operation, the LTM8023 delivers single cycle bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the output
capacitor. In addition, VIN and BIAS quiescent currents are
reduced to typically 25µA and 50µA respectively during
the sleep time. As the load current decreases towards a no
load condition, the percentage of time that the LTM8023
operates in sleep mode increases and the average input
current is greatly reduced, resulting in higher efficiency.
Burst Mode operation is enabled by tying SYNC to GND.
To disable Burst Mode operation, tie SYNC to a stable
voltage above 0.7V or synchronize to an external clock.
Do not leave the SYNC pin floating
.
Minimum Input Voltage
The LTM8023 is a step-down converter, so a minimum
amount of headroom is required to keep the output in
regulation. In addition, the input voltage required to turn
on is higher than that required to run, and depends upon
whether the RUN/SS is used. As shown in Figure 2, it
takes only about 3.5VIN for the LTM8023 to run a 3.3V
output at light load. If RUN/SS is tied to VIN, a 5.5V input
voltage is required to start. If VIN is allowed to settle in
the operating region first then the RUN/SS pin is enabled,
the minimum input voltage to start at light load is lower,
about 4.2V. A similar curve for 5VOUT operation is also
provided in Figure 2.
Figure 2. The LTM8023 Needs More Voltage to Start Than to Run
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
8023 F02
LOAD CURRENT (mA)
0
INPUT VOLTAGE (V)
4.0
4.5
5.0
2000
3.5
3.0
500 1000 1500
0 2000500 1000 1500
6.0
5.5
TO START
RUN/SS ENABLED
TO RUN
TO START
RUN/SS ENABLED
TO RUN
VOUT = 3.3V
TA = 25°C
f = 650kHz
6.5
7.0
6.0
5.0
5.5
7.5
VOUT = 5V
TA = 25°C
f = 650kHz
LTM8023 "H W st/D w j;— 1-— .I|-o-w»—l HA L7HEJWEGR 1 3
LTM8023
13
8023fj
For more information www.linear.com/LTM8023
Soft-Start
The RUN/SS pin can be used to soft-start the LTM8023,
reducing the maximum input current during start-up.
The
RUN/SS pin is driven through an external RC filter
to create a voltage ramp at this pin. Figure 3 shows the
start-up and shutdown waveforms with the soft-start
circuit. By choosing an appropriate RC time constant,
the peak start-up current can be reduced to the current
that is required to regulate the output, with no overshoot.
Choose the value of the resistor so that it can supply at
least 20µA when the RUN/SS pin reaches 2.5V.
APPLICATIONS INFORMATION
Figure 4. The Input Diode Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also Protects
the Circuit from a Reversed Input. The LTM8023 Runs Only
When the Input is Present.
Shorted Input Protection
Care needs to be taken in systems where the output will be
held high when the input to the LTM8023 is absent. This
may occur in battery charging applications or in battery
backup systems where a battery or some other supply is
diode OR-ed with the LTM8023’s output. If the VIN pin is
allowed to float and the RUN/SS pin is held high (either
by a logic signal or because it is tied to VIN), then the
LTM8023’s internal circuitry will pull its quiescent cur-
rent through its internal power switch. This is fine if your
system can tolerate a few milliamps in this state. If you
ground the RUN/SS pin, the internal power switch cur-
rent will drop to essentially zero. However, if the VIN pin
is grounded while the output is held high, then parasitic
diodes inside the LTM8023 can pull large currents from
the output through the VIN pin. Figure 4 shows a circuit
that will run only when the input voltage is present and
that protects against a shorted or reversed input.
VOUT
VIN
RUN/SS
BIAS
RTADJ
LTM8023
8023 F04
VOUT
GND
VIN
AUX
SYNC
Figure 3. To Soft-Start the LTM8023, Add a
Resistor and Capacitor to the RUN/SS Pin
8023 F03
IL
1A/DIV
VRUN/SS
2V/DIV
VOUT
2V/DIV
RUN/SS
GND
0.22µF
RUN
15k
2ms/DIV
Synchronization
The internal oscillator of the LTM8023 can be synchronized
by applying an external 250kHz to 2MHz clock to the SYNC
pin.
Do not leave this pin floating
. The resistor tied from the
RT pin to ground should be chosen such that the LTM8023
oscillates 20% lower than the intended synchronization
frequency (see the Frequency Selection section).
The LTM8023 will not enter Burst Mode operation while
synchronized to an external clock, but will instead skip
pulses to maintain regulation.
lIhA8023 DD . . llllllll -llllllll llllllll Ill-l? lllll... lllll.ll II... II . . I:II:I 14 L7LJCUEN2
LTM8023
14
8023fj
For more information www.linear.com/LTM8023
Figure 5. Layout Showing Suggested External Components, GND
Plane and Thermal Vias
VOUT
CIN VIN
RADJ
RT
COUT
GND
BIAS
AUX
SHARE
RUN/SS
PGOOD
SYNC
8023 F05
APPLICATIONS INFORMATION
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8023. The LTM8023 is neverthe-
less a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 5
for a suggested layout.
4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent or underneath
the LTM8023.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8023.
6. Use vias to connect the GND copper area to the boards
internal ground plane. Liberally distribute these GND vias
to provide both a good ground connection and thermal
path to the internal planes of the printed circuit board.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8023. However, these capacitors
can cause problems if the LTM8023 is plugged into a live
supply (see Linear Technology Application Note 88 for a
complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt-
age at the VIN pin of the LTM8023 can ring to twice the
nominal input voltage, possibly exceeding the LTM8023’s
rating and damaging the part. If the input supply is poorly
controlled or the user will be plugging the LTM8023 into
an energized supply, the input network should be designed
to prevent this overshoot. Figure 6 shows the waveforms
that result when an LTM8023 circuit is connected to a 24V
supply through six feet of 24-gauge twisted pair. The first
plot is the response with a 2.2µF ceramic capacitor at the
input. The input voltage rings as high as 35V and the input
current peaks at 20A. One method of damping the tank
circuit is to add another capacitor with a series resistor to
the circuit. In Figure 6c an aluminum electrolytic capacitor
has been added. This capacitor’s high equivalent series
resistance damps the circuit and eliminates the voltage
overshoot. The extra capacitor improves low frequency
Ensure that the grounding and heatsinking are acceptable.
A few rules to keep in mind are:
1. Place the RADJ and RT resistors as close as possible to
their respective pins.
2. Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8023.
3. Place the COUT capacitor as close as possible to the
VOUT and GND connection of the LTM8023.
LTM8023 L7HEJWEGR 1 5
LTM8023
15
8023fj
For more information www.linear.com/LTM8023
ripple filtering and can slightly improve the efficiency of the
circuit, though it is likely to be the largest component in the
circuit. An alternative solution is shown in Figure 6b. A 0.7Ω
resistor is added in series with the input to eliminate the
voltage overshoot (it also reduces the peak input current).
A 0.1µF capacitor improves high frequency filtering. This
solution is smaller and less expensive than the electrolytic
capacitor. For high input voltages its impact on efficiency
is minor, reducing efficiency less than one-half percent
for a 5V output at full load operating from 24V.
Figure 6. A Well Chosen Input Network Prevents Input Voltage Overshoot and Ensures Reliable
Operation When the LTM8023 is Connected to a Live Supply
APPLICATIONS INFORMATION
+
LTM8023
4.7µF
VIN
20V/DIV
IIN
10A/DIV
20µs/DIV
VIN
CLOSING SWITCH
SIMULATES HOT PLUG
IIN
(6a)
(6b)
LOW
IMPEDANCE
ENERGIZED
24V SUPPLY
STRAY
INDUCTANCE
DUE TO 6 FEET
(2 METERS) OF
TWISTED PAIR
+
LTM8023
4.7µF0.1µF
0.7Ω VIN
20V/DIV
IIN
10A/DIV
20µs/DIV
DANGER
RINGING VIN MAY EXCEED
ABSOLUTE MAXIMUM RATING
(6c)
+
LTM8023
4.7µF
22µF
35V
AI.EI.
8023 F06
VIN
20V/DIV
IIN
10A/DIV
20µs/DIV
+
LTM8023
LTM8023
16
8023fj
For more information www.linear.com/LTM8023
Thermal Considerations
The LTM8023 output current may need to be derated if
it is required to operate in a high ambient temperature or
deliver a large amount of continuous power. The amount
of current derating is dependent upon the input voltage,
output power and ambient temperature. The temperature
rise curves given in the Typical Performance Character-
istics section can be used as a guide. These curves were
generated by an LTM8023 mounted to a 33cm2 4-layer FR4
printed circuit board. Boards of other sizes and layer count
can exhibit different thermal behavior, so it is incumbent
upon the user to verify proper operation over the intended
systems line, load and environmental operating conditions.
The thermal resistance numbers listed in the Pin Con-
figuration are based on modeling the µModule package
mounted on a test board specified per JESD51-9 “Test
Boards for Area Array Surface Mount Package Thermal
Measurements.” The thermal coefficients provided in this
page are based on JESD 51-12 Guidelines for Reporting
and Using Electronic Package Thermal Information.”
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration typically gives four
thermal coefficients:
θJA – Thermal resistance from junction to ambient.
θJCbottom – Thermal resistance from junction to the
bottom of the product case.
θJCtop – Thermal resistance from junction to top of
the product case.
θJB – Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confu-
sion and inconsistency. These definitions are given in
JESD 51-12, and are quoted or paraphrased in the following:
θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
still air” although natural convection causes the air to
move. This value is determined with the part mounted to
a JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
θJCbottom is the junction-to-board thermal resistance
with all of the component power dissipation flowing
through the bottom of the package. In the typical
µModule regulator, the bulk of the heat flows out the
bottom of the package, but there is always heat flow out
into the ambient environment. As a result, this thermal
resistance value may be useful for comparing packages
but the test conditions don’t generally match the user’s
application.
θJCtop is determined with nearly all of the component
power dissipation flowing through the top of the pack-
age. As the electrical connections of the typical µModule
regulator are on the bottom of the package, it is rare
for an application to operate such that most of the heat
flows from the junction to the top of the part. As in the
case of θJCbottom, this value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule regulator and into the board, and is really the
sum of the θJCbottom and the thermal resistance of the
bottom of the part through the solder joints and through
a portion of the board. The board temperature is mea-
sured a specified distance from the package, using a
two sided, two layer board. This board is described in
JESD 51-9.
The most appropriate way to use the coefficients is when
running a detailed thermal analysis, such as FEA, which
considers all of the thermal resistances simultaneously.
None of them can be individually used to accurately pre-
dict the thermal performance of the product, so it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature versus load graphs
given in the LTM8023 data sheet.
APPLICATIONS INFORMATION
LTM8023 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, L7HEJWEGR 1 7
LTM8023
17
8023fj
For more information www.linear.com/LTM8023
APPLICATIONS INFORMATION
Figure 7
A graphical representation of these thermal resistances
is given in Figure 7.
The blue resistances are contained within the µModule
regulator, and the green are outside.
The die temperature of the LTM8023 must be lower than
the maximum rating of 125°C, so care should be taken
in the layout of the circuit to ensure good heat sinking
of the LTM8023. The bulk of the heat flow out of the
LTM8023 is through the bottom of the module and the LGA
pads into the printed circuit board. Consequently a poor
printed circuit board design can cause excessive heating,
resulting in impaired performance or reliability. Please
refer to the PCB Layout section for printed circuit board
design suggestions.
Finally, be aware that at high ambient temperatures the
internal Schottky diode will have significant leakage current
increasing the quiescent current of the LTM8023.
8023 F07
µMODULE REGULATOR
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION At
CASE (BOTTOM)-TO-BOARD
RESISTANCE
W— %—?%_$ #2 ¢
LTM8023
18
8023fj
For more information www.linear.com/LTM8023
TYPICAL APPLICATIONS
VIN
RUN/SS
PGOOD
LTM8023
8023 TA05
VIN*
7.5V TO 36VDC
2.2µF
93.1k49.9k
RT
ADJ
SYNCGND
SHARE
VOUT
BIAS
10µF
V
OUT
5V
2A
AUX
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
226k61.9k
VOUT
VIN
RUN/SS
PGOODBIAS3.3V
LTM8023
47µF
8023 TA04
V
OUT
2.5V
2A
VIN*
4.5V TO 36VDC
2.2µF
RT
ADJ
SYNCGND
SHARE AUX
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
2.5V Step-Down Converter 5V Step-Down Converter
VOUT
VIN
BIAS
RUN/SS
PGOOD
RT
383k79k
100µF
8023 TA03
V
OUT
1.8V
2A
VIN*
3.6V TO 15V
4.7µF
LTM8023
ADJ
SYNCGND
SHARE
AUX
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
VOUT
VIN
BIAS
SHARE
RUN/SS
PGOOD
AUX
ADJ
LTM8023
200µF
8023 TA02
V
OUT
0.82V
2A
VIN*
3.6V TO 15V
10µF
RT
13M105k
SYNCGND
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
0.82V Step-Down Converter 1.8V Step-Down Converter
VOUT
VIN
RUN/SS
RT
ADJ
PGOOD
LTM8023
8023 TA07
VOUT
3.3V
2A
SYNC
VIN*
5.5V TO 36V
GND
2.2µF
154k49.9k
22µF
BIAS
AUX
SHARE
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
LTM8023 L7HEJWEGR 1 9
LTM8023
19
8023fj
For more information www.linear.com/LTM8023
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
0
8023 TA06b
500
2500
2000
1500
1000
0 10 20 30 40
TYPICAL APPLICATIONS
VOUT
VIN
RUN/SS
RT
ADJ
LTM8023
8023 TA06
–5V
SYNC
GND
PGOODSHARE
BIAS
AUX
2.2µF
93.1k39.2k
10µF
VIN*
7V TO 31V
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
–5V Positive to Negative Converter –5V Positive to Negative Converter
Load Current vs Input Voltage
VOUT
VIN
RUN/SS
RT
ADJ
LTM8023
GNDSYNC
PGOODSHARE
BIAS
AUX
2.2µF
76.8k49.9k
VIN*
6.5V TO 36V
V
OUT
3.3V
4A
VOUT
VIN
RUN/SS
RT
ADJ
LTM8023
8023 TA08
GNDSYNC
PGOODSHARE
BIAS
AUX
2.2µF 0.22µF
49.9k
47µF
2.2k
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
Two LTM8023’s in Parallel, 3.3V at 4A
LTM8023 lllllln’ lllllll lllllll lllllll lllllll I IQi-L I».i l;\ :a: I ”i: ‘ l 4 5555 L7LJCUEN2
LTM8023
20
8023fj
For more information www.linear.com/LTM8023
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
PACKAGE DESCRIPTION
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 50
4
3
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A
MARKED FEATURE
SYMBOL
aaa
bbb
TOLERANCE
0.15
0.10
9.00
BSC
PACKAGE TOP VIEW
LGA 50 0113 REV C
11.25
BSC
PAD 1
CORNER
PADS
SEE NOTES
XY
aaa Z
aaa Z
2.72 – 2.92
DETAIL A
PACKAGE SIDE VIEW
DETAIL A
SUBSTRATE
MOLD
CAP
0.27 – 0.37
2.45 – 2.55
bbb Z
Z
1.27
BSC
0.605 – 0.665
0.605 – 0.665
8.89
BSC
7.62
BSC
C(0.30)
PAD 1
H B AD C
6
7
5
1
2
3
4
EF
PACKAGE BOTTOM VIEW
PACKAGE IN TRAY LOADING ORIENTATION
G
4.445
4.445
3.175
3.175
1.905
1.905
0.000
0.635
0.635
3.810
3.810
0.9525
0.635
0.3175
2.540
2.540
1.270
1.270
0.000
0.3175
0.3175
SUGGESTED PCB LAYOUT
TOP VIEW
LTMXXXXXX
µModule
TRAY PIN 1
BEVEL
LGA Package
50-Lead (11.25mm × 9.00mm × 2.82mm)
(Reference LTC DWG # 05-08-1804 Rev C)
7
3
4
SEE NOTES
LTM8023 0cccr7~~~ 21 L7 LJUW
LTM8023
21
8023fj
For more information www.linear.com/LTM8023
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
PACKAGE DESCRIPTION
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
YX
aaa Z
aaa Z
DETAIL A
PACKAGE BOTTOM VIEW
3
SEE NOTES
H
G
F
E
D
C
B
A
1234567
PIN 1
BGA 50 1212 REV A
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu
OR Sn Pb EUTECTIC
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
DETAIL A
Øb (50 PLACES)
DETAIL B
SUBSTRATE
A
A1
b1
ccc Z
DETAIL B
PACKAGE SIDE VIEW
MOLD
CAP
Z
MX YZddd
MZeee
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
3.22
0.50
2.72
0.71
0.60
0.27
2.45
NOM
3.42
0.60
2.82
0.78
0.63
11.25
9.0
1.27
8.89
7.62
0.32
2.50
MAX
3.62
0.70
2.92
0.85
0.66
0.37
2.55
0.15
0.10
0.20
0.30
0.15
NOTES
DIMENSIONS
TOTAL NUMBER OF BALLS: 50
A2
D
E
e
b
F
G
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
0.635
1.905
0.635
3.175
1.905
4.445
3.175
4.445
3.810
2.540
1.270
3.810
2.540
1.270
0.3175
0.3175
0.000
4.13
4.76
LTMXXXXXX
µModule
// bbb Z
Z
H2
H1
0.630 ±0.025 Ø 50x
BGA Package
50-Lead (11.25mm × 9.00mm × 3.42mm)
(Reference LTC DWG # 05-08-1883 Rev A)
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
7
SEE NOTES
LTM8023 22 L7ELUEN2
LTM8023
22
8023fj
For more information www.linear.com/LTM8023
PACKAGE DESCRIPTION
Table 3. Pin Assignment (Sorted by Pin Number)
PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION
A1 VOUT D5 GND
A2 VOUT D6 GND
A3 VOUT D7 GND
A4 VOUT E1 GND
A5 GND E2 GND
A6 GND E3 GND
A7 GND E4 GND
B1 VOUT E5 GND
B2 VOUT E6 GND
B3 VOUT E7 GND
B4 VOUT F5 AUX
B5 GND F6 GND
B6 GND F7 SHARE
B7 GND G1 VIN
C1 VOUT G2 VIN
C2 VOUT G3 VIN
C3 VOUT G5 BIAS
C4 VOUT G6 SYNC
C5 GND G7 RT
C6 GND H1 VIN
C7 GND H2 VIN
D1 GND H3 VIN
D2 GND H5 RUN/SS
D3 GND H6 PGOOD
D4 GND H7 ADJ
LTM8023 L7HEJWEGR 23
LTM8023
23
8023fj
For more information www.linear.com/LTM8023
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
F 8/10 Added Note 5 3
G 8/11 Added BGA package. Changes reflected throughout the data sheet. 1 to 24
H 8/13 Changed output capacitor from 2.2µF to 22µF 1
I 2/14 Added SnPb BGA package option 1, 2
J 8/15 Updated thermal impedance values 2
(Revision history begins at Rev F)
LTM8023 24 L7HQEQB
LTM8023
24
8023fj
For more information www.linear.com/LTM8023
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 2007
LT 0815 REV J • PRINTED IN USA
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTM8023
PART NUMBER DESCRIPTION COMMENTS
LTM8022 36V, 1A Step-Down µModule Regulator 0.8V ≤ VOUT ≤ 10V, Synchronizable, 9mm × 11.25mm × 2.8mm LGA
LTM8025 36V, 3A Step-Down µModule Regulator 0.8V ≤ VOUT ≤ 24V, Synchronizable, 9mm × 15mm × 4.3mm LGA
LTM8027 60V, 4A Step-Down µModule Regulator 2.5V ≤ VOUT ≤ 24V, Synchronizable, 15mm × 15mm × 4.3mm LGA
LTM4612 EN55022B Certified 36V, 5A Step-Down
µModule Regulator
3.3V ≤ VOUT ≤ 15V, Synchronizable, 15mm × 15mm × 2.8mm LGA
LTM4613 EN55022B Certified 36V, 8A Step-Down
µModule Regulator
3.3V ≤ VOUT ≤ 15V, Synchronizable, 15mm × 15mm × 4.3mm LGA
LTM8061 32V, 2A Li-Ion/Li-Polymer µModule Battery
Charger
C/10 or Timer Termination, Auto-Recharge, Programmable Charge Current,
9mm × 15mm × 4.3mm LGA
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