LTM4630A Datasheet by Analog Devices Inc.

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LTM4630A
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For more information www.linear.com/LTM4630A
TYPICAL APPLICATION
DESCRIPTION
Dual 18A or Single 36A
DC/DC µModule Regulator
The LT M
®
4630A is a dual 18A or single 36A output switch-
ing mode step-down DC/DC µModule
®
(micromodule)
regulator with wider VOUT range and higher efficiency
than LTM4630. Included in the package are the switch-
ing controllers, power FETs, inductors and all supporting
components. Operating from an input voltage range of
4.5V to 18V, the LTM4630A supports two outputs each
with an output voltage range of 0.6V to 8V, each set by a
single external resistor. Its high efficiency design delivers
up to 18A continuous current for each output. Only a few
input and output capacitors are needed. The LTM4630A
is pin compatible with the LTM4620 and LTM4620A (dual
13A, single 26A) and the LTM4630 (dual 18A, single 36A).
The device supports frequency synchronization, multi-
phase operation, Burst Mode operation and output voltage
tracking for supply rail sequencing and has an onboard
temperature diode for device temperature monitoring. High
switching frequency and a current mode architecture enable
a very fast transient response to line and load changes
without sacrificing stability.
Fault protection features include overvoltage and
overcurrent protection. The LTM4630A is offered in 16mm
× 16mm × 4.41mm LGA and 16mm × 16mm × 5.01mm
BGA packages.
FEATURES
APPLICATIONS
n Dual 18A or Single 36A Output
n Input Voltage Range: 4.5V to 18V (after date code
1720*)
n Output Voltage Range: 0.6V to 8V (after date code
1720*)
n ±1.5% Maximum Total DC Output Error Over Line,
Load and Temperature
n Higher Light Load Efficiency and Wider VOUT Range
Than LTM4630
n Differential Remote Sense Amplifier
n Current Mode Control/Fast Transient Response
n Multiphase Parallel Current Sharing Up to 144A
n Internal Temperature Monitor
n Pin Compatible with the LTM4620A (Dual 13A,
Single 26A) and LTM4630 (Dual 18A, Single 36A)
n Adjustable Switching Frequency or Synchronization
n Overcurrent Foldback Protection
n Selectable Burst Mode
®
Operation, Pulse Skipping
Mode Operation
n Soft-Start/Voltage Tracking
n Output Overvoltage Protection
n
16mm × 16mm × 4.41mm LGA and
16mm × 16mm ×
5.01mm BGA
Packages
n Telecom and Networking Equipment
n Storage and ATCA Cards
n Industrial Equipment
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066
and 6580258. Other patents pending.
*Maximum VIN=15V and VOUT=5.3V with date code before 1720.
36A, 1.2V Output DC/DC µModule Regulator 1.2VOUT and 3.3VOUT
Efficiency vs IOUT
4630A TA01a
LTM4630A
VIN
TEMP
RUN1
RUN2
TRACK1
TRACK2
fSET
470µF
6.3V
60.4k
100µF
6.3V
PHASMD
VOUT1 VOUT
VOUTS1
VFB1
VFB2
COMP1
COMP2
VOUT2
PGOOD2
MODE_PLLIN
PINS UNUSED IN
THIS APPLICATION:
CLKOUT
EXTVCC
SW1
SW2
VOUTS2
INTVCC
INTVCC
PGOOD1
PGOOD
10k
SGND GND
DIFFP
DIFFN
DIFFOUT
470µF
6.3V
100µF
6.3V
75k
120k
0.1µF
22µF
25V
×4
+
+
VIN
4.5V TO 15V
4.7µF
LOAD CURRENT (A)
0
65
EFFICIENCY (%)
90
85
80
75
70
100
95
10 12 14 16 182 4 6
4630A TA01b
8
5 VIN, 3.3VOUT, 500kHz
5 VIN, 1.2VOUT, 300kHz
12 VIN, 3.3VOUT, 600kHz
12 VIN, 1.2VOUT, 300kHz
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN (Note 8) ................................................ 0.3V to 20V
VSW1, VSW2 ....................................................1V to 20V
PGOOD1, PGOOD2, RUN1, RUN2,
INTVCC, EXTVCC .......................................... 0.3V to 6V
MODE_PLLIN, fSET, TRACK1, TRACK2,
DIFFOUT, PHASMD ............................... 0.3V to INTVCC
VOUT1, VOUT2, VOUTS1, VOUTS2 (Note 6) ...... 0.3V to 10V
(Note 1)
LGA PACKAGE
144-LEAD (16mm × 16mm × 4.41mm)
TOP VIEW
TEMP
CLKOUT
SW1
PHASMD
EXTVCC
1 2 3 4 5 6 7 8 109 11 12
L
K
J
H
G
F
E
D
C
B
M
A
SW2
PGOOD1
PGOOD2
RUN2
TRACK2
INTVCC
VOUTS2
DIFFP
DIFFOUT
DIFFN
RUN1
TRACK1
MODE_PLLIN
VFB1
VOUTS1
fSET
SGND
COMP1 COMP2
SGND
VFB2
VIN
VOUT2
GND
GND
VOUT1
SGND
GND
TJMAX = 125°C, ΘJA = 7°C/W, ΘJCbottom = 1.5°C/W, ΘJCtop = 3.7°C/W, ΘJB + ΘJBA 7°C/W
Θ VALUES DEFINED PER JESD51-12
WEIGHT = 3.2g
BGA PACKAGE
144-LEAD (16mm × 16mm × 5.01mm)
TOP VIEW
TEMP
CLKOUT
SW1
PHASMD
EXTVCC
1 2 3 4 5 6 7 8 109 11 12
L
K
J
H
G
F
E
D
C
B
M
A
SW2
PGOOD1
PGOOD2
RUN2
TRACK2
INTVCC
VOUTS2
DIFFP
DIFFOUT
DIFFN
RUN1
TRACK1
MODE_PLLIN
VFB1
VOUTS1
fSET
SGND
COMP1 COMP2
SGND
VFB2
VOUT2
GND
GND
SGND
GND
TJMAX = 125°C, ΘJA = 7°C/W, ΘJCbottom = 1.5°C/W, ΘJCtop = 3.7°C/W, ΘJB + ΘJBA 7°C/W
Θ VALUES DEFINED PER JESD51-12
WEIGHT = 3.39g
PART NUMBER PAD OR BALL FINISH
PART MARKING* PACKAGE
TYPE
MSL
RATING TEMPERATURE RANGE (NOTE 2)DEVICE FINISH CODE
LTM4630AEV#PBF Au (RoHS) LTM4630AV e4 LGA 3 –40°C to 125°C
LTM4630AIV#PBF –40°C to 125°C
LTM4630AEY#PBF SAC305 (RoHS) LTM4630AY e1 BGA 3 –40°C to 125°C
LTM4630AIY#PBF –40°C to 125°C
DIFFP, DIFFN ......................................... 0.3V to INTVCC
COMP1, COMP2, VFB1, VFB2 (Note 6) ........ 0.3V to 2.7V
INTVCC Peak Output Current ................................100mA
Internal Operating Temperature Range
(Note 2) ............................................. 40°C to 125°C
Storage Temperature Range .................. 55°C to 125°C
Peak Package Body Temperature .......................... 245°C
Device temperature grade is indicated by a label on the shipping container.
Pad or ball finish code is per IPC/JEDEC J-STD-609.
Terminal Finish Part Marking: www.linear.com/leadfree
This product is not recommended for second side reflow. For more
information, go to www.linear.com/BGA-assy
Recommended BGA PCB Assembly and Manufacturing Procedures:
www.linear.com/BGA-assy
BGA Package and Tray Drawings: www.linear.com/packaging
This product is moisture sensitive. For more information, go to:
www.linear.com/BGA-assy
ORDER INFORMATION
http://www.linear.com/product/LTC4630A#orderinfo
LTM463OA
LTM4630A
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ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 34.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input DC Voltage l4.5 18 V
VOUT Output Voltage l0.6 8 V
VOUT1(DC),
VOUT2(DC)
Output Voltage, Total Variation with
Line and Load
CIN = 22µF × 3, COUT = 100µF × 1 Ceramic,
470µF POSCAP
VIN = 12V, VOUT = 1.5V, IOUT = 0A to 18A
(Note 8)
l1.477 1.5 1.523 V
Input Specifications
VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V
VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 150 mV
IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A, CIN = 22µF ×3, CSS = 0.01µF,
COUT = 100µF ×3, VOUT1 = 1.5V, VOUT2 = 1.5V,
VIN = 12V
1 A
IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Burst Mode Operation
VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode
VIN = 12V, VOUT= 1.5V, Switching Continuous
Shutdown, RUN = 0, VIN = 12V
3
15
65
35
mA
mA
mA
µA
IS(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 18A
VIN = 12V, VOUT = 1.5V, IOUT = 18A
6.5
2.6
A
A
Output Specifications
IOUT1(DC), IOUT2(DC) Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 7) 0 18 A
ΔVOUT1(LINE)/VOUT1
ΔVOUT2(LINE)/VOUT2
Line Regulation Accuracy VOUT = 1.5V, VIN from 4.5V to 18V
IOUT = 0A for Each Output,
l0.01 0.025 %/V
ΔVOUT1/VOUT1
ΔVOUT2/VOUT2
Load Regulation Accuracy For Each Output, VOUT = 1.5V, 0A to 18A
VIN = 12V (Note 7)
l0.5 0.75 %
VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF ×3/
X7R/Ceramic, 470µF POSCAP, VIN = 12V,
VOUT = 1.5V, Frequency = 450kHz
15 mVP-P
fS (Each Channel) Output Ripple Voltage Frequency VIN = 12V, VOUT = 1.5V, fSET = 1.25V (Note 4) 500 kHz
fSYNC
(Each Channel)
SYNC Capture Range 400 780 kHz
ΔVOUTSTART
(Each Channel)
Turn-On Overshoot COUT = 100µF/X5R/Ceramic, 470µF POSCAP,
VOUT = 1.5V, IOUT = 0A VIN = 12V
10 mV
tSTART
(Each Channel)
Turn-On Time COUT = 100µF/X5R/Ceramic, 470µF POSCAP,
No Load, TRACK/SS with 0.01µF to GND,
VIN = 12V
5 ms
ΔVOUT(LS)
(Each Channel)
Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load
COUT = 22µF ×3/X5R/Ceramic, 470µF POSCAP
VIN = 12V, VOUT = 1.5V
30 mV
tSETTLE
(Each Channel)
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load,
VIN = 12V, COUT = 100µF, 470µF POSCAP
20 µs
IOUT(PK)
(Each Channel)
Output Current Limit VIN = 12V, VOUT = 1.5V 30 A
Control Section
VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.5V l0.592 0.600 0.606 V
IFB (Note 6) –5 –20 nA
VOVL Feedback Overvoltage Lockout l0.64 0.66 0.68 V
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ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 34.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TRACK1 (I),
TRACK2 (I)
Track Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V 1 1.25 1.5 µA
UVLO Undervoltage Lockout (Falling) 3.3 V
UVLO Hysteresis 0.6 V
tON(MIN) Minimum On-Time (Note 6) 90 ns
RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2
and VFB1, VFB2 Pins for Each Output
60.05 60.4 60.75 kΩ
VPGOOD1, VPGOOD2
Low
PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±5 µA
VPGOOD PGOOD Trip Level VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
–10
10
%
%
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 6V < VIN < 18V 4.8 5 5.2 V
VINTVCC
Load Regulation
INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.5 4.7 V
VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 50 100 mV
VEXTVCC(HYST) EXTVCC Hysteresis 220 mV
Oscillator and Phase-Locked Loop
Frequency Nominal Nominal Frequency fSET = 1.2V 450 500 550 kHz
Frequency Low Lowest Frequency fSET = 0V (Note 5) 210 250 290 kHz
Frequency High Highest Frequency fSET > 2.4V, Up to INTVCC 700 780 860 kHz
fSET Frequency Set Current 9 10 11 µA
RMODE_PLLIN MODE_PLLIN Input Resistance 250
CLKOUT Phase (Relative to VOUT1) PHASMD = GND
PHASMD = Float
PHASMD = INTVCC
60
90
120
Deg
Deg
Deg
CLK High
CLK Low
Clock High Output Voltage
Clock Low Output Voltage
2
0.2
V
V
Differential Amplifier
AV Differential
Amplifier
Gain 1 V/V
RIN Input Resistance Measured at DIFFP Input 80 kΩ
VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA 3 mV
PSRR Differential
Amplifier
Power Supply Rejection Ratio 5V < VIN < 18V 90 dB
ICL Maximum Output Current 3 mA
VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300µA INTVCC – 1.4 V
GBW Gain Bandwidth Product 3 MHz
VTEMP Diode Connected PNP I = 100µA 0.6 V
TC Temperature Coefficient l–2.2 mV/C
LTM4630A x wwmm MW «WW mm .—._a
LTM4630A
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ELECTRICAL CHARACTERISTICS
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode and Pulse-Skip Mode
Efficiency VIN=12V, VOUT = 1.2V,
fS = 300kHz
1V Dual Phase Single Output
Load Transient Response
1.2V Dual Phase Single Output
Load Transient Response
Efficiency vs Output Current,
VIN = 5V
Efficiency vs Output Current,
VIN = 12V
LOAD CURRENT (A)
0
70
EFFICIENCY (%)
98
96
94
92
88
86
84
82
80
78
76
74
72
90
100
10 12 14 16 182 4 6
4630A G01
8
1.8VOUT, 300kHz
2.5VOUT, 400kHz
1.5VOUT, 300kHz
3.3VOUT, 500kHz
1.2VOUT, 300kHz
1.0VOUT, 300kHz
0.9VOUT, 300kHz
LOAD CURRENT (A)
0
70
EFFICIENCY (%)
96
94
92
90
88
86
84
82
80
78
76
74
72
100
98
10 12 14 16 182 4 6
4630A G02
8
1.8VOUT, 400kHz
2.5VOUT, 500kHz
1.5VOUT, 400kHz
3.3VOUT, 600kHz
1.2VOUT, 300kHz
1.0VOUT, 300kHz
5.0VOUT, 700kHz
8.0VOUT, 770kHz
0.9VOUT, 300kHz
LOAD CURRENT (A)
0.01
0
EFFICIENCY (%)
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
95
1 100.1
4630A G04
CCM
PULSE-SKIP MODE
Burst Mode OPERATION
50µs/DIV
VOUT(AC)
20mV/DIV
LOAD STEP
10A/DIV
4630A G05
12VIN, 1VOUT, 300kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
50µs/DIV
VOUT(AC)
20mV/DIV
LOAD STEP
10A/DIV
4630A G06
12VIN, 1.2VOUT, 300kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4630A is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4630AE is guaranteed to meet specifications from
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4630AI is guaranteed over the full –40°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The switching frequency is programmable from 300kHz to 750kHz.
Note 5: LTM4630A device is designed to operate from 300kHz to 750kHz
Note 6: These parameters are tested at wafer sort.
Note 7: See Table 1 for Peak Current and Thermal Design Power (TDP)
current for different VIN and VOUT. See output current derating curve for
different ambient temperature.
Note 8: Total DC output voltage error includes all errors over temperature:
Line and load regulation as well as the tolerance of the integrated top
feedback resistor.
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TYPICAL PERFORMANCE CHARACTERISTICS
Single Phase Short Circuit
Protection with 18A
Single Phase Start-up with 18A
Single Phase Short Circuit
Protection with No load
3.3V Dual Phase Single Output
Load Transient Response Single Phase Start-Up with No load
50µs/DIV
VOUT(AC)
20mV/Div
LOAD STEP
10A/DIV
4630A G07
12VIN, 1.5VOUT, 400kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
50µs/DIV
VOUT(AC)
20mV/Div
LOAD STEP
10A/DIV
4630A G08
12VIN, 1.8VOUT, 400kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
1.5V Dual Phase Single Output
Load Transient Response
1.8V Dual Phase Single Output
Load Transient Response
2.5V Dual Phase Single Output
Load Transient Response
50µs/DIV
VOUT(AC)
20mV/Div
LOAD STEP
10A/DIV
4630A G09
12VIN, 2.5VOUT, 500kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
50µs/DIV
VOUT(AC)
20mV/Div
LOAD STEP
10A/DIV
4630A G10
12VIN, 3.3VOUT, 600kHz, DUAL PHASE SINGLE
OUTPUT SETUP 9A LOAD STEP UP AND STEP
DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF
POSCAP + 4 • 100µF CERAMIC CAPS
20ms/DIV
VSW
10V/Div
VOUT
0.5V/Div
IIN
0.2A/Div
4630A G11
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC, CSS = 0.1µF
20ms/DIV
VSW
10V/Div
VOUT
0.5V/Div
IIN
1A/Div
4630A G12
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC, CSS = 0.1µF
50µs/DIV
VSW
10V/Div
VOUT
0.5V/Div
IIN
1A/Div
4630A G13
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC
50µs/DIV
VSW
10V/Div
VOUT
0.5V/Div
IIN
1A/Div
4630A G14
12VIN, 1.2VOUT, 300kHz
COUT = 1 • 470µF 4V POSCAP + 1 • 100µF
6.3V CERAMIC
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PIN FUNCTIONS
VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply
output load between these pins and GND pins. Recom-
mend placing output decoupling capacitance directly
between these pins and GND pins. Review Table 6 for
output capacitance requirement. See Table 1 for output
current guideline.
GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12,
F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1,
J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power
Ground Pins for Both Input and Output Returns.
VOUT2 (A8-A12, B8-B12, C9-C12): Power Output
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling ca-
pacitance directly between these pins and GND pins.
Review Table 6 for output capacitance requirement.
See Table 1 for output current guideline.
VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top
of the internal top feedback resistor for each output. The
pin can be directly connected to its specific output, or
connected to DIFFOUT when the remote sense amplifier
is used. In paralleling modules, one of the VOUTS pins is
connected to the DIFFOUT pin in remote sensing or directly
to VOUT with no remote sensing. It is very important to
connect these pins to either the DIFFOUT or VOUT since
this is the feedback path, and cannot be left open. See the
Applications Information section.
fSET (C6): Frequency Set Pin. A 10µA current is sourced
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND in the ap-
plication. See layout guidelines in Figure 12.
VFB1, VFB2 (D5, D7): The Negative Input of the Error
Amplifier for each channel. Internally, this pin is con-
nected to VOUTS1 or VOUTS2 with a 60.4kΩ precision
resistor. Different output voltages can be programmed
with an additional resistor between VFB and GND pins. In
PolyPhase
®
operation, tying the VFB pins together allows
for parallel operation. See the Applications Information
section for details.
TRACK1, TRACK2 (E5, D8): Output Voltage Tracking Pin
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
current source. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave out-
put’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
COMP1, COMP2 (E6, E7): Current control threshold and
error amplifier compensation point for each channel. The
current comparator threshold increases with this control
voltage. Tie the COMP pins together for parallel operation.
The device is internal compensated.
DIFFP (E8): Positive input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output voltage. Diffamp can be used for 3.3V outputs.
See the Applications Information section.
DIFFN (E9): Negative input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output GND. Diffamp can be used for 3.3V outputs. See
the Applications Information section.
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM463OA
LTM4630A
8
4630afb
For more information www.linear.com/LTM4630A
PIN FUNCTIONS
MODE_PLLIN (F4): Force Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
force continuous mode of operation. Connect to INTVCC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force both channels into continuous mode of
operation and synchronized to the external clock applied
to this pin.
RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above
1.25V will turn on each channel in the module. A voltage
below 1.25V on the RUN pin will turn off the related chan-
nel. Each RUN pin has a 1µA pull-up current, once the
RUN pin reaches 1.2V an additional 4.5µA pull-up current
is added to this pin.
DIFFOUT (F8): Internal Remote Sense Amplifier Output.
Connect this pin to VOUTS1 or VOUTS2 depending on which
output is using remote sense. In parallel operation con-
nect one of the VOUTS pin to DIFFOUT for remote sensing.
Diffamp can be used for ≤ 3.3V outputs.
SW1, SW2 (G2, G11): Switching node of each channel
that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, or otherwise leave floating. See the Applications
Information section.
PHASMD (G4): Connect this pin to SGND, INTVCC, or float-
ing this pin to select the phase of CLKOUT to 60 degrees,
120 degrees, and 90 degrees respectively.
CLKOUT (G5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
PGOOD1, PGOOD2 (G9, G8): Output Voltage Power
Good Indicator. Open drain logic output that is pulled to
ground when the output voltage is not within ±10% of
the regulation point.
INTVCC (H8): Internal 5V Regulator Output. The control
circuits and internal gate drivers are powered from this
voltage. Decouple this pin to PGND with a 4.7µF low ESR
tantalum or ceramic. INTVCC is activated when either RUN1
or RUN2 is activated.
TEMP (J6): Onboard General Purpose Temperature Diode
for Monitoring the VBE Junction Voltage Change with
Temperature. See the Applications Information section.
EXTVCC (J7): External power input that is enabled through
a switch to INTVCC whenever EXTVCC is greater than 4.7V.
Do not exceed 6V on this input, and connect this pin to
VIN when operating VIN on 5V. An efficiency increase will
occur that is a function of the (VIN INTVCC) multiplied by
power MOSFET driver current. Typical current requirement
is 30mA. VIN must be applied before EXTVCC, and EXTVCC
must be removed before VIN.
VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):
Power Input Pins. Apply input voltage between these pins
and GND pins. Recommend placing input decoupling
capacitance directly between VIN pins and GND pins.
(Recommended to Use Test Points to Monitor Signal Pin Connections.)
LTM463OA
LTM4630A
9
4630afb
For more information www.linear.com/LTM4630A
SIMPLIFIED BLOCK DIAGRAM
DECOUPLING REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN1, CIN2
CIN3, CIN4
External Input Capacitor Requirement
(VIN1 = 4.5V to 18V, VOUT1 = 1.5V)
(VIN2 = 4.5V to 18V, VOUT2 = 1.2V)
IOUT1 = 18A
IOUT2 = 18A
44
44
µF
µF
COUT1
COUT2
External Output Capacitor Requirement
(VIN1 = 4.5V to 18V, VOUT1 = 1.5V)
(VIN2 = 4.5V to 18V, VOUT2 = 1.2V)
IOUT1 = 18A
IOUT2 = 18A
400
400
µF
µF
TA = 25°C. Use Figure 1 configuration.
Figure 1. Simplified LTM4630A Block Diagram
4630A BD
TEMP
CLKOUT
RUN1
MODE_PLLIN
PHASEMD
TRACK1
= 100µA
OR TEMP
MONITORS
4.7µF
SS CAP 0.1µF CIN1
22µF
25V
VIN
VIN
CIN2
22µF
25V
RFB2
60.4k
MTOP1
MBOT1
POWER
CONTROL
0.22µF
0.56µH
60.4k
COUT1
RFB1
40.2k
+
VOUT1
1.5V
18A
V
OUT2
1.2V
18A
VFB1
GND
GND
VIN
4.5V TO 18V
GND
GND
SW2
SW1
PGOOD2
PGOOD1
INTERNAL
COMP
INTERNAL
COMP
INTERNAL
FILTER
0.1µF CIN3
22µF
25V
MTOP2
MBOT2
CIN4
22µF
25V
0.22µF
0.56µH
COUT2
+
+
60.4k
VOUT1
VOUT2
VFB2
VOUTS2
VOUTS1
RFSET
VIN
RT
VIN
RT
SS CAP
DIFFOUT
DIFFN
DIFFP
COMP1
SGND
TRACK2
INTVCC
EXTVCC
RUN2
COMP2
fSET
SGND
LTM463OA ‘IO
LTM4630A
10
4630afb
For more information www.linear.com/LTM4630A
OPERATION
Power Module Description
The LTM4630A is a dual-output standalone nonisolated
switching mode DC/DC power supply. It can provide two
18A outputs with few external input and output capacitors
and setup components. This module provides precisely
regulated output voltages programmable via external
resistors from 0.6VDC to 8VDC over 4.5V to 18V input
voltages. The typical application schematic is shown in
Figure 34. See Table 1 for different output current and
frequency guideline.
The LTM4630A has dual integrated constant-frequency
current mode regulators and built-in power MOSFET
devices with fast switching speed. For switching-noise
sensitive applications, it can be externally synchronized
from 300kHz to 780kHz. A resistor can be used to program
a free run frequency on the FSET pin. See the Applications
Information section.
With current mode control and internal feedback loop
compensation, the LTM4630A module has sufficient
stability margins and good transient performance with
a wide range of output capacitors, even with all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast current
limit and foldback current limit in an overcurrent condition.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD outputs low if the output feedback
voltage exits a ±10% window around the regulation point.
As the output voltage exceeds 10% above regulation, the
bottom MOSFET will turn on to clamp the output voltage.
The top MOSFET will be turned off. This overvoltage protect
is feedback voltage referred.
Pulling the RUN pins below 1.1V forces the regulators into
a shutdown state, by turning off both MOSFETs. The TRACK
pins are used for programming the output voltage ramp and
voltage tracking during start-up or used for soft-starting
the regulator. See the Applications Information section.
The LTM4630A is internally compensated to be stable
over all operating conditions. Table 6 provides a guide line
for input and output capacitances for several operating
conditions. The Linear Technology µModule Power Design
Tool will be transient and stability analysis. The VFB pin is
used to program the output voltage with a single external
resistor to ground. A differential remote sense amplifier is
available for sensing the output voltage accurately on one
of the outputs at the load point, or in parallel operation
sensing the output voltage at the load point.
Multiphase operation can be easily employed with the
MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12
phases can be cascaded to run simultaneously with re-
spect to each other by programming the PHASMD pin to
different levels. See the Applications Information section.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping opera-
tion using the MODE_PLLIN pin. These light load features
will accommodate battery operation. Efficiency graphs are
provided for light load operation in the Typical Performance
Characteristics section. See the Applications Information
section for details.
A general purpose temperature diode is included inside
the module to monitor the temperature of the module. See
the Applications Information section for details.
The switch pins are available for functional operation
monitoring and a resistor-capacitor snubber circuit can
be careful placed on the switch pin to ground to dampen
any high frequency ringing on the transition edges. See
the Applications Information section for details.
LTM463OA M FB 4 PARALLELED ouwuws -||-.~W._
LTM4630A
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The typical LTM4630A application circuit is shown in
Figure 34. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 6 for specific external capacitor
requirements for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT step-
down ratio that can be achieved for a given input voltage.
Each output of the LTM4630A is capable of 98% duty
cycle, but the VIN to VOUT minimum dropout is still shown
as a function of its load current and will limit output cur-
rent capability related to high duty cycle on the top side
switch. Minimum on-time tON(MIN) is another consideration
in operating at a specified duty cycle while operating at
a certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 90ns.
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 60.4k internal feedback
resistor connects between the VOUTS1 to VFB1 and VOUTS2
to VFB2. It is very important that these pins be connected
to their respective outputs for proper feedback regulation.
Overvoltage can occur if these VOUTS1 and VOUTS2 pins are
left floating when used as individual regulators, or at least
one of them is used in paralleled regulators. The output
voltage will default to 0.6V with no feedback resistor on
APPLICATIONS INFORMATION
either VFB1 or VFB2. Adding a resistor RFB from VFB pin to
GND programs the output voltage:
VOUT =0.6V •
60.4k
+
R
FB
R
FB
For parallel operation of multiple channels the same feed-
back setting resistor can be used for the parallel design.
This is done by connecting the VOUTS1 to the output as
shown in Figure 2, thus tying one of the internal 60.4k
resistors to the output. All of the VFB pins tie together with
one programming resistor as shown in Figure 2.
Figure 2. 4-Phase Parallel Configurations
4630A F02
60.4k
TRACK1
TRACK2
VOUT1
VOUTS1
VFB1
VFB2
COMP1
4 PARALLELED OUTPUTS
FOR 1.2V AT 70A
OPTIONAL CONNECTION
COMP2
VOUTS2
VOUT2
60.4k
60.4k
TRACK1
TRACK2
0.1µF
VOUT1
VOUTS1
VFB1
VFB2
COMP1
COMP2
VOUTS2
VOUT2
60.4k
LTM4630A
LTM4630A
RFB
60.4k
OPTIONAL
RFB
60.4k
USE TO LOWER
TOTAL EQUIVALENT
RESISTANCE TO LOWER
IFB VOLTAGE ERROR
Table 1. FREQ Resistor, VFB Resistor, Output Current vs Various Output Voltages
VOUT 0.9V 1V 1.2V 1.5V 1.8V 2.5V 3.3V 5V 8V
RFB 121k 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k 4.90k
VIN 4.5V to
18V
4.5V to
18V
4.5V to
18V
4.5V to
9V
10V to
18V
4.5V to
9V
10V to
18V
4.5V to
9V
10V to
18V
4.5V to
9V
10V to
18V
7V to
9V
10V to
18V
10V to
18V
FREQ 300kHz 300kHz 300kHz 300kHz 400kHz 300kHz 400kHz 400kHz 500kHz 500kHz 600kHz 600kHz 700kHz 770kHz
RFREQ 75k 75k 75k 75k 90.9k 75k 90.9k 90.9k 121k 121k 140k 140k 162k >240k
Peak Output Current 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A
TDP Output Current
(0LFM)
18A 18A 18A 18A 18A 18A 18A 18A 17A 18A 16A 17A 16A 15A
TDP Output Current
(200LFM or 400LPM)
18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A 18A
*TDP is Thermal Design Power at no airflow and no heat sink. Any design beyond TDP current may consider airflow or heat sink. See Current Derating
curve for different TA and airflow.
LTM463OA VOUT 12 D°(1—D)
LTM4630A
12
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APPLICATIONS INFORMATION
In parallel operation, the VFB pins have an IFB current of 20nA
maximum each channel. To reduce output voltage error due
to this current, an additional VOUTS pin can be tied to VOUT,
and an additional RFB resistor can be used to lower the total
Thevenin equivalent resistance seen by this current. For
example in Figure 2, the total Thevenin equivalent resistance
of the VFB pin is (60.4k//RFB), which is 30.2k where RFB is
equal to 60.4k for a 1.2V output. Four phases connected
in parallel equates to a worse case feedback current of
4 IFB = 80nA maximum. The voltage error is 80nA 30.2k
= 2.4mV. If VOUTS2 is connected, as shown in Figure 2, to
VOUT, and another 60.4k resistor is connected from VFB2 to
ground, then the voltage error is reduced to 1.2mV. If the
voltage error is acceptable then no additional connections
are necessary. The onboard 60.4k resistor is 0.5% accurate
and the VFB resistor can be chosen by the user to be as ac-
curate as needed. All COMP pins are tied together for current
sharing between the phases. The TRACK/SS pins can be tied
together and a single soft-start capacitor can be used to soft-
start the regulator. The soft-start equation will need to have
the soft-start current parameter increased by the number
of paralleled channels. See Output Voltage Tracking section.
Input Capacitors
The LTM4630A module should be connected to a low ac-
impedance DC source. For each regulator input two 22µF
input ceramic capacitors are used for RMS ripple current.
A 47µF to 100µF surface mount aluminum electrolytic bulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. If low impedance power
planes are used, then this bulk capacitor is not needed.
For a buck converter, the switching duty-cycle can be
estimated as:
D=VOUT
V
IN
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =IOUT(MAX)
η
% D 1D
( )
In the above equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcher-
rated electrolytic aluminum capacitor, Polymer capacitor.
Output Capacitors
The LTM4630A is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. COUT can be a low
ESR tantalum capacitor, the low ESR polymer capacitor
or ceramic capacitor. The typical output capacitance range
for each output is from 200µF to 470µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripples or dynamic transient spikes is
required. Table 6 shows a matrix of different output voltages
and output capacitors to minimize the voltage droop and
overshoot for each output channel running a 4.5A load
step. The table optimizes total equivalent ESR and total
bulk capacitance to optimize the transient performance.
Stability criteria are considered in the Table 6 matrix, and
the Linear Technology µModule Power Design Tool will be
provided for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the num-
ber of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. The Linear
Technology µModule Power Design Tool can calculate the
output ripple reduction as the number of implemented
phases increases by N times. A small value 10Ω to 50Ω
resistor can be place in series from VOUT to the VOUTS pin
to allow for a bode plot analyzer to inject a signal into the
control loop and validate the regulator stability. The same
resistor could be place in series from VOUT to DIFFP and
a bode plot analyzer could inject a signal into the control
loop and validate the regulator stability.
Burst Mode Operation
The LTM4630A is capable of Burst Mode operation on
each regulator in which the power MOSFETs operate in-
termittently based on load demand, thus saving quiescent
current. For applications where maximizing the efficiency
at very light loads is a high priority, Burst Mode operation
LTM463OA 13
LTM4630A
13
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For more information www.linear.com/LTM4630A
APPLICATIONS INFORMATION
should be applied. Burst Mode operation is enabled with
the MODE_PLLIN pin floating. During this operation, the
peak current of the inductor is set to approximately one
third of the maximum peak current value in normal opera-
tion even though the voltage at the COMP pin indicates
a lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
BURST comparator trips, causing the internal sleep line
to go high and turn off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned off,
reducing the quiescent current to about 450µA for each
output. The load current is now being supplied from the
output capacitors. When the output voltage drops, caus-
ing COMP to rise above 0.5V, the internal sleep line goes
low, and the LTM4630A resumes normal operation. The
next oscillator cycle will turn on the top power MOSFET
and the switching cycle repeats. Either regulator can be
configured for Burst Mode operation.
Pulse-Skipping Mode Operation
In applications where low output ripple and high effi-
ciency at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4630A to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFET to stay off for several cycles, thus skipping cycles.
The inductor current does not reverse in this mode. This
mode will maintain higher effective frequencies thus lower
output ripple and lower noise than Burst Mode operation.
Either regulator can be configured for pulse-skipping mode.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to GND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4630A’s output
voltage is in regulation. Either regulator can be configured
for force continuous mode.
Multiphase Operation
For output loads that demand more than 18A of current,
two outputs in LTM4630A or even multiple LTM4630As can
be paralleled to run out of phase to provide more output
current without increasing input and output voltage ripples.
The MODE_PLLIN pin allows the LTM4630A to synchronize
to an external clock (between 300kHz and 780kHz) and the
internal phase-locked-loop allows the LTM4630A to lock
onto incoming clock phase as well. The CLKOUT signal
can be connected to the MODE_PLLIN pin of the following
stage to line up both the frequency and the phase of the
entire system. Tying the PHASMD pin to INTVCC, SGND, or
(floating) generates a phase difference (between
MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,
or 90 degrees respectively. A total of 12 phases can be
cascaded to run simultaneously with respect to each other
by programming the PHASMD pin of each LTM4630A chan-
nel to different levels. Figure 3 shows a 2-phase design,
4-phase design and a 6-phase design example for clock
phasing with the PHASMD table.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.
The LTM4630A device is an inherently current mode
controlled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Figure 35 shows an example of parallel operation
and pin connection.
LTM4630A PHASE 14
LTM4630A
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Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
DUTY FACTOR (VOUT/VIN)
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
6-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
APPLICATIONS INFORMATION
Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table
4630A F03
VOUT2
180 PHASE0 PHASE MODE_PLLIN
VOUT1
PHASMD
CLKOUT
2-PHASE DESIGN
4-PHASE DESIGN
6-PHASE DESIGN
90 DEGREE
FLOAT
VOUT2
180 PHASE0 PHASE
FLOAT
MODE_PLLIN
VOUT1
PHASMD
CLKOUT
VOUT2
270 PHASE90 PHASE
FLOAT
MODE_PLLIN
VOUT1
PHASMD
CLKOUT
60 DEGREE 60 DEGREE
VOUT2
180 PHASE0 PHASE
SGND
MODE_PLLIN
VOUT1
PHASMD
CLKOUT
VOUT2
240 PHASE60 PHASE
SGND
MODE_PLLIN
VOUT1
PHASMD
CLKOUT
VOUT2
300 PHASE120 PHASE
FLOAT
MODE_PLLIN
VOUT1
PHASMD
CLKOUT
PHASMD SGND
CONTROLLER1
CONTROLLER2
CLKOUT
FLOAT INTVCC
0 0 0
180 180 240
60 90 120
VOUT LTM4630A 15
LTM4630A
15
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APPLICATIONS INFORMATION
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancel-
lation mathematical derivations are presented, and a graph
is displayed representing the RMS ripple current reduction
as a function of the number of interleaved phases. Figure 4
shows this graph.
Frequency Selection and Phase-Lock Loop
(MODE/PLLIN and fSET Pins)
The LTM4630A device is operated over a range of frequen-
cies to improve power conversion efficiency. It is recom-
mended to operate the lower output voltages or lower
duty cycle conversions at lower frequencies to improve
efficiency by lowering power MOSFET switching losses.
Higher output voltages or higher duty cycle conversions
can be operated at higher frequencies to limit inductor
ripple current. The efficiency graphs will show an operat-
ing frequency chosen for that condition. See Table 1 for
optimized frequency for various output voltages. Select
frequency in reference to the highest output voltage.
The LTM4630A switching frequency can be set with an
external resistor from the fSET pin to SGND. An accurate
10µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be
applied. Figure 5 shows a graph of frequency setting
verses programming voltage. An external clock can be
applied to the MODE_PLLIN pin from 0V to INTVCC over
a frequency range of 300kHz to 780kHz. The clock input
high threshold is 1.6V and the clock input low threshold
is 1V. The LTM4630A has the PLL loop filter components
on board. The frequency setting resistor should always
be present to set the initial switching frequency before
locking to an external clock. Both regulators will operate
in continuous mode while being externally clock.
The output of the PLL phase detector has a pair of comple-
mentary current sources that charge and discharge the
internal filter network. When the external clock is applied
then the fSET frequency resistor is disconnected with
an internal switch, and the current sources control the
frequency adjustment to lock to the incoming external
clock. When no external clock is applied, then the internal
switch is on, thus connecting the external fSET frequency
set resistor for free run operation.
Minimum On-Time
Minimum on-time tON is the smallest time duration that
the LTM4630A is capable of turning on the top MOSFET on
either channel. It is determined by internal timing delays,
and the gate charge required turning on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
VOUT
VIN • FREQ
>tON(MIN)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple and current will increase. The on-time
can be increased by lowering the switching frequency. A
good rule of thumb is to keep on-time longer than 110ns.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pins. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4630A uses
an accurate 60.4k resistor internally for the top feedback
Figure 5. Operating Frequency vs fSET Pin Voltage
fSET PIN VOLTAGE (V)
0
FREQUENCY (kHz)
900
800
600
400
100
200
700
500
300
02
4630A F05
2.51 1.50.5
LTM463OA «HQ 3V " A: 16 W“ l—H~ «+14 I—
LTM4630A
16
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APPLICATIONS INFORMATION
Figure 7. Output Coincident Tracking Waveform
Figure 6. Example of Output Tracking Application Circuit
TIME
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT VOLTAGE
4630A F07
4630A F06
LTM4630A
VIN
TEMP
RUN1
RUN2
TRACK1
TRACK2
fSET
C8
470µF
6.3V
RFB
60.4k
R2
10k
C6
100µF
6.3V
PHASMD
VOUT1
VOUTS1
SW1
VFB1
VFB2
COMP1
COMP2
VOUTS2
VOUT2
SW2
PGOOD2
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
PGOOD
INTVCC
SGND GND
VOUT1
1.5V
MASTER
DIFFP DIFFN DIFFOUT
40.2k
PGOOD
SLAVE
VOUT2
1.2V AT 18A
VOUT1
1.5V AT 18A
C7
470µF
6.3V
C5
100µF
6.3V
R4
90.9k
RTB
60.4k
4V TO 15V INTERMEDIATE BUS
R6
100k
CSS
0.1µF
C1
22µF
25V
RTA
90.9k
C2
22µF
25V
C3
22µF
25V
C4
22µF
25V
C10
4.7µF
R9
10k
INTVCC
RAMP TIME
tSOFTSTART = (CSS/1.3µA) • 0.6
resistor for each channel. Figure 6 shows an example of
coincident tracking. Equations:
SLAVE =1+60.4k
RTA
• VTRACK
VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.6V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
tracking is disabled when VTRACK is more than 0.6V. RTA
in Figure 6 will be equal to the RFB for coincident tracking.
Figure 7 shows the coincident tracking waveforms.
The TRACK pin of the master can be controlled by a
capacitor placed on the master regulator TRACK pin to
ground. A 1.3µA current source will charge the TRACK
pin up to the reference voltage and then proceed up
to INTVCC. After the 0.6V ramp, the TRACK pin will no
longer be in control, and the internal voltage reference
will control output regulation from the feedback divider.
Foldback current limit is disabled during this sequence
of turn-on during tracking or soft-starting. The TRACK
pins are pulled low when the RUN pin is below 1.2V. The
total soft-start time can be calculated as:
tSOFT-START =CSS
1.3µA
• 0.6
Regardless of the mode selected by the MODE_PLLIN pin,
the regulator channels will always start in pulse-skipping
mode up to TRACK = 0.5V. Between TRACK = 0.5V and
LTM463OA VFB Vi VTRACK FB TB 17
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APPLICATIONS INFORMATION
0.54V, it will operate in forced continuous mode and revert
to the selected mode once TRACK > 0.54V. In order to
track with another channel once in steady state operation,
the LTM4630A is forced into continuous mode operation
as soon as VFB is below 0.54V regardless of the setting
on the MODE_PLLIN pin.
Ratiometric tracking can be achieved by a few simple cal-
culations and the slew rate value applied to the master’s
TRACK pin. As mentioned above, the TRACK pin has a
control range from 0 to 0.6V. The master’s TRACK pin
slew rate is directly equal to the master’s output slew rate
in Volts/Time. The equation:
MR
SR
• 60.4k =RTB
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus RTB
is equal the 60.4k. RTA is derived from equation:
RTA =
0.6V
VFB
60.4k +VFB
R
FB
VTRACK
R
TB
where VFB is the feedback voltage reference of the regula-
tor, and VTRACK is 0.6V. Since RTB is equal to the 60.4k
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then RTA is equal to RFB with
VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in
Figure 6.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR is
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
RTB = 76.8k. Solve for RTA to equal to 49.9k.
Each of the TRACK pins will have the 1.3µA current source
on when a resistive divider is used to implement tracking
on that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A resistor can
be pulled up to a particular supply voltage no greater than
6V maximum for monitoring.
Stability Compensation
The module has already been internally compensated
for all output voltages. Table 6 is provided for most ap-
plication requirements. The Linear Technology µModule
Power Design Tool will be provided for other control loop
optimization.
Run Enable
The RUN pins have an enable threshold of 1.4V maximum,
typically 1.25V with 150mV of hysteresis. They control the
turn on each of the channels and INTVCC. These pins can be
pulled up to VIN for 5V operation, or a 5V Zener diode can be
placed on the pins and a 10k to 100k resistor can be placed
up to higher than 5V input for enabling the channels. The
RUN pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tie together and
controlled from a single control. See the Typical Applica-
tion circuits in Figure 34.
INTVCC and EXTVCC
The LTM4630A module has an internal 5V low dropout
regulator that is derived from the input voltage. This regu-
lator is used to power the control circuitry and the power
MOSFET drivers. This regulator can source up to 70mA,
and typically uses ~30mA for powering the device at the
maximum frequency. This internal 5V supply is enabled
by either RUN1 or RUN2.
EXTVCC allows an external 5V supply to power the LTM4630A
and reduce power dissipation from the internal low dropout
5V regulator. The power loss savings can be calculated by:
(VIN – 5V) • 30mA = PLOSS
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EXTVCC has a threshold of 4.7V for activation, and a
maximum rating of 6V. When using a 5V input, connect
this 5V input to EXTVCC also to maintain a 5V gate drive
level. EXTVCC must sequence on after VIN, and EXTVCC
must sequence off before VIN.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is provided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
and DIFFOUT is connected to either VOUTS1 or VOUTS2.
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
one of the VOUTS pins. Review the parallel schematics in
Figure 32 and review Figure 2. The diffamp can only be
used for output voltage ≤ 3.3V.
SW Pins
The SW pins are generally for testing purposes by moni-
toring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combina-
tion is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance Z
can be calculated:
ZL = 2πfL,
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: ZC = 1/(2πfC). These values are a good place to
start with. Modification to these components should be made
to attenuate the ringing with the least amount of power loss.
Temperature Monitoring
A diode connected PNP transistor is used for the TEMP
monitor function by monitoring its voltage over tempera-
ture. The temperature dependence of this diode voltage
can be understood in the equation:
VD=nVTln ID
IS
where VT is the thermal voltage (kT/q), and n, the ideality
factor, is 1 for the diode connected PNP transistor being
used in the LTM4630A. IS is expressed by the typical
empirical equation:
IS=I0exp VG0
VT
where I0 is a process and geometry dependent current, (I0
is typically around 20k orders of magnitude larger than IS
at room temperature) and VG0 is the band gap voltage of
1.2V extrapolated to absolute zero or –273°C.
If we take the IS equation and substitute into the VD equa-
tion, then we get:
VD=VG0 kT
q
ln I0
ID
, VT=kT
q
The expression shows that the diode voltage decreases
(linearly if I0 were constant) with increasing temperature
and constant diode current. Figure 8 shows a plot of VD
vs Temperature over the operating temperature range of
the LTM4630A.
If we take this equation and differentiate it with respect to
temperature T, then:
dVD
dT
=
V
G0
V
D
T
This dVD/dT term is the temperature coefficient equal to
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
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Solving for T, T = –(VG0 VD)/(dVD/dT) provides the
temperature.
1st Example: Figure 8 for 27°C, or 300K the diode
voltage is 0.598V, thus, 300K = –(1200mV 598mV)/
–2.0 mV/K)
2nd Example: Figure 8 for 75°C, or 350K the diode
voltage is 0.50V, thus, 350K = –(1200mV 500mV)/
–2.0mV/K)
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temp and subtracting 273 from it.
A typical forward voltage is given in the electrical charac-
teristics section of the data sheet, and Figure 8 is the plot
of this forward voltage. Measure this forward voltage at
27°C to establish a reference point. Then using the above
expression while measuring the forward voltage over
temperature will provide a general temperature monitor.
Connect a resistor between TEMP and VIN to set the cur-
rent to 100µA. See Figure 35 for an example.
Package Thermal Measurements”). The motivation for
providing these thermal coefficients is found in JESD51-12
(“Guidelines for Reporting and Using Electronic Package
Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plication at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coef-
ficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambi-
ent, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package.
In the typical µModule, the bulk of the heat flows out
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions dont generally match
the user’s application.
3. θJCTOP, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
Figure 8. Diode Voltage VD vs Temperature T(K)
for Different Bias Currents
TEMPERATURE (°C)
–50 –25
0.3
DIODE VOLTAGE (V)
0.5
0.8
050 75
0.4
0.7
0.6
25 100
4630A F08
125
ID = 100µA
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation, and
correlation to hardware evaluation performed on a µModule
package mounted to a hardware test board—also defined
by JESD51-9 (“Test Boards for Area Array Surface Mount
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APPLICATIONS INFORMATION
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most
of the heat flows from the junction to the top of the
part. As in the case of θJCBOTTOM, this value may be
useful for comparing packages but the test conditions
don’t generally match the user’s application.
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal re-
sistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 9; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal op-
erating conditions of a µModule. For example, in normal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclu-
sively through the top or exclusively through bottom of the
µModuleas the standard defines for θJCtop and θJCbottom,
respectively. In practice, power loss is thermally dissipated
in both directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JESD51-9 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation of
the JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
4630A F09
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION
AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
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operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power loss
as that which was simulated. An outcome of this process
and due-diligence yields a set of derating curves provided
in other sections of this data sheet. After these laboratory
test have been performed and correlated to the µModule
model, then the θJB and θBA are summed together to cor-
relate quite well with the µModule model with no airflow or
heat sinking in a properly define chamber. This θJB + θBA
value is shown in the Pin Configuration section and should
accurately equal the θJA value because approximately
100% of power loss flows from the junction through the
board into ambient with no airflow or top mounted heat
sink. Each system has its own thermal characteristics,
therefore thermal analysis must be performed by the user
in a particular system.
The LTM4630A module has been designed to effectively
remove heat from both the top and bottom of the pack-
age. The bottom substrate material has very low thermal
resistance to the printed circuit board. An external heat
sink can be applied to the top of the device for excellent
heat sinking with airflow.
Figures 10 and 11 show temperature plots of the LTM4630A
with no heat sink and 200LFM airflow.
These plots equate to a paralleled 12V to 1.0V at 36A
design operating at 86.5% efficiency, and 12V to 3.3V at
36A design operating at 93.7% efficiency.
APPLICATIONS INFORMATION
Safety Considerations
The LTM4630A modules do not provide isolation from
VIN to VOUT. There is no internal fuse. If required, a slow
blow fuse with a rating twice the maximum input current
needs to be provided to protect each unit from catastrophic
failure. The device does support over current protection.
A temperature diode is provided for monitoring internal
temperature, and can be used to detect the need for thermal
shutdown that can be done by controlling the RUN pin.
Power Derating
The 1.0V, 1.8V, 3.3V, 5V and 8V power loss curves in
Figures 13 to 17 can be used in coordination with the load
current derating curves in Figures 18 to 33 for calculating
an approximate ΘJA thermal resistance for the LTM4630A
with various heat sinking and airflow conditions. The
power loss curves are taken at room temperature, and are
increased with a 1.35 to 1.4 multiplicative factor at 125°C.
These factors come from the fact that the power loss of the
regulator increases about 45% from 25°C to 150°C, thus a
50% spread over 125°C delta equates to ~0.35%/°C loss
increase. A 125°C maximum junction minus 25°C room
temperature equates to a 100°C increase. This 100°C
increase multiplied by 0.35%/°C equals a 35% power loss
increase at the 125°C junction, thus the 1.35 multiplier.
The derating curves are plotted with CH1 and CH2 in
parallel single output operation starting at 36A of load
with low ambient temperature. The output voltages are
1.0V, 1.8V, 3.3V, 5V and 8V. These are chosen to include
the lower and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived from
several temperature measurements in a controlled tem-
perature chamber along with thermal modeling analysis.
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Figure 10. Thermal Image 12V to 1.0V,
36A with 200LFM without Heat Sink
Figure 11. Thermal Image 12V to 3.3V,
36A with 200LFM without Heat Sink
APPLICATIONS INFORMATION
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The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
Figure 22, the load current is derated to ~28A at ~70°C with
no air or heat sink and the power loss for the 12V to 1.8V
at 28A output is a ~6.3W loss. The 6.3W loss is calculated
with the ~3.6W room temperature loss from the 12V to
1.8V power loss curve at 28A, and the 1.35 multiplying
factor at 120°C junction. If the 70°C ambient temperature
is subtracted from the 120°C junction temperature, then
the difference of 50°C divided by 6.3W equals an 8.0°C/W
ΘJA thermal resistance. Table 2 specifies a 8.5°C/W value
which is pretty close. The airflow graphs are more accurate
due to the fact that the ambient temperature environment
is controlled better with airflow. Tables 2 to 6 provide
equivalent thermal resistances for 1V to 8V outputs with
and without airflow and heat sinking.
The derived thermal resistances in Tables 2 to 6 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature. Room temperature power loss can be derived
from the efficiency curves and adjusted with the above
ambient temperature multiplicative factors. The printed
circuit board is a 1.6mm thick four layer board with two
ounce copper for the two outer layers and one ounce
copper for the two inner layers. The PCB dimensions are
101mm × 114mm. The heat sinks are listed in Table 6.
Layout Checklist/Example
The high integration of LTM4630A makes the PCB board
layout very simple and easy. However, to optimize its electri-
cal and thermal performance, some layout considerations
are still necessary.
Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to
minimize the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capaci-
tors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
Place a dedicated power ground layer underneath the
unit.
To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
Do not put via directly on the pad, unless they are
capped or plated over.
Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
Bring out test points on the signal pins for monitoring.
Figure 12 gives a good example of the recommended layout.
APPLICATIONS INFORMATION
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APPLICATIONS INFORMATION
Figure 12. Recommended PCB Layout
GND
GND GND
SGND
CNTRLCNTRL
VOUT1
COUT1 COUT2
VOUT2
VIN
CIN1 CIN2
1 2 3 4 5 6 7 8 109 11 12
L
K
J
H
G
F
E
D
C
B
M
A
4630A F12
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Table 2. 1.0V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 18, 19 5, 12 Figure 13 0 None 8.5
Figures 18, 19 5, 12 Figure 13 200 None 7
Figures 18, 19 5, 12 Figure 13 400 None 6
Figures 20, 21 5, 12 Figure 13 0 BGA Heat Sink 8
Figures 20, 21 5, 12 Figure 13 200 BGA Heat Sink 6
Figures 20, 21 5, 12 Figure 13 400 BGA Heat Sink 5
Table 3. 1.8V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 22, 23 5, 12 Figure 14 0 None 8.5
Figures 22, 23 5, 12 Figure 14 200 None 7
Figures 22, 23 5, 12 Figure 14 400 None 6
Figures 24, 25 5, 12 Figure 14 0 BGA Heat Sink 8
Figures 24, 25 5, 12 Figure 14 200 BGA Heat Sink 6
Figures 24, 25 5, 12 Figure 14 400 BGA Heat Sink 5
APPLICATIONS INFORMATION
Table 4. 3.3V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 26, 27 5, 12 Figure 15 0 None 8.5
Figures 26, 27 5, 12 Figure 15 200 None 7
Figures 26, 27 5, 12 Figure 15 400 None 6
Figures 28, 29 5, 12 Figure 15 0 BGA Heat Sink 8
Figures 28, 29 5, 12 Figure 15 200 BGA Heat Sink 6
Figures 28, 29 5, 12 Figure 15 400 BGA Heat Sink 5
Table 5. 5V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 30 12 Figure 16 0 None 8.5
Figures 30 12 Figure 16 200 None 7
Figures 30 12 Figure 16 400 None 6
Figures 31 12 Figure 16 0 BGA Heat Sink 8
Figures 31 12 Figure 16 200 BGA Heat Sink 6
Figures 31 12 Figure 16 400 BGA Heat Sink 5
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APPLICATIONS INFORMATION
Table 7. Dual Channel Single Output Voltage Response vs Component Matrix (Refer to Figure 32, 0A to 9A, ±25% Load Step Typical
Measured Values)
CIN (BULK)* PART NUMBER VALUE CIN (CERAMIC) PART NUMBER VALUE
SUN Electronic 25CE150AX 150µF, 25V Murata GRM219R61C226ME15L 22µF, 16V, 0805, X5R
Panasonic EEH-ZC1E101XP 100µF, 25V Taiyo Yuden EMK212BBJ226MG-T 22µF, 16V, 0805, X5R
Murata GRM31CR61E226KE15L 22µF, 25V, 1206, X5R
Taiyo Yuden TMK316BBJ226ML-T 22µF, 25V, 1206, X5R
COUT (BULK) PART NUMBER VALUE COUT (CERAMIC) PART NUMBER VALUE
Panasonic 6TPF220M5L 220µF, POSCAP, 6.3V, 5mΩ ESR Murata GRM31CR60J107ME39L 100µF, 6.3V, 1206, X5R
Panasonic 6TPF330M5EL 330µF, POSCAP, 6.3V, 5mΩ ESR Murata GRM31CR60G227ME11# 220µF, 4V, 1206, X5R
Panasonic 6TPE470MI 470µF, POSCAP, 6.3V, 18mΩ ESR Taiyo Yuden JMK316BJ107ML-T 100µF, 6.3V, 1206, X5R
Panasonic 4TPF470M5EL 470µF, POSCAP, 4V, 5mΩ ESR Taiyo Yuden JMK325ABJ227MM-T 220µF, 6.3V, 1210, X5R
HEAT SINK MANUFACTURER PART NUMBER WEBSITE
Aavid Thermalloy 375424B00034G www.aavid.com
VOUT (V)
CIN
(CERAMIC) CIN (BULK)
COUT
(CERAMIC)
COUT
(BULK)
CFF
(pF)
VIN
(V)
DROOP
(mV)
P-P
DEVIATION
(mV)
RECOVERY
TIME
(µs)
LOAD
STEP
(A)
LOAD
STEP
(A/µs)
RFB
(kΩ)
1 22µF × 4 150µF 100µF × 4 220µF × 2 N/A 5, 12 0 68 20 9 9 90.9
1.2 22µF × 4 150µF 100µF × 4 220µF × 2 N/A 5, 12 0 74 20 9 9 60.4
1.5 22µF × 4 150µF 100µF × 4 220µF × 2 N/A 5, 12 0 72 20 9 9 40.2
1.8 22µF × 4 150µF 100µF × 4 220µF × 2 N/A 5, 12 0 76 30 9 9 30.2
2.5 22µF × 4 150µF 100µF × 4 220µF × 2 N/A 5, 12 0 74 30 9 9 19.1
3.3 22µF × 4 150µF 100µF × 4 220µF × 2 N/A 5, 12 0 72 30 9 9 13.3
5 22µF × 4 150µF 100µF × 4 220µF × 2 N/A 5, 12 0 78 40 9 9 8.25
*Bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads.
Table 6. 8V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 32 12 Figure 17 0 None 8.5
Figures 32 12 Figure 17 200 None 7
Figures 32 12 Figure 17 400 None 6
Figures 33 12 Figure 17 0 BGA Heat Sink 8
Figures 33 12 Figure 17 200 BGA Heat Sink 6
Figures 33 12 Figure 17 400 BGA Heat Sink 5
LTM4630A 27
LTM4630A
27
4630afb
For more information www.linear.com/LTM4630A
APPLICATIONS INFORMATION
Figure 13. 1.0VOUT Power Loss
Curve
Figure 14. 1.8VOUT Power Loss
Curve
Figure 15. 3.3VOUT Power
Loss Curve
Figure 16. 5VOUT Power Loss
Curve
Figure 17. 8VOUT Power Loss
Curve
Figure 18. 12V to 1V Derating
Curve, No Heat Sink
Figure 19. 5V to 1V Derating
Curve, No Heat Sink
Figure 20. 12V to 1V Derating
Curve, BGA Heat Sink
Figure 21. 5V to 1V Derating
Curve, BGA Heat Sink
LOAD CURRENT (A)
0 642
0
POWER LOSS (W)
6.0
8.0
1082018 28262422
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
7.5
7.0
6.5
161412 3230
4630A F13
3634
5VIN
12VIN
LOAD CURRENT (A)
0 642
0
POWER LOSS (W)
6.0
8.0
1082018 28262422
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
7.5
7.0
6.5
161412 3230
4630A F14
3634
5VIN
12VIN
LOAD CURRENT (A)
0 642
0
POWER LOSS (W)
6.0
8.0
1082018 28262422
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
7.5
7.0
6.5
161412 3230
4630A F15
3634
5VIN
12VIN
LOAD CURRENT (A)
0 642
0
POWER LOSS (W)
8.0
10
1082018 28262422
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
9.5
9.0
8.5
161412 3230
4630A F16
3634
12VIN
LOAD CURRENT (A)
0 642
0
POWER LOSS (W)
8.0
10
1082018 28262422
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
9.5
9.0
8.5
161412 3230
4630A F17
3634
12VIN
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110
4630A F18
120
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110 120
4630A F19
130
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110
4630A F20
120
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110 120
4630A F21
130
400LFM
200LFM
0LFM
LTM463OA
LTM4630A
28
4630afb
For more information www.linear.com/LTM4630A
APPLICATIONS INFORMATION
Figure 22. 12V to 1.8V Derating
Curve, No Heat Sink
Figure 23. 5V to 1.8V Derating
Curve, No Heat Sink
Figure 24. 12V to 1.8V Derating
Curve, BGA Heat Sink
Figure 25. 5V to 1.8V Derating
Curve, BGA Heat Sink
Figure 26. 12V to 3.3V Derating
Curve, No Heat Sink
Figure 27. 5V to 3.3V Derating
Curve, No Heat Sink
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110
4630A F22
120
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110 120
4630A F23
130
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110
4630A F24
120
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110 120
4630A F25
130
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060
4630A F26
110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110
4630A F27
120
400LFM
200LFM
0LFM
LTM4630A 2V EWEB 23 2:555” 33 Emmma 33 a n no no 29
LTM4630A
29
4630afb
For more information www.linear.com/LTM4630A
APPLICATIONS INFORMATION
Figure 28. 12V to 3.3V Derating
Curve, BGA Heat Sink
Figure 31. 12V TO 5V Derating
Curve, BGA Heat Sink
Figure 29. 5V to 3.3V Derating
Curve, BGA Heat Sink
Figure 32. 12V to 8V Derating
Curve, No Heat Sink
Figure 30. 12V to 5V Derating
Curve, No Heat Sink
Figure 33. 12V to 8V Derating
Curve, BGA Heat Sink
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060
4630A F28
110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060
4630A F31
110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060 110 120
4630A F29
130
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060
4630A F32
110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060
4630A F30
110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30 40
0
LOAD CURRENT (A)
40
50 80 10090
30
25
20
15
10
5
35
7060
4630A F33
110
400LFM
200LFM
0LFM
LTM463OA
LTM4630A
30
4630afb
For more information www.linear.com/LTM4630A
Figure 34. Typical 4.5VIN to 18VIN, 300kHz, 1.0V and 1.2V at 18A Outputs
APPLICATIONS INFORMATION
4630A F31
LTM4630A
VIN
TEMP
RUN1
RUN2
TRACK1
TRACK2
fSET
COUT2
470µF
6.3V
RFB2
60.4k
R2
10k
COUT1
100µF
6.3V
PHASMD
VOUT1
VOUTS1
SW1
VFB1
VFB2
COMP1
COMP2
VOUTS2
VOUT2
SW2
PGOOD2
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
PGOOD1
INTVCC
SGND GND
TRACK1
TRACK2
DIFFP DIFFN DIFFOUT
RFB1
90.9k
PGOOD2
VOUT2
1.2V AT 18A
CFF*
CBOT*
CCOMP*
COUT2
470µF
6.3V
COUT1
100µF
6.3V
R4
75k
4.5V TO 18V INTERMEDIATE BUS
R7
100k
C5
0.1µF C9
0.1µF
C1
22µF
25V
C2
22µF
25V
C3
22µF
25V
C4
22µF
25V
C10
4.7µF
VOUT1
1.0V AT 18A
R3
10k
INTVCC
+
+
+
CIN
(OPT)
VIN
4.5V TO 18V
*SEE TABLE 6
LTM463OA 4i | m | | | J _ W :E m a M | U I_, 4H- w m- 4H- _ 4H- 4H- 31
LTM4630A
31
4630afb
For more information www.linear.com/LTM4630A
TYPICAL APPLICATIONS
Figure 35. LTM4630A 2-Phase, 600kHz, 3.3V at 28A Design with Temperature Monitoring
4630A F32
LTM4630A
VIN
TEMP
RUN1
RUN2
TRACK1TRACK1
TRACK2
fSET
COUT2
470µF
6.3V
R5
13.3k
COUT1
100µF
6.3V
PHASMD
VOUT1
VOUTS1
SW1
VFB1
VFB2
COMP1
COMP2
VOUTS2
VOUT2
SW2
PGOOD2 PGOOD1
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
PGOOD1
R2
10k
INTVCC
SGND GND DIFFP DIFFN DIFFOUT
COUT2
470µF
6.3V
COUT1
100µF
6.3V
R4
140k
4.5V TO 18V INTERMEDIATE BUS
C9
0.1µF
C1
22µF
25V
C2
22µF
25V
C11
22µF
25V
C3
22µF
25V
C10
4.7µF
+
+
INTVCC
A/D
µC
VIN
RT
VIN
4.5V TO 18V
VOUT
3.3V
28A
RT = VIN
100µA
LTM463OA
LTM4630A
32
4630afb
For more information www.linear.com/LTM4630A
TYPICAL APPLICATIONS
Figure 36. LTM4630A 3.3V and 2.5V Output with Tracking Function
4630A F33
LTM4630A
VIN
TEMP
RUN1
RUN2
TRACK1
TRACK2
fSET
COUT2
470µF
6.3V
R8
19.1k
R2
10k
COUT1
100µF
6.3V
PHASMD
VOUT1
VOUTS1
SW1
VFB1
VFB2
COMP1
COMP2
VOUTS2
VOUT2
SW2
PGOOD2
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
PGOOD1
INTVCC
INTVCC
SGND GND DIFFP DIFFN DIFFOUT
R5
13.3k
PGOOD2
COUT2
470µF
6.3V
COUT1
100µF
6.3V
R4
140k
R9
60.4k
4.5V TO 18V INTERMEDIATE BUS
R6
100k
C5
0.1µF
C1
22µF
25V
R7
19.1k
C2
22µF
25V
C3
22µF
25V
C4
22µF
25V
C10
4.7µF
+
+
R3
10k
VOUT1
3.3V
15A
VIN
4.5V TO 18V
VOUT2
2.5V AT 15A
VOUT1
3.3V
LTM463OA im; ul— __+I_+l__ m: If. 33
LTM4630A
33
4630afb
For more information www.linear.com/LTM4630A
TYPICAL APPLICATIONS
Figure 37. LTM4630A 4-Phase, 1.2V at 70A Output Design
4630A F34
LTM4630A
VIN
TEMP
RUN1
RUN
RUN1
RUN2
TRACK1TRACK
TRACK2
fSET
COUT2
470µF
6.3V
R5
60.4k
R2
5k
COUT1
100µF
6.3V
PHASMD
VOUT1
VOUTS1
SW1
VFB1
VFB2
COMP1
COMP2 COMP
VOUTS2
VOUT2
SW2
PGOOD2 PGOOD
MODE_PLLIN CLKOUT
CLK1
CLK1
INTVCC EXTVCC PGOOD1
PGOOD
SGND GND DIFFP DIFFN DIFFOUT
COUT2
470µF
6.3V
COUT1
100µF
6.3V
R4
75k
R6
100k
C1
22µF
25V
C2
22µF
25V
C3
22µF
25V
C10
4.7µF
+
+
LTM4630A
VIN
TEMP
RUN1
RUN2
TRACK1
TRACK2
fSET
COUT2
470µF
6.3V
COUT1
100µF
6.3V
VIN
4.5V TO 18V
PHASMD
VOUT1
VOUTS1
SW1
VFB1
VFB2
COMP1
VFB
COMP
COMP2
VOUTS2
VOUT2
SW2
PGOOD2 PGOOD
MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1
PGOOD
SGND GND DIFFP DIFFN DIFFOUT
COUT2
470µF
6.3V
COUT1
100µF
6.3V
R10
75k
R9
100k
C5
22µF
25V
C19
0.22µF
C15
22µF
25V
C12
22µF
25V
C16
4.7µF
+
+
INTVCC
TRACK
VFB
INTVCC
VOUT
1.2V
70A
LTM463OA 5.01mm <—16mm—>/ 15mm
LTM4630A
34
4630afb
For more information www.linear.com/LTM4630A
LTM4630A Component LGA and BGA Pinout
PACKAGE DESCRIPTION
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 VOUT1 B1 VOUT1 C1 VOUT1 D1 GND E1 GND F1 GND
A2 VOUT1 B2 VOUT1 C2 VOUT1 D2 GND E2 GND F2 GND
A3 VOUT1 B3 VOUT1 C3 VOUT1 D3 GND E3 GND F3 GND
A4 VOUT1 B4 VOUT1 C4 VOUT1 D4 GND E4 GND F4 MODE_PLLIN
A5 VOUT1 B5 VOUT1 C5 VOUT1S D5 VFB1 E5 TRACK1 F5 RUN1
A6 GND B6 GND C6 fSET D6 SGND E6 COMP1 F6 SGND
A7 GND B7 GND C7 SGND D7 VFB2 E7 COMP2 F7 SGND
A8 VOUT2 B8 VOUT2 C8 VOUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT
A9 VOUT2 B9 VOUT2 C9 VOUT2 D9 GND E9 DIFFN F9 RUN2
A10 VOUT2 B10 VOUT2 C10 VOUT2 D10 GND E10 GND F10 GND
A11 VOUT2 B11 VOUT2 C11 VOUT2 D11 GND E11 GND F11 GND
A12 VOUT2 B12 VOUT2 C12 VOUT2 D12 GND E12 GND F12 GND
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND
G2 SW1 H2 GND J2 VIN K2 VIN L2 VIN M2 VIN
G3 GND H3 GND J3 VIN K3 VIN L3 VIN M3 VIN
G4 PHASEMD H4 GND J4 VIN K4 VIN L4 VIN M4 VIN
G5 CLKOUT H5 GND J5 GND K5 GND L5 VIN M5 VIN
G6 SGND H6 GND J6 TEMP K6 GND L6 VIN M6 VIN
G7 SGND H7 GND J7 EXTVCC K7 GND L7 VIN M7 VIN
G8 PGOOD2 H8 INTVCC J8 GND K8 GND L8 VIN M8 VIN
G9 PGOOD1 H9 GND J9 VIN K9 VIN L9 VIN M9 VIN
G10 GND H10 GND J10 VIN K10 VIN L10 VIN M10 VIN
G11 SW2 H11 GND J11 VIN K11 VIN L11 VIN M11 VIN
G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND
PACKAGE PHOTO
LGA BGA
LTM463OA // \ TIL EEL 35
LTM4630A
35
4630afb
For more information www.linear.com/LTM4630A
LGA Package
144-Lead (16mm × 16mm × 4.41mm)
(Reference LTC DWG # 05-08-1901 Rev B)
DETAIL B
DETAIL B
SUBSTRATE
MOLD
CAP
// bbb Z
Z
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
LAND DESIGNATION PER JESD MO-222, SPP-010
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 144
4
3
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
PACKAGE TOP VIEW
4
PAD “A1”
CORNER
X
Y
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
3
SEE NOTES
D
E
b
e
e
b
F
G
LGA 144 0213 REV B
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1
SYMBOL
A
b
D
E
e
F
G
H1
H2
aaa
bbb
eee
MIN
4.31
0.60
0.36
3.95
NOM
4.41
0.63
16.0
16.0
1.27
13.97
13.97
0.41
4.00
MAX
4.51
0.66
0.46
4.05
0.15
0.10
0.05
NOTES
DIMENSIONS
TOTAL NUMBER OF LGA PADS: 144
H2
H1
DETAIL A
DIA 0.630
PAD 1
L K J H G F E D C BM A
1
2
3
4
5
6
7
8
10
9
11
12
SUGGESTED PCB LAYOUT
TOP VIEW
0.0000
0.0000
0.630 ±0.025 SQ. 143x
0.6350
0.6350
1.9050
1.9050
3.1750
3.1750
4.4450
4.4450
5.7150
5.7150
6.9850
6.9850
6.9850
5.7150
5.7150
4.4450
4.4450
3.1750
3.1750
1.9050
1.9050
0.6350
0.6350
6.9850
DETAIL A
0.630 ±0.025 SQ. 143x
SYXZØ eee 3x, C (0.22 x45°)
7
SEE NOTES
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
LTMXXXXXX
µModule
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4630A#packaging for the most recent package drawings.
LTM463OA JL_ \OOOOOOWOOOOOO . . woo-000M000... $3235..“ \/ vgmngl 7K: ‘l‘p ‘ “““ ‘ 44 q 4\ \x _\ P‘ ,, n , J D L ‘9 . 7 _H_ ‘Cy..,,. W...... ,,/;...\_,...,......“ ,{K Til ELL <\ .ia-l.="" 36="">
LTM4630A
36
4630afb
For more information www.linear.com/LTM4630A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC4630A#packaging for the most recent package drawings.
BGA Package
144-Lead (16mm × 16mm × 5.01mm)
(Reference LTC DWG # 05-08-1969 Rev Ø)
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
X
Y
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
3
SEE NOTES
D
E
b
e
e
b
F
G
BGA 144 0114 REV Ø
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1
LTMXXXXXX
µModule
DETAIL A
PIN 1
11
10
9
8
7
6
5
4
3
2
12
1
ABCDEFGHK JLM
SUGGESTED PCB LAYOUT
TOP VIEW
0.0000
0.0000
0.630 ±0.025 Ø 144x
0.6350
0.6350
1.9050
1.9050
3.1750
3.1750
4.4450
4.4450
5.7150
5.7150
6.9850
6.9850
6.9850
5.7150
5.7150
4.4450
4.4450
3.1750
3.1750
1.9050
1.9050
0.6350
0.6350
6.9850
DETAIL A
Øb (144 PLACES)
A
DETAIL B
PACKAGE SIDE VIEW
Z
MX YZddd
MZeee
A2
DETAIL B
SUBSTRATE
A1
b1
ccc Z
MOLD
CAP
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
4.81
0.50
4.31
0.60
0.60
0.36
3.95
NOM
5.01
0.60
4.41
0.75
0.63
16.00
16.00
1.27
13.97
13.97
0.41
4.00
MAX
5.21
0.70
4.51
0.90
0.66
0.46
4.05
0.15
0.10
0.20
0.30
0.15
NOTES
DIMENSIONS
TOTAL NUMBER OF BALLS: 144
// bbb Z
Z
H2
H1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE
BALL DESIGNATION PER JESD MS-028 AND JEP95
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
7
SEE NOTES
LTM463OA 37
LTM4630A
37
4630afb
For more information www.linear.com/LTM4630A
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/16 Added BGA package 2, 34
B 01/18 Changed VIN(MAX) from 15V to 18V. Added date code information.
Changed VIN Absolute Maximum Rating from 16V to 20V.
Changed VOUT(MAX) from 5.3V to 8V.
Updated Efficiency vs Output Current graph.
Updated Table 1.
Updated thermal images.
Updated text to match updated efficiency and thermal data.
Added Fibure 17.
Added Figure 32 and Figure 33.
Updated Power Loss curves.
Updated Derating curves.
1, 3
2
1, 3
5
11
22
21, 23
27
29
27
27, 28, 29
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM463OA mm Puwer Search mpm v”, (Mm) v vm Wax) Output VN v w 38 SEGLc‘ES
LTM4630A
38
4630afb
For more information www.linear.com/LTM4630A
LT 0118 REV B • PRINTED IN USA
ANALOG DEVICES, INC. 2015
www.linear.com/LTM4630A
RELATED PARTS
DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design:
Selector Guides
Demo Boards and Gerber Files
Free Simulation Tools
Manufacturing:
Quick Start Guide
PCB Design, Assembly and Manufacturing Guidelines
Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
PART NUMBER DESCRIPTION COMMENTS
LTM4620A Lower Current of the LTM4630A, Dual 13A or Single 26A Pin Compatible with LTM4630A, 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V,
15mm × 15mm × 4.41mm (BGA) and, 15mm × 15mm × 5.01mm (BGA)
LTM4620 Lower VOUT of the LTM4620, Dual 13A or Single 26A,
VOUT ≤ 2.5V
Pin Compatible with LTM4630A, 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V,
15mm × 15mm × 4.41mm(BGA), 15mm × 15mm × 5.01mm (BGA)
LTM4630 Lower VOUT of the LTM4630A, VOUT ≤ 1.8V Pin Compatible with LTM4630A; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V,
16mm × 16mm × 4.41mm (LGA), 16mm × 16mm × 5.01mm (BGA)
LTM4630-1 External Compensation of the LTM4630 with ±0.8% (-1A)
and ±1.5% DC VOUT Accuracy
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm (LGA),
16mm × 16mm × 5.01mm (BGA)
LTM4650 Higher Current of the LTM4630, Dual 25A or Single 50A Pin Compatible with LTM4630A; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V,
16mm × 16mm × 5.01mm (BGA)
LTM4650-1 External Compensation of the LTM4650 with ±0.8% (-1A)
and ±1.5% DC VOUT Accuracy
4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm (LGA),
16mm × 16mm × 5.01mm (BGA)
LTM4631 Ultrathin, Lower Current of the LTM4630, Dual 10A or
Single 20A, 1.91mm Package Height
Pin Compatible with LTM4630A, 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V,
16mm × 16mm × 1.91mm (LGA)
LTM4636 Single 40A µModule Regulator with Excellent Thermal
Performance
4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.07mm BGA
Package
LTM4647 Single 30A µModule Regulator in Small Package 4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 9mm × 15mm × 5.01mm BGA
Package
LTM4677 LTM4630 with PSM Function 4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA)
LTM4643 Ultrathin, Quad 3A µModule Regulator 4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 3.3V, 9mm × 15mm × 1.82mm (LGA)
LTM4644 Quad 4A µModule Regulator 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 9mm × 15mm × 5.01mm (BGA)
LTM4639 Lower VIN (2.375V ≤ VIN ≤ 7V), 20A 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.92mm (BGA)

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