SP3012 Series Datasheet by Littelfuse Inc.

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© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Description
Applications
The SP3012 Series integrates either 3, 4 or 6 channels of
ultra low capacitance rail-to-rail diodes and an additional
zener diode to provide protection for electronic equipment
that may experience destructive electrostatic discharges
(ESD). These robust devices can safely absorb repetitive
ESD strikes above the maximum level specified in the IEC
61000-4-2 international standard (±8kV contact discharge)
without performance degradation.
The extremely low loading capacitance also makes it ideal
for protecting high speed signal lines such as USB3.0,
HDMI, USB2.0, and eSATA.
Features
ESD, IEC 61000-4-2,
±12kV contact, ±25kV air
EFT, IEC 61000-4-4, 40A
(tP=5/50ns)
Lightning, IEC 61000-
4-5 2nd edition, 4A
(tP=8/20μs)
Low capacitance of 0.5pF
(TYP) per I/O
Low leakage current of
1.5μA (MAX) at 5V
Small form factor μDFN
(JEDEC MO-229) and
SOT23-6 (JEDEC MO-
178AB) packages provide
flow through routing to
simplify PCB layout
AEC-Q101 Qaulified
(μDFN10 and μDFN14)
RoHS compliant and lead-
free
• LCD/PDP TVs
• External Storages
• DVD/Blu-ray Players
• Desktops
• MP3/PMP
• Set Top Boxes
• Smartphones
• Ultrabooks/Notebooks
• Digital Cameras
• Automotive Electronics
Pinout
Functional Block Diagram
Life Support Note:
Not Intended for Use in Life Support or Life Saving Applications
The products shown herein are not designed for use in life sustaining or life saving
applications unless otherwise expressly indicated.
Application Example for USB3.0
SP3012 Series 0.5pF Diode Array for USB3.0 RoHS
Pb
GREEN
PIN 14
PIN 13
PIN 8
PIN 10
PIN 9
PIN 11
PIN 12
PIN 1
PIN 2
PIN 4
PIN 5
GND (PIN 3, 8)
SP3012-04UTG
GND (PIN 2)
PIN 1
PIN 4
PIN 5
SP3012-03UTG SP3012-06UTG
PIN 1
PIN 3
PIN 4
PIN 6
GND (PIN 2)
SP3012-04HTG
8
7
14
1
SP3012-06UTG (AEC-Q101 Qualified)
SP3012-03UTG
6 7 8 9 10
SP3012-04UTG (AEC-Q101 Qualified)
SP3012-04HTG
3 2 1
4 5 6
5 4 3 2 1
1 2 3
6 5 4
*Pins 6, 7, 9, 10 are not internally connected
but should be connected to the trace.
*Pins 1, 2, 3, 4, 5, 6, 7 are not internally connected
but should be connected to the opposite pin
with the PCB trace.
Additional Information
Datasheet Resources Samples
Signal GND
USB ControllerUSB Port
V
BUS
SSTX+
SSTX-
SSRX+
SSRX-
GND
D+
D-
SP3012-06UTG
IC
/ \
© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
SP3012
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Absolute Maximum Ratings
Symbol Parameter Value Units
IPP Peak Current (tp=8/20μs) 4.0 A
TOP Operating Temperature -40 to 125 °C
TSTOR Storage Temperature -55 to 150 °C
Electrical Characteristics (TOP=25ºC)
Parameter Symbol Test Conditions Min Typ Max Units
Reverse Standoff Voltage VRWM IR ≤ 1µA 5.0 V
Reverse Leakage Current ILEAK VR=5V, Any I/O to GND 1. 5 µA
Clamp Voltage1VC
IPP=1A, tp=8/20µs, Fwd 6.6 7. 9 V
IPP=2A, tp=8/20µs, Fwd 7. 0 8.4 V
Dynamic Resistance RDYN (VC2 - VC1) / (IPP2 - IPP1) 0.4 Ω
ESD Withstand Voltage1VESD
IEC61000-4-2 (Contact) ±12 kV
IEC61000-4-2 (Air) ±25 kV
Diode Capacitance1CI/O-GND Reverse Bias=0V, f=1 MHz 0.5 0.65 pF
Diode Capacitance1CI/O-/O Reverse Bias=0V, f=1 MHz 0.3 0.4 pF
Note: 1 Parameter is guaranteed by design and/or device characterization.
Insertion Loss (S21) I/O to GNDCapacitance vs. Bias Voltage
Clamping Voltage vs. IPP
Bias Voltage (V)
Capacitance (pF)
0.0
0.2
0.4
0.01.0 2.03.0 4.05.0
0.6
0.8
1.0
0.0
2.0
4.0
6.0
8.0
10.0
1234
Clamp Voltage (V)
Current (A)
-30
-18
-15
-12
-9
-3
0
Attenuation (dB)
-6
-21
-24
-27
100 1000
Frequency (MHz)
0 1 2 3 4 5 6 7 8 9 10 11
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TLP Voltage (V)
TLP Current (A)
Transmission Line Pulsing(TLP) Plot
© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Time
Temperature
TP
TL
TS(max)
TS(min)
25
tP
tL
tS
time to peak temperature
Preheat
P
rehea
t
Ramp-up
R
amp-up
Ramp-down
R
amp-d
o
Critical Zone
TL to TP
C
ritical Zon
e
T
to
T
P
Reflow Condition Pb – Free assembly
Pre Heat
- Temperature Min (Ts(min))150°C
- Temperature Max (Ts(max))200°C
- Time (min to max) (ts)60 – 180 secs
Average ramp up rate (Liquidus) Temp
(TL) to peak 3°C/second max
TS(max) to TL - Ramp-up Rate 3°C/second max
Reflow - Temperature (TL) (Liquidus) 217°C
- Temperature (tL)60 – 150 seconds
Peak Temperature (TP)260+0/-5 °C
Time within 5°C of actual peak
Temperature (tp)20 – 40 seconds
Ramp-down Rate 6°C/second max
Time 25°C to peak Temperature (TP)8 minutes Max.
Do not exceed 260°C
Soldering Parameters
Part Numbering System
Part Marking System
SP 3012 xx T G
Series
Package
T= Tape & Reel
G= Green
Number of
Channels
TVS Diode Arrays
(SPA
®
Diodes)
03 = 3 channel
04 = 4 channel
06 = 6 channel SOT23-6 (3.0x1.75mm)
x
µDFN-10 (2.5x1.0mm)
µDFN-14 (3.5x1.35mm)
µDFN-6 (1.6x1.6mm)
U=
H=
V**
Product Series
V = SP3012
Assembly Site
Number of
Channels
3 = 3 channel
4 = 4 channel
6 = 6 channel
Part Number Package Marking Min. Order Qty.
SP3012-03UTG µDFN-6 V*33000
SP3012-04UTG µDFN-10 V*43000
SP3012-06UTG µDFN-14 V*63000
SP3012-04HTG SOT23-6 V*43000
Ordering Information
Pulse Waveform
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
110%
0.05.0 10.0 15.0 20.0 25.0 30.0
Time (μs)
Percent of I
PP
Product Characteristics
Lead Plating Pre-Plated Frame (µDFN)
Matte Tin (SOT23)
Lead Material Copper Alloy
Lead Coplanarity 0.0004 inches (0.102mm)
Substitute Material Silicon
Body Material Molded Epoxy
Flammability UL 94 V-0
Notes :
1. All dimensions are in millimeters
2. Dimensions include solder plating.
3. Dimensions are exclusive of mold flash & metal burr.
4. Blo is facing up for mold and facing down for trim/form, i.e. reverse trim/form.
5. Package surface matte finish VDI 11-13.
T a} WWW a: —0— d on the landing pattern
© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Application Information
Adding external ESD protection to a high-speed data port is
not trivial for a variety of reasons.
1. ESD protection devices will add parasitic capacitance
to each data line from line to GND and line to line causing
impedance mismatches between the differential pairs. This
ultimately affects the signal eye-diagram and whether or
not the transceiver can distinguish a “1” from a “0”.
2. ESD devices should be placed as close as possible
to the port being protected to maximize their effect (i.e.
clamping capability) and minimize the effect that PCB trace
inductance can have during an ESD transient. Depending
on the package size and pinout this could be challenging
and the bigger the package, the larger the land pattern
must be, which adds more parasitic capacitance.
3. Stub traces can add another element of discontinuity
adversely affecting signal integrity so ESD protection is
best employed when it’s overlaid” on the data lines or
when the signals can simply pass underneath the device.
Taking all of this into account Littelfuse developed
the SP3012 Series which was designed specifically
for protection of high-speed data ports such as HDMI
1.3/1.4 and USB 3.0. They present less than 0.5pF from
line to GND and only 0.3pF from line to line minimizing
impedance mismatch between the differential pairs.
Furthermore, the SP3012 is rated up to ±12kV (contact
discharge) which far exceeds the maximum requirement of
the IEC 61000-4-2 standard.
There are two options available (4 channel and 6 channel)
and both are housed in leadless µDFN packages so the
data lines can pass directly underneath the device to
reduce discontinuities and maintain signal integrity.
J1
U1
Figure 1 shows the layout used for the SP3012-06UTG in a
USB 3.0 application. The traces routed toward the top are
the two legacy USB 2.0 lines (D+/D-) that run at the slower
speed of 480Mbps and therefore are not as critical as the
5Gbps Super-Speed traces.
Figure 1: PCB Layout of the SP3012-06UTG for USB 3.0
Figure 2: USB 3.0 Eye Diagram with the SP3012-06UTG
Figure 3: USB 3.0 Eye Diagram with the SP3012-04UTG
Figure 2 shows the USB 3.0 eye diagram that resulted
from the PCB layout above with the SP3012-06UTG
soldered on the landing pattern.
Base: 27.0000 ns Scale:33.0 ps/div
500
0
-500
Wfrms:500
Using a similar layout as above, Figure 3 shows the eye
diagram that resulted using the SP3012-04UTG to protect
the Super-Speed data lines and the SP3003-02UTG to
protect the legacy data pair.
Base: 27.0000 ns Scale:33.0 ps/div
500
0
-500
Wfrms:850
Signal Integrity of High-Speed Data Interfaces
USB 3.0 Eye Diagram Data
© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Embossed Carrier Tape & Reel Specification — μDFN-6
K0
A0
B0
P2
D1 P0
t
FE
W
D
Symbol Millimetres Inches
Min Max Min Max
E1.65 1.85 0.06 0.07
F3.45 3.55 0.14 0.14
D1 1. 0 0 1.25 0.04 0.05
D1.50 MIN 0.06 MIN
P0 3.90 4.10 0.15 0.16
10P0 40.0+/- 0.20 1.57+/-0.01
W7.90 8.30 0.31 0.33
P2 1.95 2.05 0.08 0.08
A0 1.78 1.88 0.07 0.07
B0 1.78 1.88 0.07 0.07
K0 0.84 0.94 0.03 0.04
t0.25 TYP 0.01 TYP
Package Dimensions — μDFN-6
Package μDFN-6 (1.6x1.6x0.5mm)
JEDEC MO-229
Symbol Millimeters Inches
Min Max Min Max
A0.45 0.55 0.018 0.022
A1 0.00 0.05 0.000 0.002
A3 0.152Ref 0.006 Ref
b0.20 0.30 0.008 0.012
D1.55 1.65 0.061 0.065
D2 1.05 1.30 0.042 0.052
E 1.50 1.70 0.060 0.067
E2 0.40 0.65 0.016 0.026
e0.50 BSC 0.020BSC
L0.164 0.316 0.006 0.012
D
E
B
123
654
Top View
Pin 1 Index Area
A
A
1
2
3
54 6
L
Pin 1 chamfer
0.10 x 45
0.05 C
Bottom View
0.05 C
0.05 C
b
A1 A3
C
Seating plane
Side View
0.10 CA
M
B
0.05 C
M
D2
E2
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© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Package Dimensions— µDFN-10 (2.5x1.0x0.5mm)
Package µDFN-10 (2.5x1.0x0.5mm)
JEDEC MO-229
Symbol Millimeters Inches
Min Nom Max Min Nom Max
A0.48 0.515 0.55 0.019 0.020 0.021
A1 0.00 -- 0.05 0.000 0.022
A3 0.125 Ref 0.005 Ref
b0.15 0.20 0.25 0.006 0.008 0.012
b1 0.35 0.40 0.45 0.014 0.016 0.018
D2.40 2.50 2.60 0.094 0.098 0.102
E0.90 1. 0 0 1. 10 0.035 0.039 0.043
e0.50 BSC 0.020 BSC
L0.30 0.365 0.43 0.012 0.014 0.016
D
E
B
Top View
A
A
Bottom View
0.05 C
b
A1
b1
A3
C
Seating
Plane
Side View
0.10 CA
M
B
0.05 C
M
L
e
2xR0.075mm (7x)
R0.125
0.05 C
X1
X
P
P1
Z (C) G
Y
(Y1)
Soldering Pad Layout
Recomended
Soldering Pad Layout
Dimensions
Inch Millimeter
C(0.034) (0.875)
G0.008 0.20
P0.020 0.50
P1 0.039 1. 0 0
X0.008 0.20
X1 0.016 0.40
Y0.027 0.675
Y1 (0.061) (1.55)
Z0.061 1.55
X1
X
P
P1
Z (C) G
Y
(Y1)
Soldering Pad Layout
Alternative
Embossed Carrier Tape & Reel Specification— µDFN-10
Package µDFN-10 (2.5x1.0x0.5mm)
Symbol Millimeters
A0 1.30 +/- 0.10
B0 2.83 +/- 0.10
D0 Ø 1.50 + 0.10
D1 Ø 1.00 + 0.25
E1.75 +/- 0.10
F3.50 +/- 0.05
K0 0.65 +/- 0.10
P0 4.00 +/- 0.10
P1 4.00 +/- 0.10
P2 2.00 +/- 0.05
T0.254 +/- 0.02
W8.00 + 0.30 /- 0.10
K0
A0
B0
P2
P1 P0
T
FE
W
D0
D1
5º Max
5º Max
User Feeding Direction
Pin 1 Location
D
E
B
Top View
A
A
Bottom View
0.05 C
b
A1
b1
A3
C
Seating
Plane
Side View
0.10 CA
M
B
0.05 C
M
L
e
2xR0.075mm (7x)
R0.125
0.05 C
X1
X
P
P1
Z (C) G
Y
(Y1)
Soldering Pad Layout
Recomended
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© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Package Dimensions — µDFN-14 (3.5x1.35x0.5mm)
µDFN-14 (3.5x1.35x0.5mm)
JEDEC MO-229
Symbol Millimeters Inches
Min Nom Max Min Nom Max
A0.45 0.50 0.55 0.018 0.020 0.022
A1 0.00 0.02 0.05 0.000 0.001 0.002
A2 0.203 Ref 0.008 Ref
b0.15 0.20 0.25 0.006 0.008 0.012
D3.40 3.50 3.60 0.134 0.138 0.142
D2 - - - - - -
E1.25 1.35 1.45 0.050 0.054 0.058
E1 - - - - - -
e0.500 BSC 0.020 BSC
L0.25 0.30 0.35 0.010 0.012 0.014
D
E
B
Top View
A
Bottom View
Side View
PIN 1 Index Area 1 2 3 4
A
Cb
A1 A2
Seating
Plane
Pin 1 Identification
Chamfer 0.10X45º
Notes:
1. Dimension and tolerancing comform to ASME Y14.5M-1994.
2. Controlling dimensions: Millimeter. Converted Inch dimensions are not necessarily
exact.
Soldering Pad Layout
Recomended
Symbol Millimeter Inches
Soldering Pad Layout Dimensions
Symbol Millimeters Inches
Nom Nom
D3.30 0.1299
E1.65 0.0571
b0.30 0.0118
L0.50 0.0197
e0.50 typ 0.020 typ
s0.20 0.0078
s1 0.65 0.0256
Embossed Carrier Tape & Reel Specification — µDFN-14
Symbol Millimeters
A0 1.58 +/- 0.10
B0 3.73 +/- 0.10
D0 Ø 1.50 + 0.10
D1 Ø 0.60 +/- 0.05
E1.75 +/- 0.10
F5.50 +/- 0.05
K0 0.68 + 0.12/ -0.10
P0 2.00 +/- 0.05
P1 4.00 +/- 0.10
P2 4.00 +/- 0.10
T0.28 +0.02/ -0.05
W12.00 + 0.30 /- 0.10
P0 D0 E
F
P1
P2
D1
W
T
B0
K0
A0
User Feeding Direction
Pin 1 Location
*1” i, % T ‘ 5w | + ¢ A | ¢ a 7. , ’{F Lm J j
© 2017 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 02/23/17
TVS Diode Arrays (SPA® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Embossed Carrier Tape & Reel Specification — SOT23-6
8mm TAPE AND REEL
GENERAL INFORMATION
1. 3000 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
2.0mm
4.0mm
C
L
1.75mm
1.5mm
DIA. HOLE
8mm
4.0mm
8.4mm
180mm
14.4mm
13mm
60mm
ACCESS HOLE
COVER TAPE
USER DIRECTION OF FEED PIN 1
SOT-23 (8mm POCKET PITCH)
Package Dimensions — SOT23-6
Package SOT23
Pins 6
JEDEC MO-178AB
Millimeters Inches Notes
Min Max Min Max
A0.900 1.450 0.035 0.057 -
A1 0.000 0.150 0.000 0.006 -
A2 0.900 1.300 0.035 0.051 -
b0.350 0.500 0.0138 0.0196 -
C0.080 0.220 0.0031 0.009 -
D2.800 3.000 0.11 0.118 3
E2.600 3.000 0.102 0.118 -
E1 1.500 1.750 0.06 0.069 3
e0.95 Ref 0.0374 ref -
e1 1.9 Ref 0.0748 Ref -
L0.30 0.600 0.012 0.023 4,5
N6 6 6
a0º 8º 0º 8º -
M2.590 0.102 -
O0.690 .027 TYP -
P0.990 .039 TYP -
R0.950 0.038 -
O
P
R
M
Recommended Solder Pad Layout
Notes:
1. Dimensioning and tolerancing Per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 (1992).
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.
4. Foot length L measured at reference to seating plane.
5. “L” is the length of flat foot surface for soldering to substrate.
6. “N” is the number of terminal positions.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
Disclaimer Notice - Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and
test each product selected for their own applications. Littelfuse products are not designed for, and may not be used in, all applications.
Read complete Disclaimer Notice at www.littelfuse.com/disclaimer-electronics.

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