LT3745-1 Datasheet by Analog Devices Inc.

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L I n LT3745_1 V :3. $1,? __ __ E_ L7 LJUEAD
LT3745-1
1
37451f
TYPICAL APPLICATION
DESCRIPTION
16-Channel 50mA LED
Driver with Buck Controller
The LT
®
3745-1 integrates a 16-channel LED driver with a
55V buck controller. The LED driver lights up to 75mA/36V
of LEDs in series per channel, and the buck controller gen-
erates an adaptive bus voltage supplying the parallel LED
strings. Each channel has individual 6-bit dot correction
current adjustment and 12-bit grayscale PWM dimming.
Both dot correction and grayscale are accessible via a serial
data interface in LVDS logic. A ±4% LED current match-
ing and a 0.5µs minimum LED on-time can be achieved
at 50mA per channel.
The LT3745-1 performs full diagnostic and protection
against open/short LED and overtemperature fault. The
fault status is sent back through the serial data interface.
The 30MHz fully-buffered, cascadable LVDS serial data
interface makes the chip extremely suitable for large screen
LCD dynamic backlighting and mono-, multi-, full-color
LED displays. The LT3745 uses a TTL/CMOS serial data
interface instead of LVDS.
16-Channel LED Driver, 1MHz Buck, 10 LEDs, 25mA to 75mA per Channel, 500Hz 12-Bit Dimming
FEATURES
APPLICATIONS
n 6V to 55V Power Input Voltage Range
n 16 Independent LED Outputs Up to 75mA/36V
n ±4% LED Current Matching at 50mA (Typ ±1%)
n 6-Bit Dot Correction Current Adjustment
n 12-Bit Grayscale PWM Dimming
n 0.5µs Minimum LED On-Time
n Adaptive LED Bus Voltage for High Efficiency
n Cascadable 30MHz LVDS Serial Data Interface
n Full Diagnostic and Protection: Individual Open/Short
LED and Overtemperature Fault
n 40-Lead 6mm × 6mm QFN Package
n Large Screen Display LED Backlighting
n Mono-, Multi-, Full-Color LED Displays
n LED Billboards and Signboards
L, LT, LT C, LTM , Linear Technology and the Linear logo are registered trademarks and
True Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 8058810
LVDS
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EN/UVLO
SYNC
RT
SS
VCC
ISET
TSET
SCKI+
SCKI
SDI+
SDI
LDI
SCKO+
SCKO
SDO+
SDO
LED13
LED14
LED15
LED00
LED01
LED02
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LT3745-1
100k
V
IN
42V TO 55V
EN
VCC
3V TO 3.6V
VIN CAP
0.47µF
GATE
GND
FB
ISP
ISN
4.7µF
267k
10k
47µF
×2
47µH 25mΩ
PWMCK+
PWMCK
LVDS
2.048MHz
LVDS CLOCK
37451 TA01
10µF
46.4k
10nF
60.4k
32.4k
LT3 745— 1 TOP V‘EW xi“) @191 EU ‘35) E5) ‘3‘) E31 ‘32) ‘3‘) m} WW WW RE (‘7‘ RE (@601 L7 LINE/“2 v toerch
LT3745-1
2
37451f
ABSOLUTE MAXIMUM RATINGS
VIN .......................................................................... 57V
CAP ......................................................... VIN – 8V to VIN
GATE ..............................................................CAP to VIN
LED00 to LED15, ISP, ISN .........................................40V
ISP ................................................. ISN – 1V to ISN + 1V
FB, RT, TSET, ISET ....................................................... 2V
VCC ...............................................................0.3V to 4V
SCKI+, SCKI, SCKO+, SCKO, SDI+, SDI,
SDO+, SDO, LDI, PWMCK+, PWMCK, SYNC,
SS, EN/UVLO ............................................. 0.3V to VCC
Operating Junction Temperature Range
(Notes 2, 3)
LT3745E-1 .........................................40°C to 125°C
LT3745I-1 ..........................................40°C to 125°C
Storage Temperature Range ..................6C to 125°C
(Note 1)
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply
VIN VIN Operating Voltage l6 55 V
IVIN VIN Supply Current VEN/UVLO = 0V
No Switching 0.2
0.4 2
0.55 µA
mA
VCC VCC Operating Voltage l3 3.6 V
IVCC VCC Supply Current (Note 4) VEN/UVLO = 0V
LED Channel Off, 30MHz Data Off
LED Channel On, 30MHz Data Off
LED Channel On, 30MHz Data On
0.25
11
16
19
mA
mA
mA
mA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V,
RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3745EUJ-1#PBF LT3745EUJ-1#TRPBF LT3745UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LT3745IUJ-1#PBF LT3745IUJ-1#TRPBF LT3745UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PIN CONFIGURATION
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
EN/UVLO
LED07
LED06
LED05
LED04
LED03
LED02
LED01
LED00
SCKI
SYNC
LED08
LED09
LED10
LED11
LED12
LED13
LED14
LED15
SCKO
ISET
TSET
VIN
GATE
CAP
ISP
ISN
FB
SS
RT
SCKI+
SDI
SDI+
LDI
VCC
PWMCK+
PWMCK
SDO+
SDO
SCKO+
21
30
10
1
TJMAX = 125°C, θJA = 34°C/W, θJC = 2.5°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
LT3 745— 1 L7 LJUW 3
LT3745-1
3
37451f
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V,
RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Undervoltage Lockout (UVLO)
VCC UVLO Threshold VCC Rising
VCC Falling 2.76
2.58 2.86
2.68 2.96
2.78 V
V
EN/UVLO Shutdown Threshold
UVLO Threshold IVCC <1mA
VEN/UVLO Rising
VEN/UVLO Falling
0.35
1.26
1.18
1.30
1.22
1.34
1.26
V
V
V
IEN/UVLO EN/UVLO Bias Current VEN/UVLO = VCC = 3.3V 0.1 1 µA
(VIN – VCAP) UVLO Threshold (VIN – VCAP) Rising
(VIN – VCAP) Falling 4.6
4.2 4.9
4.5 5.2
4.8 V
V
Soft-Start (SS)
ISS Soft-Start Charge Current VSS = 1V –16 –12 –8 µA
Soft-Start Discharge Current VSS = VCC, VEN/UVLO = 1V 330 µA
VSS(TH) Soft-Start Reset Threshold 0.35 V
Oscillator
VRT RT Pin Voltage 1.186 1.205 1.224 V
IRT RT Pin Current Limit VRT = 0V –80 µA
fOSC Oscillator Frequency RT = 280k
RT = 105k
RT = 46.4k
184
460
935
204
510
1035
224
560
1135
kHz
kHz
kHz
fSYNC Sync Frequency Range (Note 5) RT = 348k 200 1000 kHz
SYNC LOGIC
High Level Voltage
Low Level Voltage
VCC = 3V to 3.6V
2.4
0
VCC
0.6
V
V
Error Amplifiers and Loop Dynamics
VFB FB Regulation Voltage VISN = 5V l1.186 1.210 1.234 V
IFB FB Input Bias Current VISN = 5V, VFB Regulated –120 nA
LED Regulation Voltage VISN = 5V, VFB = 1V 0.6 0.7 0.8 V
tOFF(MIN) Minimum GATE Off-Time VISP = VISN = 5V, VFB = 1V 120 ns
tON(MIN) Minimum GATE On-Time (VISPVISN) = 60mV, VISN = 5V, VFB = 1V 200 ns
Current Sense Amplifier
ISP/ISN Pin Common Mode VISP = VISN l0 36 V
VIN to ISN Dropout Voltage (VIN – VISN) VISP = VISN, VFB = 1V l1.7 2.1 V
Current Limit Sense Threshold (VISP – VISN) VFB = 1V 30 44 58 mV
IISP ISP Input Bias Current –24 µA
IISN ISN Input Bias Current –48 µA
Gate Driver
VBIAS CAP Bias Voltage (VIN – VCAP) 7V < VIN < 55V 6.4 6.8 7.1 V
ICAP CAP Bias Current Limit (VIN – VCAP) = VBIAS – 0.5V 22 mA
GATE High Level (VIN – VGATE) IGATE = –100mA 0.4 V
GATE Low Level (VGATE – VCAP) IGATE = 100mA 0.3 V
GATE Rise Time CGATE = 3.3nF to VIN 30 ns
GATE Fall Time CGATE = 3.3nF to VIN 30 ns
LT3 745— 1 4 L7LJ1W
LT3745-1
4
37451f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LED Driver
VISET Trimmed ISET Pin Voltage l1.181 1.205 1.229 V
LEDxx Operating Voltage VIN = 48V, VISP = VISN = VLEDxx l36 V
LEDxx Leakage Current LED Channel Off, VIN = 48V,
VISP = VISN = 36V, VLEDxx = 24V 0.2 µA
ILED LED Constant Sink Current VISP = VISN = 5V, VLEDxx = 1V
REGDC = 0x00
REGDC = 0x20
REGDC = 0x3F
l
l
l
23.3
47.5
70
25.3
50.5
74
27.3
53.5
78
mA
mA
mA
ILEDC Current Mismatch Between Channels VISP = VISN = 5V, VLEDxx = 1V,
REGDC = 0x20 (Note 6)
l±1 ±4 %
ILEDD Current Mismatch Between Devices VISP = VISN = 5V, VLEDxx = 1V,
REGDC = 0x20 (Note 7)
l±1 ±3 %
ILINE LED Current Line Regulation VISP = VISN = 5V, VLEDxx = 1V,
REGDC = 0x20, VCC = 3V to 3.6V (Note 8) 0.1 0.2 %/V
ILOAD LED Current Load Regulation VISP = VISN = 5V, REGDC = 0x20,
VLEDxx = 1V to 3V (Note 9) 0.1 0.2 %/V
VOPEN Open LED Threshold VISP = VISN = 5V, VLEDxx Falling 0.35 V
VSHT Short LED Threshold VISP = VISN = 5V, VLEDxx Rising 3.7 3.9 4.1 V
tLEDON Minimum LED On-Time VISP = VISN = 5V, REGGS = 0x001 0.5 µs
Thermal Protection
ITSET TSET Output Current VTSET = 1V l19.0 19.8 20.6 µA
TSET Over Temperature Threshold TA = 25°C 510 mV
Serial Data Interface
VSIH
VSIL
Single-Ended Input (Note 10)
High Level Voltage
Low Level Voltage
VCC = 3V to 3.6V
2.4
0
VCC
0.6
V
V
ISI Single-Ended Input Current VCC = 3V to 3.6V, SI = VCC or GND –0.2 0.2 µA
VCM
VDTH
VDTL
Differential Input (Note 11)
Common Mode
High Threshold
Low Threshold
VCC = 3V to 3.6V
VID = 200mV
VCM = 1.2V
VCM = 1.2V
0.1
–100
50
–50
2.3
100
V
mV
mV
IDI Differential Input Current VCC = 3.6V; DI+, DI = 2.4V or 0V –0.2 0.2 µA
VOD Differential Output Voltage (Note 11) RL = 100Ω 230 330 430 mV
VOD VOD Magnitude Change Between
Complementary Outputs RL = 100Ω 1 10 mV
VOS Differential Output Offset Voltage RL = 100Ω 1.1 1.2 1.3 V
VOS VOS Magnitude Change Between
Complementary Outputs RL = 100Ω 1 10 mV
IOSD Differential Output Short-Circuit Current DO+ = 0V or DO = 0V –6 –8 mA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V,
RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
LT3 745— 1 L7 LJUW 5
LT3745-1
5
37451f
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3V to 3.6V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 5V,
VLEDxx = 1V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, CSCKO+/SCKO– = CSDO+/SDO– = 15pF, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCKI Data Shift Clock Frequency l30 MHz
fPWMCK PWMCK Clock Frequency l25 MHz
tWH-CKI
tWL-CKI
SCKI Pulse Duration SCKI = H (Figure 3)
SCKI = L (Figure 3)
l
l
16
16 ns
ns
tWH-PWM
tWL-PWM
PWMCK Pulse Duration PWMCK = H (Figure 4)
PWMCK = L (Figure 4)
l
l
20
20 ns
ns
tWH-LDI LDI Pulse Duration LDI = H (Figure 3) l20 ns
tSU-SDI SDI-SCKI Setup Time SDI – SCKI (Figure 3) l5 ns
tHD-SDI SCKI-SDI Hold Time SCKI – SDI (Figure 3) l5 ns
tSU-LDI SCKI-LDI Setup Time SCKI – LDI (Figure 3) l5 ns
tHD-LDI LDI-SCKI Hold Time LDI – SCKI (Figure 3) l15 ns
tPD-SCKSCKI-SCKO Propagation Delay (Rising) SCKI – SCKO (Figure 3) l33 50 ns
tPD-SCKSCKI-SCKO Propagation Delay (Falling) SCKI – SCKO (Figure 3) l33 50 ns
tPD-SCK SCK Duty Cycle Change tPD-SCK = tPD-SCK – tPD-SCK0 ns
tPD-SD SCKO-SDO Propagation Delay SCKO – SDO (Figure 3) l2 5 8 ns
tPD-PWM PWMCK-LED Propagation Delay PWMCK – ILED (Figure 4) 55 ns
tR-SO SCKO/SDO Rise Time CLOAD = 15pF, 10% to 90% 2.6 ns
tF-SO SCKO/SDO Fall Time CLOAD = 15pF, 90% to 10% 2.6 ns
Table 1. Test Parameter Equations
ILEDC(%) =IOUTmax(015) – IOUTmin(015)
2IOUTavg(015)
100
(1)
ILEDD(%) =IOUTavg(015) – IOUTcal
IOUTcal
100
(2)
IOUTcal =2500 1.205V
RISET
(3)
ILINE (% / V) =IOUTn VCC =3.6V – IOUTn VCC =3V
IOUTn VCC =3V 100
0.6V
(4)
ILOAD (% / V) =IOUTn VOUTn =3V – IOUTn VOUTn =1V
IOUTn VOUTn =1V 100
2V
(5)
VID =V(DI+)– V(DI)
(6)
VCM =V(DI+)+V(DI)
2
(7)
VOD =V(DO+)– V(DO)
(8)
VOS =V(DO+)+V(DO)
2
(9)
LT3 745— 1 6 L7LJ1‘JW
LT3745-1
6
37451f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3745E-1 is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3745I-1 is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: This IC includes thermal shutdown protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when thermal shutdown protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: The VCC supply current with LED channel on highly depends on
the LED current setting and LEDxx pin voltage; its test condition is
RISET = 60.4k, REGDC = 0x3F, REGGS = 0xFFF, VISP = VISN = 5V,
VLEDxx = 1V. The VCC supply current with serial data interface on highly
depends on VCC supply voltage, SCKI+/SCKI clock frequency,
SCKO+/SCKO, SDO+/SDO loading capacitance, and PWMCK+/PWMCK
clock frequency; its test condition is VCC = 3.3V, fSCKI+/SCKI– = 30MHz,
CSCKO+/SCKO– = CSDO+/SDO– = 15pF, fPWMCK+/PWMCK– = 409.6KHz.
ELECTRICAL CHARACTERISTICS
Note 5: The SYNC frequency must be higher than the RT programmed
oscillator frequency, and is suggested to be around 20% higher. Any SYNC
frequency higher than the suggested value may introduce sub-harmonic
oscillation in the converter due to insufficient slope compensation. See
Application Information section.
Note 6: The current mismatch between channels is calculated as
Equation1 in Table 1.
Note 7: The current mismatch between devices is calculated as
Equations2 and 3 in Table 1.
Note 8: The LED current line regulation is calculated as Equation 4 in
Table 1.
Note 9: The LED current load regulation is calculated as Equation 5 in
Table 1.
Note 10: The specifications of single-ended input SI apply to the LDI pin.
Note 11: The specifications of differential inputs DI+/DI apply to SCKI+/
SCKI, SDI+/SDI and PWMCK+/PWMCK; the specifications of differential
outputs DO+/DO apply to SCKO+/SCKO and SDO+/SDO. The parameters
VID, VCM, VOD and VOS are defined in Equations 6 to 9 and measured in the
Parameter Test Setup.
CL
RL
DO+
DO
37451 PT
CL
D
Parameter Test Setup
LT3745— 1 L7 HEW 7
LT3745-1
7
37451f
TYPICAL PERFORMANCE CHARACTERISTICS
200Hz 2-Level DC Dimming 200Hz 4-Level DC Dimming Adaptive LED Bus Voltage I
Adaptive LED Bus Voltage II Adaptive LED Bus Voltage III Adaptive LED Bus Voltage IV
100Hz 8:1 GS Dimming 100Hz 4096:1 GS Dimming 500Hz 4096:1 GS Dimming
TA = 25°C, unless otherwise noted.
CIRCUIT OF FIGURE 7:
DC15 = 0×20
GS15 = 0×200
VPWMCK
0.5V/DIV
VLED15
2V/DIV
VOUT
2V/DIV
ILED15
50mA/DIV
5ms/DIV 37451 G01
CIRCUIT OF FIGURE 7:
DC15 = 0×20
GS15 = 0×001
VPWMCK
0.5V/DIV
VLED15
2V/DIV
VOUT
2V/DIV
ILED15
50mA/DIV
500ns/DIV 37451 G02
CIRCUIT OF FIGURE 7:
DC15 = 0×20
GS15 = 0×001
VPWMCK
0.5V/DIV
VLED15
2V/DIV
VOUT
2V/DIV
ILED15
50mA/DIV
500ns/DIV 37451 G03
CIRCUIT OF FIGURE 7:
(a) EN = 1, GS15 = 0×FFF (c) EN = 1, DC15 = 0×00
(b) EN = 1, DC15 = 0×3F
VSCKI
0.5V/DIV
VLED15
2V/DIV
VOUT
2V/DIV
ILED15
50mA/DIV
1ms/DIV 37451 G04
(a) (b) (c) (a) (b) (c)
CIRCUIT OF FIGURE 7:
(a) EN = 0, GS15 = 0×FFF (c) EN = 1, DC15 = 0×00
(b) EN = 1, DC15 = 0×3F (d) EN = 1, DC15 = 0×20
VSCKI
0.5V/DIV
VLED15
2V/DIV
VOUT
2V/DIV
ILED15
50mA/DIV
0.5ms/DIV 37451 G05
(a) (b) (c) (d)
CIRCUIT OF FIGURE 7:
DC00-15 = 0×3F, GS00-15 = 0×FFF
IL
0.5A/DIV
VOUT
0.5V/DIV
2ms/DIV 37451 G06
CIRCUIT OF FIGURE 7:
DC00-15 = 0×20, GS00-15 = 0×800
IL
0.5A/DIV
VOUT
0.5V/DIV
2ms/DIV 37451 G07
CIRCUIT OF FIGURE 7:
DC00-15 = 0×3F, GS00-01 = 0×1FF, GS02-03 = 0×3FF,
GS04-05 = 0×5FF, GS06-07 = 0×7FF, GS08-09 = 0×9FF,
GS10-11 = 0×BFF, GS12-13 = 0×DFF, GS14-15 = 0×FFF
IL
0.5A/DIV
VOUT
0.5V/DIV
2ms/DIV 37451 G08
CIRCUIT OF FIGURE 7:
DC00-03 = 0×3F, GS00-03 = 0×3FF, DC04-07 = 0×2F,
GS04-07 = 0×7FF, DC08-11 = 0×1F, GS08-11 = 0×BFF,
DC12-15 = 0×0F, GS12-15 = 0×FFF
IL
0.5A/DIV
VOUT
0.5V/DIV
2ms/DIV 37451 G09
LT3 745— 1 um U 43 / 32 E T ; ’ f—*—— 500 ‘2 U ‘ 2 EU / / K // / / 3 / / A g a u / u _ / // > vw / / // / I 32 4 EU ‘ ‘UUU /‘ / a a t ? a > >2 > \ L0 / LE, /// \\ / /
LT3745-1
8
37451f
TYPICAL PERFORMANCE CHARACTERISTICS
IVCC vs VCC – Shutdown Mode
IVCC vs VCC – Channel Off,
Data Off
VCC UVLO Threshold
vs Temperature
EN/UVLO UVLO Threshold
vs Temperature
(VIN-VCAP) UVLO Threshold
vs Temperature Oscillator Frequency fOSC vs RT
Buck Efficiency Shutdown IVIN vs VIN Quiescent IVIN vs VIN
TA = 25°C, unless otherwise noted.
0
60
65
EFFICIENCY (%)
70
80
75
90
85
100
95
0.1 0.2 0.3
LOAD CURRENT (A)
0.4
37451 G10
0.5 0.6 0.7 0.8 0.9 1.0
48VIN, 4VOUT at 200kHz
24VIN, 12VOUT at 1MHz
12VIN, 4VOUT at 500kHz
0
0
I
VIN
(µA)
1
3
2
4
5
10 20
VIN (V) 37451 G11
30 40 50 60
T = 25°C
T = 125°C
T = –40°C
0
0.38
I
VIN
(mA)
0.39
0.41
0.40
0.42
0.43
10 20
VIN (V) 37451 G12
30 40 50 60
T = 25°C
T = 125°C
T = –40°C
VCC (V)
3.0
0
IVCC (µA)
100
200
300
400
500
3.1 3.2 3.3 3.4
37451 G13
3.5 3.6
T = 125°C
T = –40°C
T = 25°C
VCC(V)
3.0
10.0
I
VCC
(mA)
10.5
11.0
11.5
12.0
3.1 3.2 3.3 3.4
37451 G14
3.5 3.6
T = 125°C
T = –40°C
T = 25°C
–50
2.60
V
CC
(V)
2.75
2.70
2.65
2.80
2.85
2.90
–25 25 50 75 100 1250
JUNCTION TEMPERATURE (°C) 37451 G15
UVLO
UVLO+
–50
1.20
V
EN/UVLO
(V)
1.26
1.24
1.22
1.28
1.30
1.32
–25 25 50 75 100 1250
JUNCTION TEMPERATURE (°C) 37451 G16
UVLO
UVLO+
–50
4.40
V
IN
- V
CAP
(V)
4.60
4.50
4.70
4.80
4.90
–25 25 50 75 100 1250
JUNCTION TEMPERATURE (°C) 37451 G17
UVLO
UVLO+
20 60 100 180 220 260
0
f
OSC
(kHz)
400
200
600
800
1000
140 300
RT (kΩ) 37451 G18
LT3745— 1 072 520 ms \ a \ - 5 E » \\ > \\ 4 U U E \\ \\ T \\ /’_ V ‘V AP (V) L7 LJUW 25m ////
LT3745-1
9
37451f
TYPICAL PERFORMANCE CHARACTERISTICS
FB Regulation Voltage
vs Load Current
LED Regulation Voltage
vs Load Current
Soft-Start Charge Current ISS
vs Temperature Current Sense Threshold vs VISN
CAP Bias Voltage (VIN-VCAP)
vs VIN
CAP Bias Voltage (VIN-VCAP)
vs ICAP VISET Pin Voltage vs Temperature
Oscillator Frequency fOSC
vs Temperature
TA = 25°C, unless otherwise noted.
JUNCTION TEMPERATURE (°C)
–50
480
f
OSC
(kHz)
490
500
510
520
–25 0 25
37451 G19
50 75 100 125
LOAD CURRENT (mA)
0
1.204
V
FB
(V)
1.206
1.208
1.210
1.212
1.216
200 400 600 800
37451 G20
1000 1200
1.214
LOAD CURRENT (mA)
0
0.60
V
LED
(V)
0.62
0.64
0.66
0.68
0.72
200 400 600 800
37451 G21
1000 1200
0.70
–50
–11.0
I
SS
(µA)
–10.8
–10.6
–10.4
–10.0
–10.2
–25 025 50 75 100 125
JUNCTION TEMPERATURE (°C) 37451 G22 VISN (V)
0
35
V
ISP
– V
ISN
(mV)
40
45
50
55
60
10 20 30
37451 G23
40
T = 125°C
T = –40°C
T = 25°C
0
6.70
V
IN
-V
CAP
(V)
6.74
6.78
6.90
6.86
6.82
10 20 30 40 50 60
VIN (V) 37451 G24
T = 25°C
T = 125°C
T = –40°C
0
6.20
V
IN
-V
CAP
(V)
6.30
6.40
6.90
6.80
6.70
6.60
6.50
4 8 12 16 2420
ICAP (mA) 37451 G25
T = 25°C
T = 125°C
T = –40°C
–50
1.200
V
ISET
(V)
1.202
1.210
1.208
1.206
1.204
–25 025 50 75 100 125
JUNCTION TEMPERATURE (°C) 37451 G26
LT3 745— 1 5L7 \ E E E 30 A A 2 <5 \="" e="" §="" _=""> _ 700 60 ‘IO I D (mil) L7LJCUEN2
LT3745-1
10
37451f
TYPICAL PERFORMANCE CHARACTERISTICS
Short LED Threshold vs VISN TSET Current vs ISET Current
TSET Threshold vs Temperature
LED Current Derating
vs Temperature
LED Current vs Dot Correction
LED Current ILED
vs LED Voltage VLED
LED Current Variation ILED
vs Temperature
TA = 25°C, unless otherwise noted.
Nominal LED Current vs RISET
37451 G27
40
0
I
LED
(mA)
10
50
40
30
20
80 120 160 200 240 280 320
RISET (kΩ)
81
0
I
LED
(mA)
10
80
70
60
50
40
30
20
16
24 32 40 48 56 64
DOT CORRECTION +1 37451 G28
0
10
80
70
60
50
40
30
20
0
I
LED
(mA)
0.5 1.0 1.5 2.0 2.5 3.0
VLED (V) 37451 G29
DC = 0×3F
DC = 0×20
DC = 0×00
JUNCTION TEMPERATURE (°C)
–50
49.0
I
LED
(mA)
49.5
50.0
50.5
51.0
–25 0 25 50 75 100 125
37451 G30
0
0
V
LED
(V)
30
18
24
12
6
816 24 32 40
VISN (V) 37451 G31
0
0
I
TSET
(µA)
20
12
16
8
4
4 8 12 16 20
IISET (µA) 37451 G32
–50
350
450
400
VTSET (mV)
700
600
650
550
500
–25 025 50 12575 100
JUNCTION TEMPERATURE (°C)
37451 G33
80
0
10
I
LED
(mA)
60
40
50
30
20
85 90 95 100 120105 110 115
JUNCTION TEMPERATURE (°C) 37451 G34
OT = 0 OT = 1
LT3 745— 1 L7 LJUW 1 1
LT3745-1
11
37451f
PIN FUNCTIONS
EN/UVLO (Pin 1): Enable and Undervoltage Lockout
(UVLO) Pin. The pin can accept a digital input signal to
enable or disable the chip. Tie to 0.35V or lower to shut
down the chip or tie to 1.34V or higher for normal op-
eration. This pin can also be connected to VIN through a
resistor divider to program a power input UVLO threshold.
If both the enable and UVLO functions are not used, tie
this pin to VCC pin.
LED00 to LED15 (Pins 2 to 9, 22 to 29): LED Driver Output
Pins. Connect the cathodes of LED strings to these pins.
SCKI, SCKI+ (Pins 10, 11): Serial Interface LVDS Logic
Clock Input Pins.
SDI, SDI+ (Pins 12, 13): Serial Interface LVDS Logic
Data Input Pins.
LDI (Pin 14): Serial Interface TTL/CMOS Logic Latch Input
Pin. An asynchronous input signal at this pin latches the
serial data in the shift registers into the proper registers
and the status information is ready to shift out with the
coming clock pulses. See more details in the Operation
section.
VCC (Pin 15): Logic and Control Supply Pin. The pin powers
serial data interface and internal control circuitry. Must be
locally bypassed with a capacitor to ground.
PWMCK+, PWMCK (Pins 16, 17): Grayscale PWM
Dimming LVDS Logic Clock Input Pins. Individual PWM
dimming signal is generated by counting this clock pulse
from zero to the bits in its 12-bit grayscale PWM register.
SDO+, SDO (Pins 18, 19): Serial Interface LVDS Logic
Data Output Pins.
SCKO+, SCKO (Pins 20, 21): Serial Interface LVDS Logic
Clock Output Pins.
SYNC (Pin 30): Switching Frequency Synchronization Pin.
Synchronizes the internal oscillator frequency to an exter-
nal clock applied to the SYNC pin. The SYNC pin is TTL/
CMOS logic compatible. Tie to ground or VCC if not used.
RT (Pin 31): Timing Resistor Pin. Programs the switching
frequency from 200kHz to 1MHz. See Table 2 for the rec-
ommended RT values for common switching frequencies.
SS (Pin 32): Soft-Start Pin. Placing a capacitor here pro-
grams soft-start timing to limit inductor inrush current
during start-up. The soft-start cycle will not begin until
all the VCC, EN/UVLO, and (VIN-VCAP) voltages are higher
than their respective UVLO thresholds.
FB (Pin 33): Feedback Pin. The pin is regulated to the
internal bang-gap reference 1.210V during start-up and
precharging phases. Connect to a resistor divider from the
buck converter output to program the maximum LED bus
voltage. See more details in the Applications Information
section.
ISN (Pin 34): Negative Inductor Current Sense Pin. The
pin is connected to one terminal of the external inductor
current sensing resistor and the buck converter output
supplying parallel LED channels.
ISP (Pin 35): Positive Inductor Current Sense Pin. The pin
is connected to the inductor and the other terminal of the
external inductor current sensing resistor.
CAP (Pin 36): VIN Referenced Regulator Supply Capacitor
Pin. The pin holds the negative terminal of an internal VIN
referenced 6.8V linear regulator used to bias the gate driver
circuitry. Must be locally bypassed with a capacitor to VIN.
GATE (Pin 37): Gate Driver Pin. The pin drives an external
P-channel power MOSFET with a typical peak current of
1A. Connect this pin to the gate of the power MOSFET with
a short and wide PCB trace to minimize trace inductance.
VIN (Pin 38): Power Input Supply Pin. Must be locally
bypassed with a capacitor to ground.
TSET (Pin 39): Temperature Threshold Setting Pin. A
resistor to ground programs overtemperature threshold.
See more details in the Applications Information section.
ISET (Pin 40): Nominal LED Current Setting Pin. A resistor
to ground programs the nominal LED current for all the
channels. See more details in the Applications Informa-
tion section.
GND (Exposed Pad Pin 41): Ground Pin. Must be soldered
to a continuous copper ground plane to reduce die tem-
perature and to increase the power capability of the device.
LT3 745— 1 L7LJCUEN2 12
LT3745-1
12
37451f
BLOCK DIAGRAM
32
3534 3031
1
15
33
16
14
CSS
CVCC RFB2
RFB1
VCC VCC
SS
ISN RTISP SYNC
12µA
EN/UVLO
FB
PWMCK+
SDI+
SDI
17 PWMCK
LDI
OT
STATUS
INFO
(FAULT
LEDXX)
x
SCKI
PRECHG
VSS < 1V
(VIN-VCAP)
VIN
VIN
CIN
RS
M1
L
D1
GATE
CAP
6.8V
1.205V
ISET
TSET
VPTAT
IREF
OT
UV
1.210V +
REFERENCE BIAS
AND UVLO
RAMP OSC
S
R
Q
+
+
+
RT
DRIVER
GM1+
37
38
36
CCAP
COUT
V
OUT
PG
POR
GM2
0.7V LED00 LED01 LED15
EN
+ – . . .
C0
SHIFT
REGISTER
C1
192192
16X
16X
FS
FS
SDI
SCKO SDO
FS
EN
GS REGISTER
DC REGISTER
12-BIT PWM
DIMMING
CONSTANT CURRENT
SINK
6-BIT DOT
CORRECTION
OPEN/SHORT
LED
12 12 EN
6 6
FAULT LEDXX
PWMCK
IREF
LEDXX
GND
37451 BD
40
39
+
+
RISET
RTSET
S
R
Q
12
13
SCKI+
SCKI
10
11
20
21
SCKO+
SCKO
18
19
41
SDO+
SDO
L7 LJUW LT3 745— 1 13
LT3745-1
13
37451f
OPERATION
The LT3745-1 integrates a single constant-frequency
current-mode nonsynchronous buck controller with six-
teen linear current sinks. The buck controller generates
an adaptive output LED bus voltage to supply parallel
LED strings and the sixteen linear current sinks regulate
and modulate individual LED strings. Its operation is best
understood by referring to the Block Diagram.
Start-Up
The LT3745-1 enters shutdown mode when the EN/UVLO
pin is lower than 0.35V. Once the EN/UVLO pin is above
0.35V, the part starts to wake up internal bias currents,
generate various references, and charge the capacitor CCAP
towards 6.8V regulation voltage. This VIN referenced voltage
regulator (VIN – VCAP) will supply the internal gate driver
circuitry driving an external P-channel MOSFET in normal
operation. The LT3745-1 remains in undervoltage lockout
(UVLO) mode as long as any one of the EN/UVLO, VCC, and
(VIN VCAP) UVLO flags is high. Their UVLO thresholds
are typically 1.30V, 2.86V, and 4.9V, respectively. After all
the UVLO flags are cleared, the buck controller starts to
switch, and the soft-start SS pin is released and charged
by a 12µA current source, thereby smoothly ramping up
the inductor current and the output LED bus voltage.
Power-on-Reset (POR)
During start-up, an internal power-on-reset (POR) high
signal blocks the input signals to the serial data interface
and resets all the internal registers except the 194-bit shift
register. The 1-bit frame select (FS) register, 1-bit enable
LED channel (EN) register, individual 12-bit grayscale (GS)
registers, and individual 6-bit dot correction (DC) registers
are all reset to zero. Thus all the LED channels are turned off
initially with the default grayscale (0x000) and dot correc-
tion (0x00) setting. Once the part completes its soft-start
(i.e., the SS pin voltage is higher than 1V) and the output
LED bus voltage is power good (i.e., within 5% of its FB
programmed regulation level), the POR signal goes low
to allow the input signals to the serial data interface. Any
fault triggering the soft-start will generate another POR
high signal and reset internal registers again.
LVDS Serial Data Interface
The LT3745-1 has a 30MHz, fully-buffered, cascadable
LVDS (low voltage differential signals) serial data in-
terface. Due to the differential signal transmission and
the low voltage swing, LVDS delivers the benefits of low
noise generation, high noise rejection, and low power
consumption for high data rate signals. Therefore, the
LT3745-1 uses LVDS logic for SCKI+, SCKI, SDI+, SDI,
SCKO+, SCKO, and SDO+, SDO signals (high data rate
signals), and TTL/CMOS logic for LDI signal (low data rate
signal). In this data sheet, the differential signals SCKI+,
SCKI, SDI+, SDI, SCKO+, SCKO and SDO+, SDO are
abbreviated to SCKI, SDI, SCKO and SDO, respectively.
The LT3745-1 can be connected to microcontrollers,
digital signal processors (DSPs), or field programmable
gate arrays (FPGAs) in two different topologies shown
in Figure 1. In topology #1, the LDI signal needs global
routing while the SCKI, and SDI signals only need local
routing between chips. Each chip provides the SCKO sig-
nal along with the SDO signal to drive the next chip. The
skew inside the chip between the SCKI and SDI signals
is balanced internally. The skew outside the chip between
the SCKO and SDO signals can be easily balanced by
parallel routing these two pairs of signals between chips.
The SDI signal is received with the SCKI signal, and the
SDO signal is sent with the SCKO signal. In a low data
rate application with a small number of cascaded chips,
the topology#1 can be simplified to the topology #2 by
ignoring the SCKO outputs.
Figure 2 shows two serial data input SDI frames (GS frame
and DC frame) and one serial data output SDO frame (status
frame). All the frames have the same 194-bit in length and
are transmitted with the MSB first and the LSB last. The SDI
frames are sent with the SCKI signal and the SDO frame is
received with the SCKO signal. The C0 bit (frame select)
determines any SDI frame to be either a GS frame (C0 = 0)
or a DC frame (C0 = 1), and the C1 bit (EN) enables (C1 = 1)
or disables (C1 = 0) all the LED channels. The status frame
reads back the TSET pin resistor-programmable over-
temperature flag and individual open/short LED fault flags,
as well as the individual 6-bit DC setting.
LT3 745— 1 LT3745-1 LVDS Tnpnlngv #1
LT3745-1
14
37451f
OPERATION
Inside the part, there are one 194-bit shift register
SR[0:193], one 1-bit frame select (FS) register, one 1-bit
enable LED channel (EN) register, sixteen 12-bit grayscale
(GS) registers, sixteen 6-bit dot correction (DC) registers,
one 1-bit over temperature (OT) flag register, and sixteen
1-bit LED fault flag registers. The input of the 194-bit shift
register, i.e., the input of the first bit SR[0], is connected
to the SDI signal. The output of the 194-bit shift register,
i.e., the output of the last bit SR[193] is connected to the
SDO signal. The SCKI signal shifts the SDI frame (GS or DC
frame) in and the SCKO signal shift the SDO frame (status
frame) out of the 194-bit shift register with their rising
edges. The LDI high signal latches the SDI frame (GS or
DC frame) from the 194-bit shift register into correspond-
ing FS, EN, GS or DC registers, and loads the SDO frame
(status frame) from the OT and LED fault flag registers
to the 194-bit shift register at the same time. Therefore, a
daisy-chain type loop communication with simultaneous
writing and reading capability is implemented.
Figure 3 illustrates the timing relation among serial input
and serial output signals in more detail. One DC frame fol-
lowed by another GS frame is sent through the LDI, SCKI,
and SDI signals. At the same time, two status frames are
received through the SCKO and SDO signals. The rising
edges of the SCKI signal shift a frame of 194-bit data at
100Ω
100Ω
SCKO+
LDO
CONTROLLER CHIP 1
SCKO
SDO+
SDO
100Ω
SDI
SDI+
100Ω
SCKI
SCKI+
LDI
SCKO+
SCKO
SDO+
SDO
SCKI+
LDI
SCK-
SDI+
SDI
100Ω
100Ω
CHIP 2
LT3745-1 LVDS Topology #1
SCKO+
SCKO
SDO+
SDO
SCKI+
LDI
SCK-
SDI+
SDI
100Ω
100Ω
CHIP N
SCKO+
SCKO
SDO+
SDO
SCKI+
LDI
SCK-
SDI+
SDI
100Ω
SCKO+
LDO
CONTROLLER CHIP 1
SCKO
SDO+
SDO
100Ω
SDI
SDI+
100Ω
SCKI
SCKI+
LDI
SCKO+
SCKO
SDO+
SDO
SCKI+
LDI
SCK-
SDI+
SDI
100Ω
CHIP 2
LT3745-1 LVDS Topology #2
SCKO+
SCKO
SDO+
SDO
SCKI+
LDI
SCK-
SDI+
SDI
100Ω
CHIP N
SCKO+
SCKO
SDO+
SDO
37451 F01
SCKI+
LDI
SCK-
SDI+
SDI
Figure 1. Tw o Topologies of the LT3745-1 LVDS Serial Data Interface
LT3 745— 1 L7HEJWEGR 1 5
LT3745-1
15
37451f
Figure 2. Serial Data Frame Format
OPERATION
Figure 3. Serial Data Input and Output Timing Chart
COMMAND REGISTER:
C1: ENABLE LED CHANNELS - ENABLE = 1, DISABLE = 0
C0: FRAME SELECT - GS FRAME = 0, DC FRAME = 1
STATUS REGISTER:
S0-S15: LED 0-15 FAULT - FAULT = 1, OK = 0
F0: OT - OVER TEMPERATURE = 1, OK = 0
194 BITS
GS
FRAME
GS 0, 12 BITS
DC 0, 6 BITSDC 15, 6 BITS
DC 0, 6 BITSDC 15, 6 BITS
37451 F02
GS 15, 12 BITS
LSB
LSB
LSB
LSB
LSB
LSB
MSB MSB MSB
MSB MSB MSB
C0C1
DC
FRAME
C0C1x x x x x x
S00 0 0 0 0S15
0 0 0 0 0
x x x x x x
STATUS
FRAME
F00
37451 F03
SCKI 186
1 186
INPUT DATA STATUS DATA
193 1 193192 194194
193 192 193 194 1
C0 = 0C0 = 1C1
C0 = 1 F0C1
0x F0C1
C1
GS 0
LSB
C0 = 0 F0C1
GS 0
LSB GS 15
MSB
GS 15
MSB
C1 F00
GS 0
LSB
GS 0
LSB + 1
GS 15
MSB
GS 15
MSB
DC 0
LSB
DC 0
LSB
DC 0
LSB + 1
DC 15
MSB
DC 15
MSB
194 11
SDI
LDI
SR[1]
SR[0]
SCKO
SDO/
S
R[385]
tWH-LDI tHD-LDI
tSU-LDI
tWH-CKI
tWL-CKI
tSU-SDI
tHD-SDI
tPD-SCK
tPD-SCKtPD-SD
DC 15
MSB DC 15
MSB DC 15
MSB – 1 GS 15
MSB DC 15
MSB
F00
LT3745-1
LT3745-1
16
37451f
OPERATION
the SDI pins into the 194-bit shift register SR[0:193].
After 194 clock cycles, all the 194-bit data sit in the right
place waiting for the LDI signal. An asynchronous LDI high
signal latches the 1-bit FS register, 1-bit EN register, and
individual 12-bit GS registers (when FS = 0) or 6-bit DC
registers (when FS = 1) for each channel. At the same time,
a frame of status information, including over temperature
flag and individual open/short LED fault flags, is parallel
loaded into the 194-bit shift register and will be shifted
out with the coming clock cycles.
Constant Current Sink
Each LED channel has a local constant current sink regu-
lating its own LED current independent of the LED bus
voltage VOUT. The recommended LED pin voltage ranges
from 0.8V to 3V. As shown in the Typical Performance
Characteristics ILED vs VLED curves, the LED current ILED
has the best load regulation when the LED pin voltage
VLED sits above 0.5V. A lower LED bus voltage VOUT may
not regulate all the LED channels across temperature,
current, and manufacturing variation, while a higher LED
bus voltage VOUT will force a higher LED pin voltage across
the current sink, thereby dissipating more power inside
the part. See more details about the choice of the LED
bus voltage and the power dissipation calculation in the
Application Information section.
Dot Correction and Grayscale Digital-to-Analog
Conversion
The resistor on the ISET pin programs the nominal LED
current (10mA to 50mA) for all the channels. Individual
LED channel can be adjusted to a different current setting
by its own 6-bit dot correction register. The adjustable
LED current ranges from 0.5X to 1.5X of the nominal LED
current in 63 linear steps. See more details about setting
nominal LED current and dot correction in the Applications
Information section.
In addition to the dot correction current adjustment,
individual LED channels can also be modulated by their
own grayscale PWM dimming signal. To achieve a better
performance, all the grayscale PWM dimming signals are
synchronized to the same frequency with no phase shift
between rising edges. Each constant current sink is enabled
or disabled when its grayscale PWM dimming signal goes
high or low. This periodic grayscale PWM dimming signal
is generated by its own 12-bit grayscale register with a
duty cycle from 0/4096 to 4095/4096 and a period equal
to 4096 PWMCK clock cycles.
The generation of the grayscale PWM dimming signal is
best understood by referring to Figure 4. The LVDS signals
PWMCK+, PWMCK are abbreviated to the PWMCK signal.
After EN = 1 is set, the first rising edge of the PWMCK
signal will increase the internal 12-bit grayscale counter
from zero to one and turn on all the LED channels with
grayscale value not zero. Each following rising edge of
the PWMCK signal increases the grayscale counter by
one. Any LED channel will be turned off when its 12-bit
grayscale register value is equal to the value in the gray-
scale counter. To generate a 100% duty cycle for all the
grayscale PWM dimming signals, the PWMCK signal can
be paused before counting to the value in any individual
12-bit grayscale registers. Setting EN = 0 will reset the
grayscale counter to zero and turn off all the LED chan-
nels immediately.
Dual-Loop Analog
OR
Control
The switching frequency can be programmed from 200kHz
to 1MHz with the resistor connected to the RT pin and it
can be synchronized to an external clock using the SYNC
pin. Each switching cycle starts with the gate driver turning
on the external P-channel MOSFET M1 and the inductor
current is sampled through the sense resistor RS between
the ISP and ISN pins. This current is amplified and added
to a slope compensation ramp signal, and the resulting
sum is fed into the positive terminal of the PWM compara-
tor. When this voltage exceeds the level at the negative
terminal of the PWM comparator, the gate driver turns
off M1. The level at the negative terminal of the PWM
comparator is set by either of two error amplifiers GM1
and GM2. In this dual-loop analog
OR
control, the FB loop
GM1 regulates the FB pin voltage to 1.205V and the LED
loop GM2 regulates the minimum
active
LED pin voltage
(LED00 to LED15) to 0.7V. In the start-up phase, the GM2
is disabled and the output LED bus voltage is regulated
towards the feedback resistor programmed LED bus volt-
age. This FB programmed voltage defines the maximum
LT3 745— 1 ||| JIWIIIIWII H L7HEJWEGR 1 7
LT3745-1
17
37451f
LED bus voltage and should be programmed high enough
to supply the worst-case LED string across temperature,
current, and manufacturing variation.
Adaptive-Tracking-Plus-Precharging
Higher system efficiency and faster transient re-
sponse are two highly anticipated specifications in an
individually-modulated multi-channel LED driver chip.
The LT3745-1 uses a patent pending adaptive-tracking-
plus-precharging technique to achieve both of them
simultaneously.
Besides 16 internal grayscale PWM dimming signals,
the part also generates another internal precharging
signal PRECHG. As shown in Figure 4, the PRECHG
signal divides any grayscale PWM dimming cycle
into two phases: tracking phase when PRECHG = 0
and precharging phase when PRECHG = 1. During
each grayscale PWM dimming cycle – 4096 PWMCK
clock cycles, the PRECHG signal stays low for the first
3584 clock cycles (7/8 of the grayscale PWM dimming
period) and goes high for the rest 512 clock cycles (1/8
of the grayscale PWM dimming period). In the event of
all the LED channels being not
active
(i.e., either fault
or off) before the 3585th PWMCK clock, the PRECHG
signal will go high immediately.
To better explain the operation of the adaptive-tracking-
plus-precharging technique, a simplified application
system with 3-channel LED array is presented in Fig-
ure 5. Each channel consists of a single LED with the
forward voltage drop equal to 3.1V, 3.5V, and 3.9V,
respectively. Three internal grayscale PWM dimming
signals PWM1, PWM2, and PWM3 are used to modulate
each LED channel.
At the beginning of each grayscale PWM dimming
cycle, all three LED channels are turned on and the
tracking phase starts with PRECHG = 0. The amplifier
GM2 is enabled and takes the control from the amplifier
GM1, regulating the minimum
active
LED pin voltage to
0.7V. With the VLED3 equal to 0.7V, the output LED bus
voltage is tracked to 4.6V. Subsequently, at a certain
time instant t1 when the third channel is turned off, the
minimum
active
LED pin voltage goes to VLED2, 1.1V.
Then the amplifier GM2 tracks the output LED bus voltage
OPERATION
Figure 4. Grayscale PWM Dimming and Precharging Signal Timing Chart
PWMCK 40964095 1 235841 2 3
C1/EN
I(LED00)
REG = 0x002
REG = 0xFFF
TRACKING PHASE PRECHARGING PHASE
REG = 0x000
I(LED01)
tWH-PWM
tWL-PWM
tPD-PWM
I(LED15)
PRECHG
3585
37451 F04
LT3745-1
LT3745-1
18
37451f
down to 4.2V to maintain the minimum
active
LED pin
voltage equal to 0.7V again. Similarly, at the next time
instant t2, the output LED bus voltage is tracked down
to 3.8V. In this manner, the adaptive-tracking technique
eliminates unnecessary power dissipation across the
current sinks and yields superior system efficiency when
compared to a constant 4.6V output voltage.
At a later time instant t3 when the PRECHG signal goes
high, the amplifier GM2 is disabled and gives the control
back to the amplifier GM1. The amplifier GM1 regulates
the output LED bus voltage towards the FB programmed
maximum value 4.6V to guarantee shorter minimum
LED on-time for the next grayscale PWM dimming
OPERATION
cycle. Without the precharging phase, the output LED
bus voltage will stay at 3.8V before the next grayscale
PWM dimming cycle, when all the 3 LED channels will be
turned on again. At that time the 3.8V LED bus voltage
is too low to keep all the LED channels in regulation,
and the minimum LED on-time is greatly increased to
accommodate the slow transient response of the switch-
ing buck converter charging the output capacitor from
3.8V to 4.6V. This adaptive-tracking-plus-precharging
LED bus voltage technique simultaneously lowers the
power dissipation in the LT3745-1 and maintains a
shorter minimum LED on-time.
Figure 5. Adaptive-Tracking-Plus-Precharging LED Bus Voltage Technique
PWM1
PWM2
PWM3
PRECHG
IDEAL VOUT
LT3745-1 VOUT
CONSTANT VOUT
4096*T
PWMCK
4.6V
4.6V 4.2V 3.8V
t1t2t3t4
4.6V 4.2V 3.8V
3.1V
(1)VOUT = 4.6V
37451 F05
(2) (3)
1.5V 1.1V 0.7V
+
+
+
+
+ +
3.5V 3.9V
L7 LJUW LT3 745— 1 DMIN DMAX 19
LT3745-1
19
37451f
APPLICATIONS INFORMATION
Globally, the LT3745-1 converts a higher input voltage to a
single lower LED bus voltage (VOUT) supplying 16 parallel
LED strings with the adaptive-tracking-plus-precharging
technique. Locally, the part regulates and modulates the
current of each string to an independent dot correction
and grayscale PWM dimming setting sent by LVDS logic
serial data interface. This Application Information section
serves as a guideline of selecting external components
(refer to the Block Diagram) and avoiding common pitfalls
for the typical application.
Programming Maximum VOUT
The adaptive-tracking-plus-precharging technique regu-
lates VOUT to its maximum value during the start-up and
precharging phases, and adaptively lowers the voltage to
keep the minimum
active
LED pin voltage around 0.7V
during the tracking phase. Therefore, the maximum VOUT
should be programmed high enough to keep all the LED
pin voltages higher than 0.8V to maintain LED current
regulation across temperature, current, and manufactur-
ing variation. As a starting point, the maximum LED bus
voltage, VOUT(MAX), can be calculated as:
VOUT(MAX) = 0.8V + nVF(MAX)
where n is the number of LED per string and VF(MAX) is
the maximum LED forward voltage rated at the highest
operating current and the lowest operating temperature.
The VOUT(MAX) is programmed with a resistor divider
between the output and the FB pin. The resistor values
are calculated as:
RFB2 =RFB1
VOUT(MAX)
1.210V 1
Tolerance of the feedback resistors will add additional er-
rors to the output voltage, so 1% resistor values should be
used. The FB pin output bias current is typically 120nA, so
use of extremely high value feedback resistors could also
cause bias current errors. A typical value for RFB1 is 10k.
VIN Power Input Supply Range
The power input supply for the LT3745-1 can range from 6V
to 55V, covering a wide variety of industrial power supplies.
Another restriction on the minimum input voltage VIN(MIN)
is the 2.1V minimum dropout voltage between the VIN and
ISN pins, and thus the VIN(MIN) is calculated as:
VIN(MIN) = VOUT(MAX) + 2.1V
Choosing Switching Frequency
Selection of the switching frequency is a trade-off between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
and gate charge losses. However, lower frequency opera-
tion requires larger inductor and capacitor values.
Another restriction on the switching frequency comes
from the input and output voltage range caused by the
minimum switch on and switch off-time. The highest
switching frequency fSW(MAX) for a given application can
be calculated as:
fSW(MAX) =MIN DMIN
tON(MIN)
,1– DMAX
tOFF(MIN)
where the minimum duty cycle DMIN and the maximum
duty cycle DMAX are determined by:
DMIN =VOUT(MIN)
+
VD
VIN(MAX) +VD
and DMAX =VOUT(MAX)
+
VD
VIN(MIN) +VD
tON(MIN) is the minimum switch on-time (~200ns), tOFF(MIN)
is the minimum switch off-time (~120ns), VOUT(MIN) is the
minimum adaptive output voltage, VIN(MAX) is the maximum
input voltage, and VD is the catch diode forward voltage
(~0.5V). The calculation of fSW(MAX) simplifies to:
fSW(MAX) =
MIN 5VOUT(MIN) +VD
VIN(MAX) +VD
,8.33VIN(MIN) – VOUT(MAX)
VIN(MIN) +VD
MHz
LT3 745— 1 l l> 44 mV 20 L7ELUEN2
LT3745-1
20
37451f
APPLICATIONS INFORMATION
Obviously, lower frequency operation accommodates both
extremely high and low VOUT to VIN ratios.
Besides these common considerations, the specific appli-
cation also plays an important role in switching frequency
choice. In a noise-sensitive system, the switching frequency
is usually chosen to keep the switching noise out of a
sensitive frequency band.
Switching Frequency Setting and Synchronization
The LT3745-1 uses a constant switching frequency that
can be programmed from 200kHz to 1MHz with a resistor
from the RT pin to ground. Table 2 shows RT values for
common switching frequencies.
Table 2. Switching Frequency fSW vs RT Value
fSW (kHz) RT* (kΩ)
200 280
300 182
400 133
500 105
600 84.5
700 71.5
800 60.4
900 53.6
1000 46.4
* Recommend 1% Standard Values
Synchronizing the LT3745-1 oscillator to an external fre-
quency can be achieved using the SYNC pin. The square
wave amplitude, compatible to TTL/CMOS logic, should
have valleys that are below 0.6V and peaks that are above
2.4V. The synchronization frequency also ranges from
200kHz to 1MHz, in which the RT resistor should be cho-
sen to set the internal switching frequency around 20%
below the synchronization frequency. In the case of 200kHz
synchronization frequency, RT = 348k is recommended.
It is also important to note that when the synchroniza-
tion frequency is much higher than the RT programmed
internal frequency, the internal slope compensation will
be significantly reduced, which may trigger sub-harmonic
oscillation at duty cycles greater than 50%.
Inductor Current Sense Resistor RS and Current Limit
The current sense resistor, RS, monitors the inductor
current between the ISP and ISN pins, which are the in-
puts to the internal current sense amplifier. The common
mode input voltage of the current sense amplifier ranges
from 0V to (VIN – 2.1V) or 36V absolute maximum value,
whichever is lower. The current sense amplifier not only
provides current information to form the current mode
control, but also a 44mV threshold. The 44mV threshold
across the RS resistor imposes an accurate current limit
to protect both P-channel MOSFET M1 and catch diode
D1, and also to prevent inductor current saturation. Good
Kelvin sensing is required for accurate current limit. The
RS resistor value can be determined by:
IOUT(MAX) =IL(MAX)
IL
2
where the maximum inductor current IL(MAX) is set by:
IL(MAX) =
44mV
RS
IOUT(MAX) is the maximum output load current, and IL
is the inductor peak-to-peak ripple current. Allowing ad-
equate margin for ripple current and external component
tolerances, RS can be estimated as:
RS=35mV
IOUT(MAX)
Inductor Selection
The critical parameters for selection of an inductor are
inductance value, DC or RMS current, saturation current,
and DCR resistance. For a given input and output voltage,
the inductor value and switching frequency will determine
the peak-to-peak ripple current, IL. The IL value usually
ranges from 20% to 50% of the maximum output load
current, IOUT(MAX). Lower values of IL require larger and
more costly inductors; higher values of IL increase the
peak currents and the inductor core loss. An inductor
LT3 745— 1 VOUT VD L7 LJUW 2 1
LT3745-1
21
37451f
APPLICATIONS INFORMATION
current ripple of 30% to 40% offers a good compromise
between inductor performance and inductor size and cost.
However, for high duty cycle applications, a IL value of
~20% should be used to prevent sub-harmonic oscillation
due to insufficient slope compensation.
The largest inductor ripple current occurs at the highest
VIN. To guarantee that the ripple current stays below the
specified maximum, the inductor value should be chosen
according to the following equation:
LVOUT +VD
VIN(MAX) +VD
V
IN(MAX)
V
OUT
fSW IL
The inductor DC or RMS current rating must be greater
than the maximum output load current IOUT(MAX) and its
saturation current should be higher than the maximum
inductor current IL(MAX). To achieve high efficiency, the
DCR resistance should be less than 0.1Ω, and the core
material should be intended for high frequency applications.
Power MOSFET Selection
Important parameters for the external P-channel MOSFET
M1 include drain-to-source breakdown voltage (V(BR)DSS),
maximum continuous drain current (ID(MAX)), maximum
gate-to-source voltage (VGS(MAX)), total gate charge (QG),
drain-to-source on resistance (RDS(ON)), reverse transfer
capacitance (CRSS). The MOSFET V(BR)DSS specification
should exceed the maximum voltage across the source to
the drain of the MOSFET, which is VIN(MAX) plus VD. The
ID(MAX) should exceed the peak inductor current, IL(MAX).
Since the gate driver circuit is supplied by the internal
6.8V VIN referenced regulator, the VGS(MAX) rating should
be at least 10V.
Each switching cycle the MOSFET is switched off and on, a
packet of gate charge QG is transferred from the VIN pin to
the GATE pin, and then from the GATE pin to the CAP pin.
The resulting dQG/dt is a current that must be supplied to
the CCAP capacitor by the internal regulator. The maximum
22mA current capability of the internal regulator limits the
maximum QG(MAX) it can deliver to:
QG(MAX) =22mA
fSW
Therefore, the QG at VGS = 6.8V from the MOSFET data
sheet should be less than QG(MAX).
For maximum efficiency, both RDS(ON) and CRSS should
be minimized. Lower RDS(ON) means less conduction loss
while lower CRSS reduces transition loss. Unfortunately,
RDS(ON) is inversely related to CRSS. Thus balancing the
conduction loss with the transition loss is a good criterion
in selecting a MOSFET. For applications with higher VIN
voltages (≥24V) a lower CRSS is more important than a
low RDS(ON).
Catch Diode Selection
The catch diode D1 carries load current during the switch
off-time. Important parameters for the catch diode includes
peak repetitive reverse voltage (VRRM), forward voltage
(VF), and maximum average forward current (IF(AV)). The
diode VRRM specification should exceed the maximum
reverse voltage across it, i.e., VIN(MAX). A fast switching
Schottky diode with lower VF should be used to yield lower
power loss and higher efficiency.
In continuous conduction mode, the average current
conducted by the catch diode is calculated as:
ID(AVG) = IOUT • (1 – D)
The worst-case condition for the diode is when VOUT is
shorted to ground with maximum VIN and maximum IOUT
at present. In this case, the diode must safely conduct
the maximum load current almost 100% of the time. To
improve efficiency and to provide adequate margin for
short-circuit operation, a Schottky diode rated to at least
the maximum output current is recommended.
LT3 745— 1 Vom ' ( VIN ’VOUT) v2 w 22 L7ELUEN2
LT3745-1
22
37451f
APPLICATIONS INFORMATION
CIN, CVCC, and CCAP Capacitor Selection
A local input bypass capacitor CIN is required for buck
converters because the input current is pulsed with fast
rise and fall times. The input capacitor selection criteria are
based on the voltage rating, bulk capacitance, and RMS
current capability. The capacitor voltage rating must be
greater than VIN(MAX). The bulk capacitance determines the
input supply ripple voltage and the RMS current capability
is used to keep from overheating the capacitor.
The bulk capacitance is calculated based on maximum
input ripple, VIN:
CIN =DMAX IOUT(MAX)
VIN fSW
VIN is typically chosen at a level acceptable to the user.
100mV is a good starting point. For ceramic capacitors,
only X5R or X7R type should be used because they retain
their capacitance over wider voltage and temperature
ranges than other types such as Y5V or Z5U. Aluminum
electrolytic capacitors are a good choice for high voltage,
bulk capacitance due to their high capacitance per unit area.
The capacitor RMS current is:
ICIN(RMS) =IOUT VOUT ( VIN VOUT)
VIN
2
If applicable, calculate at the worst-case condition,
VIN = 2 VOUT. The capacitor RMS current rating specified
by the manufacturer should exceed the calculated ICIN(RMS).
Due to their low ESR, ceramic capacitors are a good choice
for high voltage, high RMS current handling. Note that the
ripple current ratings from aluminum electrolytic capacitor
manufacturers are based on 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
For a larger high voltage capacitor value, the combination
of aluminum electrolytic capacitors and ceramic capacitors
is an economical approach. Multiple capacitors may also
be paralleled to meet size or height requirements in the
design. Locate the capacitor very close to the MOSFET
switch and the catch diode, and use short, wide PCB traces
to minimize parasitic inductance.
The general discussion above also applies to the capacitor
CVCC at the VCC pin and the capacitor CCAP between the VIN
and CAP pins. Typically, a 10µF 10V-rated ceramic capaci-
tor for CVCC and a 0.47µF 16V-rated ceramic capacitor for
CCAP should be sufficient.
COUT Capacitor Selection
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT3745-1 to produce the DC output containing a con-
trolled voltage ripple. It also stores energy to satisfy load
transients and to stabilize the dual-loop operation. Thus
the selection criteria for COUT are based on the voltage
rating, the equivalent series resistance ESR, and the bulk
capacitance. As always, choose the COUT with a voltage
rating greater than VOUT(MAX).
The LT3745-1 utilizes the output as the dominant pole
to stabilize the dual loop operation, so the COUT value
determines the unity gain frequency fUGF, which is set
around 1/10 of the switching frequency. To stabilize the FB
loop during the start-up and precharging phases and the
LED loop during the tracking phase, a low ESR capacitor
(tens of mΩ) should be used and its minimum COUT is
calculated as:
COUT =MAX 0.25
RSfUGF
,1.5
VOUT(MAX) RSfUGF
The adaptive-tracking-plus-precharging technique moves
the VOUT with the grayscale PWM dimming frequency to
improve system efficiency, choosing a ceramic capacitor
as the COUT inevitably generates acoustic noise due to the
piezo effect of the ceramic material. In an acoustic noise
sensitive application, low ESR tantalum or aluminum
capacitors are preferred. When choosing a capacitor,
LT3 745— 1 SS VISET Ruvw L7HEJWEGR 23
LT3745-1
23
37451f
look carefully through the data sheet to find out what the
actual capacitance is under operating conditions (applied
voltage and temperature). A physically larger capacitor, or
one with a higher voltage rating, may be required.
Undervoltage Lockout (UVLO) and Shutdown
LT3745-1 has three UVLO thresholds with hysteresis for
the EN/UVLO, VCC, and CAP pins. The part will remain in
UVLO mode not switching until all the EN/UVLO, VCC, and
(VINVCAP) voltages pass their respective typical thresh-
olds (1.30V, 2.86V, and 4.9V). As shown in Figure 6, the
EN/UVLO pin can be controlled in two different ways. The
EN/UVLO pin can accept a digital input signal to enable or
disable the chip. Tie to 0.35V or lower to shut down the
chip or tie to 1.34V or higher for normal operation. This
pin can also be connected to a resistor divider between VIN
and ground to program a power input VIN UVLO threshold.
After RUV1 is selected, RUV2 can be calculated by:
RUV2 =RUV1 VIN(ON)
1.3V – 1
where VIN(ON) is the power input voltage above which the
part goes into normal operation. It is important to check
the EN/UVLO pin voltage not to exceed its 4V absolute
maximum rating:
VIN(MAX)
R
UV1
RUV1 +RUV2
<4V
APPLICATIONS INFORMATION
Soft-Start
During soft-start, the SS pin voltage smoothly ramps up
inductor current and output voltage. The effective voltage
range of SS pin is from 0V to 1V. Therefore, the typical
soft-start period is:
tSS =CSS 1V
12µA
where CSS is the capacitor connected at SS pin and
12µA is the soft-start charge current. Whenever a UVLO
or thermal shutdown occurs, the SS pin will be discharged
and the part will stop switching until the UVLO event has
disappeared and the SS pin has reached it reset threshold,
0.35V. The part then initiates a new soft-start cycle.
Setting Nominal LED Current
The nominal LED current is defined as the average LED
current across 16-channel when all the individual dot cor-
rection registers are set to 0x20. The nominal LED current
is programmed by a single resistor, RISET, between the
ISET pin and ground. The voltage at the ISET pin, VISET,
is trimmed to an accurate 1.205V, generating a current
inversely proportional to RISET. The nominal LED current,
ILED(NOM), can be calculated as:
ILED(NOM) =
V
ISET
RISET
2500
Figure 6. Methods of Controlling the EN/UVLO Pin
VIN
VCC
EN/UVLO
FROM µCONTROLLER
(6a) (6b)
37451 F06
VIN
VCC
EN/UVLO
V
IN
RUV2
RUV1
LT3745-1 LED
LT3745-1
24
37451f
ILED(NOM) must be set between 10mA and 50mA. Typical
RISET resistor values for various nominal LED currents
are listed in Table 3.
Table 3. Nominal LED Current ILED(NOM) vs. RISET Value
ILED(NOM) (mA) RISET* (kΩ)
10 301
20 150
30 100
40 75
50 60.4
* Recommend 1% Standard Values
Setting Dot Correction
The LT3745-1 can adjust the LED current for each channel
independently. This fine current adjustment, also called
dot correction, is mainly used to calibrate the brightness
deviation between LED channels. The 6-bit (64 steps) dot
correction setting adjusts each LED current from 0.5X to
1.5X of the nominal LED current according to:
ILEDn =ILED(NOM) DCn+32
64
where ILEDn is the nth LED current and DCn is the nth
programmed dot correction setting (DCn = 0 to 63). The
fine current step over the nominal LED current gives an
excellent resolution:
ILED
ILED(NON)
=1
64 1.56%
which enhances the relative LED current match accuracy
if used as calibration.
Setting Grayscale
Although adjusting the LED current changes its luminous
intensity, or brightness, it will also affect the color match-
ing between LED channels by shifting the chromaticity
coordinate. The best way to adjust the brightness is to
control the amount of LED on-/off-time by pulse width
modulation (PWM).
The LT3745-1 can adjust the brightness for each channel
independently. The 12-bit grayscale PWM dimming results
in 4096 linear brightness steps from 0% to 99.98%. The
brightness level GSn% for channel n can be calculated as:
GSn%=
GS
n
4096 100%
where GSn is the nth programmed grayscale setting
(GSn = 0 to 4095).
Open/Short LED Fault
The LT3745-1 has individual LED fault diagnostic circuitry
that detects both open and short LED faults for each chan-
nel. The open LED fault is defined as any LED string is
open or disconnected from the circuit; and the short LED
fault is defined as any LED string is shorted across itself.
The open LED flag is set if the LED pin voltage is lower
than 0.35V (typical) during on status with initial 500ns
blanking. The short LED flag is set if the LED pin voltage
is higher than 75% of the LED bus voltage VOUT any time.
If one LED channel is shorted across itself, the channel will
be turned off to eliminate unnecessary power dissipation.
The function can also be used to disable LED channels by
connecting their LED pins to the output directly. Both the
open and short LED flags are combined to set the LED
fault bits (S0 to S15) in the status frame to 1.
Thermal Protection
The LT3745-1 has two overtemperature thresholds: one
is the fixed internal thermal shutdown and the other one
is programmed by a resistor, RTSET, between the TSET
pin and ground. When the junction temperature exceeds
165°C, the part will enter thermal shutdown mode, shut
down serial data interface, turn off LED channels, and stop
switching. After the junction temperature drops below
155°C, the part will initiate a new soft-start.
APPLICATIONS INFORMATION
L7 LJUW RTSET LT3 745— 1 25
LT3745-1
25
37451f
When the RTSET is placed at the TSET pin, a current equal
to the current flowing through the RISET passes the
RTSET, generating a voltage VTSET at the TSET pin, which
is calculated as:
VTSET =1.205V
R
TSET
RISET
Then the VTSET is compared to an internal proportional-
to-absolute-temperature voltage VPTAT,
VPTAT = 1.72mV • (TJ + 273.15)
where TJ is the LT3745-1 junction temperature in °C.
When VPTAT is higher than VTSET, an overtemperature flag
OT = 1 is set. Once the RTSET programmed temperature is
exceeded, the part will also gradually derate the nominal
LED current ILED(NOM) to limit the total power dissipation
without interrupting its normal operation.
Cascading Devices and Determining Serial Data
Interface Clock
In a large LCD backlighting or LED display system, multiple
LT3745-1 chips can be easily cascaded to drive all the LED
strings. The minimum serial data interface clock frequency
fSCKI for a large display system can be calculated as:
fSCKI = NLT3745-1 • 194 • fREFRESH
APPLICATIONS INFORMATION
where NLT3745-1 is the number of LT3745-1 chips and
fREFRESH is the refresh rate of the whole system.
Calculating Power Dissipation
The total power dissipation inside the chip can be calcu-
lated as:
PTOTAL
=
VIN (IVIN
+
fSW QG)
+
VCC
IVCC +GSn%ILEDn VLEDn
n=0
15
where IVIN is the power input VIN quiescent current, IVCC
is the VCC supply current, and VLEDn is the LED pin volt-
age for channel n.
From the total power dissipation PTOTAL, the junction
temperature TJ can be calculated as:
TJ = TA + PTOTALθJA
Keep TJ below the maximum operating junction tempera-
ture 125°C.
LT3 745— 1 26 L7ELUEN2
LT3745-1
26
37451f
TYPICAL APPLICATION
Figure 7. 16-Channel LED Driver, 500kHz Buck, 1 LED 25mA to 75mA per Channel, 100Hz 12-Bit Dimming
EN/UVLO
SYNC
RT
SS
VCC
ISET
TSET
SCKI+
SCKI
SDI+
SDI
LDI
SCKO+
SCKO
SDO+
SDO
LED10
LED11
LED12
LED13
LED14
LED15
LED00
LED01
LED02
LED03
LED04
LED05
.
.
.
.
.
.
LT3745-1
100k
VIN
10V TO 40V
EN
VCC
3V TO 3.6V
VIN CAP
0.47µF
16V
M1
D1
GATE
GND
FB
ISP
ISN
4.7µF
50V
23.2k
10k
C1
220µF
L1
22µH 25mΩ 4V MAXIMUM OUTPUT VOLTAGE
PWMCK+
LVDS C1: SANYO 6TPE220MI
D1: DIODES DFLS160
L1: WÜRTH ELECTRONIK 7447779122
M1: VISHAY Si9407BDY
409.6kHz
LVDS CLOCK
LVDS
PWMCK
37451 F07
10µF
10V
105k
10nF
60.4k
32.4k
LT3 745— 1 1 iiiii fifififlfififififi E17771 , a: 122% g 1 E”; 11:. 1 1:. E777 777771 7777777777 E1. 7 a: 1 m g 1 E: '1: EH 17777111111 {1111111111 £17771 1 1 ‘1 1 1 *1 O 1 W iguuuwuuuuuéj 1 D 1 g 1 1 g E 7 777777777 T 7777777777 ’ 5 7777777777 E 1 3 C 1 1; 1 E 1 H H H H 111 1 1 H H ‘ :‘ e ‘ 117 LTLJflWE/ég 27
LT3745-1
27
37451f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
6.00 0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 ¥ 45
CHAMFER
0.40 0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 0.10
4.42 0.10
4.42 0.05
4.42 0.05
0.75 0.05 R = 0.115
TYP
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 0.05
4.50 0.05
(4 SIDES)
5.10 0.05
6.50 0.05
0.25 0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LT3 745— 1 L7LJCUEN2 28
LT3745-1
28
37451f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2012
LT 0512 • PRINTED IN USA
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ISD < 10µA, 5mm × 7mm QFN-10 Package
LT3486 Dual 1.3A , 2MHz High Current LED Driver VIN: 2.5V to 24V, VOUT(MAX) = 36V, True Color PWM Dimming = 1000:1,
ISD < 1µA, 5mm × 3mm DFN-16 TSSOP-16E Package
LT3496 Triple Output 750mA, 2.1 MHz High Current LED Driver with
3,000:1 Dimming VIN: 3V to 30V, VOUT(MAX) = 60V, True Color PWM Dimming = 3000:1,
ISD < 1µA, 4mm × 5mm QFN-28 Package
LT3595 45V, 2.5MHz 16-Channel Full Featured LED Driver VIN: 4.5V to 45V, VOUT(MAX) = 45V, True Color PWM Dimming = 5000:1,
ISD < 1µA, 5mm × 9mm QFN-56 Package
LT3598 44V, 1.5A, 2.5MHz Boost 6-Channel 30mA LED Driver VIN: 3V to 40V, VOUT(MAX) = 44V, True Color PWM Dimming = 1000:1,
ISD < 1µA, 4mm × 4mm QFN-24 Package
LT3599 44V, 2A, 2.5MHz Boost 4-Channel 120mA LED Driver VIN: 3V to 40V, VOUT(MAX) = 44V, True Color PWM Dimming = 1000:1,
ISD < 1µA, 4mm × 4mm QFN-24 Package
LT3754 60V, 1MHz Boost 16-Channel 50mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8% Current Matching VIN: 4.5V to 40V, VOUT(MAX) = 60V, True Color PWM Dimming = 3000:1,
ISD < 1µA, 5mm × 5mm QFN-32 Package
LT3760 60V, 1MHz Boost 8-Channel 100mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8% Current Matching VIN: 4.5V to 40V, VOUT(MAX) = 60V, True Color PWM Dimming = 3000:1,
ISD < 1µA, TSSOP-28E Package
Figure 8. 16-Channel LED Driver, 1MHz Buck, 10 LEDs, 25mA to 75mA per Channel, 500Hz 12-Bit Dimming
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EN/UVLO
SYNC
RT
SS
VCC
ISET
TSET
LED13
LED14
LED15
LED00
LED01
LED02
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LT3745-1
100k
VIN
42V TO 55V
EN
VCC
3V TO 3.6V
VIN CAP
0.47µF
16V
GATE
GND
FB
ISP
ISN
4.7µF
100V
267k
10k
C1
47µF
×2
L1
47µH
M1
D1
25mΩ 33.4V MAXIMUM OUTPUT VOLTAGE
PWMCK+
PWMCK
2.048MHz
LVDS CLOCK
37451 F08
10µF
10V
46.4k
10nF
60.4k
32.4k
C1: SANYO 35SVPD47M
D1: DIODES DFLS160
L1: WÜRTH ELECTRONIK 744771147
M1: VISHAY Si9407BDY
SCKI+
SCKI
SDI+
SDI
LDI
SCKO+
SCKO
SDO+
SDO
LVDS
LVDS

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