T13 Datasheet by Efinix, Inc.

QEFINIX® Tfiio
T13 Data Sheet
DST13-v2.13
August 2021
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Copyright © 2021. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other
trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.
T13 Data Sheet
Contents
Introduction..................................................................................................................................... 4
Features............................................................................................................................................4
Available Package Options......................................................................................................................5
Device Core Functional Description................................................................................................5
XLR Cell.......................................................................................................................................................6
Logic Cell....................................................................................................................................................6
Embedded Memory..................................................................................................................................7
Multipliers................................................................................................................................................... 7
Global Clock Network.............................................................................................................................. 8
Device Interface Functional Description......................................................................................... 8
Interface Block Connectivity.................................................................................................................... 8
General-Purpose I/O Logic and Buffer...................................................................................................9
Complex I/O Buffer..................................................................................................................... 11
Double-Data I/O.......................................................................................................................... 12
Clock and Control Distribution Network............................................................................................. 13
I/O Banks.................................................................................................................................................. 14
PLL............................................................................................................................................................. 14
LVDS.........................................................................................................................................................18
LVDS TX.........................................................................................................................................18
LVDS RX.........................................................................................................................................20
MIPI............................................................................................................................................................21
MIPI TX.......................................................................................................................................... 22
MIPI RX.......................................................................................................................................... 27
D-PHY Timing Parameters.......................................................................................................... 32
Power Up Sequence...................................................................................................................... 34
Power Supply Current Transient............................................................................................................35
Configuration.................................................................................................................................35
Supported Configuration Modes..........................................................................................................36
Mask-Programmable Memory Option..................................................................................................36
DC and Switching Characteristics................................................................................................. 37
LVDS I/O Electrical and Timing Specifications..............................................................................41
ESD Performance...........................................................................................................................41
MIPI Electrical Specifications and Timing.....................................................................................42
MIPI Power-Up Timing............................................................................................................................43
MIPI Reset Timing................................................................................................................................... 43
Configuration Timing.................................................................................................................... 44
PLL Timing and AC Characteristics............................................................................................... 46
Pinout Description.........................................................................................................................47
Efinity Software Support............................................................................................................... 50
T13 Interface Floorplan.................................................................................................................51
Ordering Codes............................................................................................................................. 52
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T13 Data Sheet
Revision History.............................................................................................................................53
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T13 Data Sheet
Introduction
The T13 FPGA features the high-density, low-power Efinix® Quantum™ architecture
wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and
differential I/O support, T13 FPGAs supports a variety of applications that need wide
I/O connectivity. The T13 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2
controller, which is the most popular camera interface used in the mobile industry. The
carefully tailored combination of core resources and I/O provides enhanced capability for
applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs,
power management, and LED drivers.
Features
•High-density, low-power Quantum™ architecture
•Built on SMIC 40 nm process
•Core leakage current as low as 6.8 mA(1)
•FPGA interface blocks
—GPIO
—PLL
—LVDS 800 Mbps per lane with up to 13 TX pairs and 13 RX pairs
—MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane
•Programmable high-performance I/O
—Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces
•Flexible on-chip clocking
—16 low-skew global clock signals can be driven from off-chip external clock signals or
PLL synthesized clock signals
—PLL support
•Flexible device configuration
—Standard SPI interface (active, passive, and daisy chain)
—JTAG interface
—Optional Mask Programmable Memory (MPM) capability
•Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1: T13 FPGA Resources
LEs(2) Global Clock
Networks
Global Control
Networks
Embedded
Memory (kbits)
Embedded
Memory Blocks
(5 Kbits)
Embedded
Multipliers
12,828 Up to 16 Up to 16 727.04 142 24
(1) Typical leakage current for BGA256 package only.
(2) Logic capacity in equivalent LE counts.
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T13 Data Sheet
Table 2: T13 Package-Dependent Resources
Resource BGA169 BGA256
Available GPIO(3) 73 195
Global clocks from GPIO pins 4 16
Global controls from GPIO pins 3 16
PLLs 5 5
LVDS 8 TX pairs
12 RX pairs
13 TX pairs
13 RX pairs
MIPI DPHY with CSI-2 controller
(4 data lanes, 1 clock lane)
2 TX instances
2 RX instances
–
Available Package Options
Table 3: Available Packages
Package Dimensions (mm x mm) Pitch (mm)
169-ball FBGA 9 x 9 0.65
256-ball FBGA 13 x 13 0.8
Device Core Functional Description
T13 FPGAs feature an eXchangeable Logic and Routing (XLR) cell that Efinix has optimized
for a variety of applications. Trion® FPGAs contain three building blocks constructed from
XLR cells: logic elements, embedded memory blocks, and multipliers. Each FPGA in the
Trion® family has a custom number of building blocks to fit specific application needs. As
shown in the following figure, the FPGA includes I/O ports on all four sides, as well as
columns of XLR cells, memory, and multipliers. A control block within the FPGA handles
configuration.
(3) The LVDS I/O pins are dual-purpose. The full number of GPIO are available when all LVDS I/O pins are in GPIO mode.
GPIO and LVDS as GPIO supports different features. See Table 5: Features for GPIO and LVDS as GPIO on page 10.
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T13 Data Sheet
Figure 1: T13 FPGA Block Diagram
Device Interface
Embedded Memory
Multiplier
Device Interface
Device Interface
Device Interface
XLR Cells and Routing
I/O Ports from Core to Device Interface
Note: The number and locations of rows and
columns are shown for illustration purposes
only. The actual number and position depends
on the core.
Each Device Contains Unique
Interface Blocks such as GPIO
and PLL
Quantum Fabric
XLR Cell
The eXchangeable Logic and Routing (XLR) cell is the basic building block of the Quantum™
architecture. The Efinix XLR cell combines logic and routing and supports both functions
interchangeably. This unique innovation greatly enhances the transistor flexibility and
utilization rate, thereby reducing transistor counts and silicon area significantly.
Logic Cell
The logic cell comprises a 4-input LUT or a full adder plus a register (flipflop). You can
program each LUT as any combinational logic function with four inputs. You can configure
multiple logic cells to implement arithmetic functions such as adders, subtractors, and
counters.
Figure 2: Logic Cell Block Diagram
4-Input LUT
Clock
Clock Enable
Preset/Reset
Carry In
LUT Out
Carry Out
Register Out
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T13 Data Sheet
Embedded Memory
The core has 5-kbit high-speed, synchronous, embedded SRAM memory blocks. Memory
blocks can operate as single-port RAM, simple dual-port RAM, true dual-port RAM, FIFOs,
or ROM. You can initialize the memory content during configuration. The Efinity® software
includes a memory cascading feature to connect multiple blocks automatically to form a
larger array. This feature enables you to instantiate deeper or wider memory modules.
The memory read and write ports have the following modes for addressing the memory
(depth x width):
256 x 16 1024 x 4 4096 x 1 512 x 10
512 x 8 2048 x 2 256 x 20 1024 x 5
The read and write ports support independently configured data widths.
Figure 3: Embedded Memory Block Diagram (True Dual-Port Mode)
Embedded
Memory
Write Data A [9:0]
Address A [11:0]
Write Enable A
Clock A
Clock Enable A
Read Data A [9:0]
Write Data B [9:0]
Address B [11:0]
Write Enable B
Clock B
Clock Enable B
Read Data B [9:0]
Multipliers
The FPGA has high-performance multipliers that support 18 x 18 fixed-point multiplication.
Each multiplier takes two signed 18-bit input operands and generates a signed 36-bit output
product. The multiplier has optional registers on the input and output ports.
Figure 4: Multiplier Block Diagram
Multiplier
Operand A [17:0]
Operand B [17:0]
Clock
Clock Enable A
Set/Reset A
Clock Enable B
Set/Reset B
Multiplier Output [35:0]
Clock Enable Output
Set/Reset Output
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T13 Data Sheet
Global Clock Network
The Quantum™ core fabric supports up to 16 global clock (GCLK) signals feeding 16 pre-
built global clock networks. Global clock pins (GPIO), PLL outputs, and core-generated
clocks can drive the global clock network
The Quantum™ compute fabric supports up to 16 global clock (GCLK) signals feeding 16 pre-
built global clock networks. Global clock pins (GPIO), PLL outputs, oscillator output, and
core-generated clocks can drive the global clock network.
The global clock networks are balanced clock trees that feed all FPGA modules. Each
network has dedicated clock-enable logic to save power by disabling the clock tree at the
root. The logic dynamically enables/disables the network and guarantees no glitches at the
output.
Figure 5: Global Clock Network
GCLK [8:15]GCLK [0:7]
Binary Clock Tree
Distribution
Device Interface Functional Description
The device interface wraps the core and routes signals between the core and the device
I/O pads through a signal interface. Because they use the flexible Quantum™ architecture,
devices in the Trion® family support a variety of interfaces to meet the needs of different
applications.
Learn more: The following sections describe the available device interface features in T13 FPGAs. Refer
to the Trion® Interfaces User Guide for details on the Efinity® Interface Designer settings.
Interface Block Connectivity
The FPGA core fabric connects to the interface blocks through a signal interface. The
interface blocks then connect to the package pins. The core connects to the interface blocks
using three types of signals:
•Input—Input data or clock to the FPGA core
•Output—Output from the FPGA core
•Clock output—Clock signal from the core clock tree
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ELF-1!- clock Output
T13 Data Sheet
Figure 6: Interface Block and Core Connectivity
FPGA
Signal
Interface
Core
Interface
Block
Input
Output
Clock Output
Interface
Block
GPIO
Input
Output
Clock Output
Interface
Block
Input
Output
Clock Output
Interface
Block
Input
Output
Clock Output
GPIO blocks are a special case because they can operate in several modes. For example, in
alternate mode the GPIO signal can bypass the signal interface and directly feed another
interface block. So a GPIO configured as an alternate input can be used as a PLL reference
clock without going through the signal interface to the core.
When designing for Trion® FPGAs, you create an RTL design for the core and also configure
the interface blocks. From the perspective of the core, outputs from the core are inputs to the
interface block and inputs to the core are outputs from the interface block.
The Efinity netlist always shows signals from the perspective of the core, so some signals do
not appear in the netlist:
•GPIO used as reference clocks are not present in the RTL design, they are only visible in
the interface block configuration of the Efinity® Interface Designer.
•The FPGA clock tree is connected to the interface blocks directly. Therefore, clock
outputs from the core to the interface are not present in the RTL design, they are only
part of the interface configuration (this includes GPIO configured as output clocks).
The following sections describe the different types of interface blocks in the T13. Signals and
block diagrams are shown from the perspective of the interface, not the core.
General-Purpose I/O Logic and Buffer
The GPIO support the 3.3 V LVTTL and 1.8 V, 2.5 V, and 3.3 V LVCMOS I/O standards.
The GPIOs are grouped into banks. Each bank has its own VCCIO that sets the bank voltage
for the I/O standard.
Each GPIO consists of I/O logic and an I/O buffer. I/O logic connects the core logic to the
I/O buffers. I/O buffers are located at the periphery of the device.
The I/O logic comprises three register types:
•Input—Capture interface signals from the I/O before being transferred to the core logic
•Output—Register signals from the core logic before being transferred to the I/O buffers
•Output enable—Enable and disable the I/O buffers when I/O used as output
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T13 Data Sheet
Table 4: GPIO Modes
GPIO Mode Description
Input Only the input path is enabled; optionally registered. If registered, the input path uses the
input clock to control the registers (positively or negatively triggered).
Select the alternate input path to drive the alternate function of the GPIO. The alternate path
cannot be registered.
In DDIO mode, two registers sample the data on the positive and negative edges of the input
clock, creating two data streams.
Output Only the output path is enabled; optionally registered. If registered, the output path uses the
output clock to control the registers (positively or negatively triggered).
The output register can be inverted.
In DDIO mode, two registers capture the data on the positive and negative edges of the
output clock, multiplexing them into one data stream.
Bidirectional The input, output, and OE paths are enabled; optionally registered. If registered, the input
clock controls the input register, the output clock controls the output and OE registers. All
registers can be positively or negatively triggered. Additionally, the input and output paths
can be registered independently.
The output register can be inverted.
Clock output Clock output path is enabled.
Table 5: Features for GPIO and LVDS as GPIO
LVDS as GPIO are LVDS pins that act as GPIOs instead of the LVDS function.
Supported FeaturesPackage
GPIO LVDS as GPIO
BGA169
BGA256
DDIO
Schmitt Trigger
Variable Drive Strength
Pull-up
Pull-down
Slew Rate
Pull-up
Important: Efinix® recommends that you limit the number of LVDS as GPIO set as output and
bidirectional to 16 per bank to avoid switching noise. The Efinity software issues a warning if you exceed
the recommended limit.
During configuration, all GPIO pins excluding LVDS as GPIO are configured in weak pull-
up mode.
During user mode, unused GPIO pins are tri-stated and configured in weak pull-up mode.
You can change the default mode to weak pull-down in the Interface Designer.
Note: Refer to Table 42: Single-Ended I/O Buffer Drive Strength Characteristics on page 39 for more
information.
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ALT \NCLK 0E OUTCLK OUT1 OUTO IIO Block
T13 Data Sheet
Complex I/O Buffer
Figure 7: I/O Interface Block
1. GPIO pins using LVDS resources do not have a pull-down resistor.
Note: LVDS as GPIO do not have double data I/O (DDIO).
Table 6: GPIO Signals (Interface to FPGA Fabric)
Signal Direction Description
IN[1:0] Output Input data from the GPIO pad to the core fabric.
IN0 is the normal input to the core. In DDIO mode, IN0 is the data captured on
the positive clock edge (HI pin name in the Interface Designer) and IN1 is the data
captured on the negative clock edge (LO pin name in the Interface Designer).
ALT Output Alternative input connection (in the Interface Designer, Register Option is none).
Alternative connections are GCLK, GCTRL, PLL_CLKIN, MIPI_CLKIN.(4)
OUT[1:0] Input Output data to GPIO pad from the core fabric.
OUT0 is the normal output from the core. In DDIO mode, OUT0 is the data captured
on the positive clock edge (HI pin name in the Interface Designer) and OUT1 is the
data captured on the negative clock edge (LO pin name in the Interface Designer).
OE Input Output enable from core fabric to the I/O block. Can be registered.
OUTCLK Input Core clock that controls the output and OE registers. This clock is not visible in the
user netlist.
INCLK Input Core clock that controls the input registers. This clock is not visible in the user netlist.
(4) MIPI_CLKIN is only available in packages that support MIPI.
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\n the Ink-mace Deswgnen \NO ‘5 the HI pin name and IN1 isms LO pm name.
T13 Data Sheet
Table 7: GPIO Pads
Signal Direction Description
IO Bidirectional GPIO pad.
Double-Data I/O
T13 FPGAs support double data I/O (DDIO) on certain input and output registers. In this
mode, the DDIO register captures data on both positive and negative clock edges. The core
receives 2 bit wide data from the interface.
In normal mode, the interface receives or sends data directly to or from the core on the
positive and negative clock edges. In resync mode, the interface resynchronizes the data to
pass both signals on the positive clock edge only.
Not all GPIO support DDIO; additionally, LVDS as GPIO (that is, single ended I/O) do not
support DDIO functionality.
Note: The Resource Assigner in the Efinity® Interface Designer shows which GPIO support DDIO.
Figure 8: DDIO Input Timing Waveform
DATA1
DATA2 DATA3 DATA4
DATA5 DATA6 DATA7 DATA8
DATA1
DATA3
DATA5 DATA7
DATA2
DATA4 DATA6 DATA8
DATA1
DATA3
DATA5 DATA7
DATA2 DATA4 DATA6 DATA8
GPIO Input
Clock
IN0
IN1
IN0
IN1
Normal Mode
Resync Mode
In resync mode, the IN1 data captured on the falling clock edge is delayed one half clock cycle.
In the Interface Designer, IN0 is the HI pin name and IN1 is the LO pin name.
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T13 Data Sheet
Figure 9: DDIO Output Timing Waveform
GPIO Output
Clock
Normal Mode
DATA2
OUT0
OUT1
DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
DATA4 DATA6 DATA8
DATA1
DATA3 DATA5 DATA7
DATA8
GPIO Output
Clock
Resync Mode
DATA2
OUT0
OUT1
DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
DATA4 DATA6 DATA8
DATA1
DATA3 DATA5 DATA7
DATA8
In the Interface Designer, OUT0 is the HI pin name and OUT1 is the LO pin name.
Clock and Control Distribution Network
The global clock network is distributed through the device to provide clocking for the
core's LEs, memory, multipliers, and I/O blocks. Designers can access the T13 global
clock network using the global clock GPIO pins, PLL outputs, and core-generated clocks.
Similarly, the T13 has GPIO pins (the number varies by package) that the designer can
configure as control inputs to access the high-fanout network connected to the LE's set, reset,
and clock enable signals.
Learn more: Refer to the T13 Pinout for information on the location and names of these pins.
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T13 Data Sheet
I/O Banks
Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has
independent power pins. The number and voltages supported vary by FPGA and package.
Some I/O banks are merged at the package level by sharing VCCIO pins. Merged banks have
underscores (_) between banks in the name (e.g., 1B_1C means 1B and 1C are connected).
Table 8: I/O Banks by Package
Package I/O Banks Voltage (V) Banks with
DDIO Support
Merged Banks
1A - 1E, 3A - 3E 1.8, 2.5, 3.3 1B, 1C, 1D,
3B, 3C, 3D, 3E
1B_1C_1D,
3A_3B, 3C_3D_3E
BGA169
4A, 4B 3.3 – –
1A - 1E, 3A - 3E 1.8, 2.5, 3.3 1B, 1C, 1D,
3B, 3C, 3D, 3E
1B_1C, 1D_1E.
3A_3B_3C, 3D_3E
BGA256
4A, 4B 3.3 – –
Learn more: Refer to the T13 Pinout for information on the I/O bank assignments.
PLL
The T13 has 5 available PLLs to synthesize clock frequencies.
You can use the PLL to compensate for clock skew/delay via external or internal feedback to
meet timing requirements in advanced application. The PLL reference clock has up to four
sources. You can dynamically select the PLL reference clock with the CLKSEL port. (Hold
the PLL in reset when dynamically selecting the reference clock source.)
One of the PLLs can use an LVDS RX buffer to input it’s reference clock.
The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M
counter), a post-divider counter (O counter), and output divider.
Note: Refer to T13 Interface Floorplan on page 51 for the location of the PLLs on the die. Refer to
Table 65: General Pinouts on page 47 for the PLL reference clock resource assignment.
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L, Tl
T13 Data Sheet
Figure 10: PLL Block Diagram
M
Counter
PLL
Phase
Frequency
Detector
Charge
Pump
Loop
Filter
Voltage
Control
Oscillator
Output
Divider (C)
O
Counter
CLKOUT0
LOCKED
RSTN
F
VCO
F
OUT
F
PFD
Phase
Shift
Output
Divider (C) CLKOUT1
Phase
Shift
Output
Divider (C) CLKOUT2
Phase
Shift
N
Counter
CLKIN[3]
CLKIN[2]
CLKIN[1]
CLKIN[0]
F
IN
CLKSEL[1]
CLKSEL[0]
COREFBK
Local feedback
Internal feedback
The counter settings define the PLL output frequency:
Internal Feedback Mode Local and Core Feedback Mode Where:
FPFD = FIN / N
FVCO = FPFD x M
FOUT = (FIN x M) / (N x O
x C)
FPFD = FIN / N
FVCO = (FPFD x M x O x CFBK ) (5)
FOUT = (FIN x M x CFBK) / (N x
C)
FVCO is the voltage control oscillator frequency
FOUT is the output clock frequency
FIN is the reference clock frequency
FPFD is the phase frequency detector input frequency
C is the output divider
Note: FIN must be within the values stated in PLL Timing and AC Characteristics on page 46.
Figure 11: PLL Interface Block Diagram
Trion FPGA
Core
PLL
Block
GPIO
Block(s)
PLL Signals
Reference
Clock
(5) (M x O x CFBK) must be ≤ 255.
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T13 Data Sheet
Table 9: PLL Signals (Interface to FPGA Fabric)
Signal Direction Description
CLKIN[3:0] Input Reference clocks driven by I/O pads or core clock tree.
CLKSEL[1:0] Input You can dynamically select the reference clock from one of the clock in pins.
RSTN Input Active-low PLL reset signal. When asserted, this signal resets the PLL; when de-
asserted, it enables the PLL. Connect this signal in your design to power up or reset
the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL.
Assert RSTN when dynamically changing the selected PLL reference clock.
COREFBK Input Connect to a clock out interface pin when the the PLL feedback mode is set to core.
CLKOUT0
CLKOUT1
CLKOUT2
Output PLL output. The designer can route these signals as input clocks to the core's GCLK
network.
LOCKED Output Goes high when PLL achieves lock; goes low when a loss of lock is detected.
Connect this signal in your design to monitor the lock status.
Table 10: PLL Interface Designer Settings - Properties Tab
Parameter Choices Notes
Instance Name User defined
PLL Resource The resource listing depends on the FPGA you choose.
External PLL reference clock comes from an external pin.
Dynamic PLL reference clock comes from an external pin or the core, and is
controlled by the clock select bus.
Clock Source
Core PLL reference clock comes from the core.
Automated
Clock
Calculation
Pressing this button launches the PLL Clock Caclulation window. The
calculator helps you define PLL settings in an easy-to-use graphical
interface.
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T13 Data Sheet
Table 11: PLL Interface Designer Settings - Manual Configuration Tab
Parameter Choices Notes
Reset Pin Name User defined
Locked Pin Name User defined
Internal PLL feedback is internal to the PLL resulting in no known phase
relationship between clock in and clock out.
Local PLL feedback is local to the PLL. Aligns the clock out phase with clock in.
Feedback Mode
Core PLL feedback is from the core. The feedback clock is defined by the
COREFBK connection, and must be one of the three PLL output clocks.
Aligns the clock out phase with clock in and removes the core clock delay.
Reference clock
Frequency (MHz)
User defined
Multiplier (M) 1 - 255 (integer) M counter.
Pre Divider (N) 1 - 15 (integer) N counter.
Post Divider (O) 1, 2, 4, 8 O counter.
Clock 0, Clock 1,
Clock 2
On, off Use these checkboxes to enable or disable clock 0, 1, and 2.
Pin Name User defined Specify the pin name for clock 0, 1, or 2.
Divider (C) 1 to 256 Output divider.
Phase Shift
(Degree)
0, 45, 90, 135,
180, or 270
Phase shift CLKOUT by 0, 45, 90, 135, 180, or 270 degrees.
180, and 270 require the C divider to be 2.
45 and 135 require the C divider to be 4.
90 requires the C divider to be 2 or 4.
To phase shift 225 degrees, select 45 and invert the clock at the
destination.
To phase shift 315 degrees, select 135 and invert the clock at the
destination.
Use as Feedback On, off
Table 12: PLL Reference Clock Resource Assignments (BGA169 and BGA256)
PLL REFCLK1 REFCLK2
PLL_BR0(6) Differential: GPIOB_CLKP0, GPIOB_CLKN0
Single Ended: GPIOB_CLKP0
GPIOR_157_PLLIN
PLL_TR0 GPIOR_76_PLLIN0 GPIOR_77_PLLIN1
PLL_TR1 GPIOR_76_PLLIN0 GPIOR_77_PLLIN1
PLL_TL0 GPIOL_74_PLLIN0 GPIOL_75_PLLIN1
PLL_TL1 GPIOL_74_PLLIN0 GPIOL_75_PLLIN1
(6) PLL_BR0 can be used as the PHY clock for DDR DRAM block.
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T13 Data Sheet
LVDS
The LVDS hard IP transmitters and receivers operate independently.
•LVDS TX consists of LVDS transmitter and serializer logic.
•LVDS RX consists of LVDS receiver, on-die termination, and de-serializer logic.
The T13 has one PLL for use with the LVDS receiver.
Note: You can use the LVDS TX and LVDS RX channels as 3.3 V single-ended GPIO pins, which support a
weak pull-up but do not support a Schmitt trigger or variable drive strength. When using LVDS as GPIO,
make sure to leave at least 2 pairs of unassigned LVDS pins between any GPIO and LVDS pins in the same
bank. This separation reduces noise. The Efinity software issues an error if you do not leave this separation.
The LVDS hard IP has these features:
•Dedicated LVDS TX and RX channels (the number of channels is package dependent),
and one dedicated LVDS RX clock
•Up to 800 Mbps for LVDS data transmit or receive
•Supports serialization and deserialization factors: 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, and 2:1
•Ability to disable serialization and deserialization
•Source synchronous clock output edge-aligned with data for LVDS transmitter and
receiver
•100 Ω on-die termination resistor for the LVDS receiver
Note: The LVDS RX supports the sub-lvds, slvs, HiVcm, RSDS and 3.3 V LVPECL differential I/O standards
with a transfer rate of up to 800 Mbps.
LVDS TX
Figure 12: LVDS TX Interface Block Diagram
Trion FPGA
Serializer TXP
TXN
PLL
Core
SLOWCLK
FASTCLK
OUT[n:0]
Transmitter
LVDS TX
Table 13: LVDS TX Signals (Interface to FPGA Fabric)
Signal Direction Notes
OUT[n-1:0] Input Parallel output data where n is the serialization factor.
A width of 1 bypasses the serializer.
FASTCLK Input Fast clock to serialize the data to the LVDS pads.
SLOWCLK Input Slow clock to latch the incoming data from the core.
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WWWLF
T13 Data Sheet
Table 14: LVDS TX Pads
Pad Direction Description
TXP Output Differential P pad.
TXN Output Differential N pad.
The following waveform shows the relationship between the fast clock, slow clock, TX data
going to the pad, and byte-aligned data from the core.
Figure 13: LVDS Timing Example Serialization Width of 8
OUT[7:0]
TX Pad
FASTCLK
SLOWCLK
A[7:0]
OUT is byte-aligned data passed from the core on the rising edge of SLOWCLK.
A
0A
1
A
2
A
3A
4A
5A
6A
7B
0B
1B
2B
3B
4B
5B
6B
7C
0C
1C
2C
3C
4C
5C
6C
7
B[7:0] C[7:0]
Figure 14: LVDS Timing Data and Clock Relationship Width of 8 (Parallel Clock Division=1)
TX Data
TX Clock
A
0A
1
A
2A
3A
4
A
5
A
6
A
7B
0B
1B
2B
3B
4B
5B
6B
7C
0C
1C
2C
3C
4C
5C
6C
7
Figure 15: LVDS Timing Data and Clock Relationship Width of 7 (Parallel Clock Division=1)
TX Data
TX Clock
A
0
A
1
A
2A
3A
4A
5A
6B
0B
1B
2B
3B
4B
5B
6C
0C
1C
2C
3C
4C
5C
6
Table 15: LVDS TX Settings in Efinity® Interface Designer
Parameters Choices Notes
Mode serial data output
or reference
clock output
serial data output—Simple output buffer or serialized output.
reference clock output—Use the transmitter as a clock output. When
choosing this mode, the Serialization Width you choose should
match the serialization for the rest of the LVDS bus.
Parallel Clock
Division
1, 2 1—The output clock from the LVDS TX lane is parallel clock frequency.
2—The output clock from the TX lane is half of the parallel clock
frequency.
Enable Serialization On or off When off, the serializer is bypassed and the LVDS buffer is used as a
normal output.
Serialization Width 2, 3, 4, 5, 6, 7, or 8 Supports 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, and 2:1.
Reduce VOD Swing On or off When true, enables reduced output swing (similar to slow slew rate).
Output Load 3 (default),
5, 7, or 10
Output load in pF.
www.efinixinc.com 19
2. Only available far an LVDS (deserializaliun width is 1). maeeaeeeaeaaeaemaaeae. SLOWCLKJ l l l l l l l F lN[7:0] A[7:0] X: B[7:D] : Orko] IN ls byleraligned data passed to the core on (he nsmg edge 0! SLOWCLK
T13 Data Sheet
LVDS RX
Figure 16: LVDS RX Interface Block Diagram
Trion FPGA
Deserializer
RXP1
RXN1
PLL
Core
SLOWCLK
FASTCLK
IN[n:0]
Receiver
1. There is a ~30k Ω internal weak pull-up to VCCIO (3.3V).
2. Only available for an LVDS RX resource in bypass mode
(deserialization width is 1).
LVDS RX
ALT2
PLL
Table 16: LVDS RX Signals (Interface to FPGA Fabric)
Signal Direction Notes
IN[n-1:0] Output Parallel input data where n is the de-serialization factor.
A width of 1 bypasses the deserializer.
ALT Output Alternative input, only available for an LVDS RX resource in bypass
mode (deserialization width is 1; alternate connection type). Alternative
connections are PLL_CLKIN and PLL_EXTFB.
FASTCLK Input Fast clock to de-serialize the data from the LVDS pads.
SLOWCLK Input Slow clock to latch the incoming data to the core.
Table 17: LVDS RX Pads
Pad Direction Description
RXP Input Differential P pad.
RXN Input Differential N pad.
The following waveform shows the relationship between the fast clock, slow clock, RX data
coming in from the pad, and byte-aligned data to the core.
Figure 17: LVDS RX Timing Example Serialization Width of 8
www.efinixinc.com 20
T13 Data Sheet
Table 18: LVDS RX Settings in Efinity® Interface Designer
Parameter Choices Notes
Connection Type normal, pll_clkin,
pll_extfb
normal—Regular RX function.
pll_clkin—Use the PLL CLKIN alternate function of the LVDS RX
resource.
pll_extfb—Use the PLL external feedback alternate function of the
LVDS RX resource.
Enable
Deserialization
On or off When off, the de-serializer is bypassed and the LVDS buffer is used
as a normal input.
Deserialization
Width
2, 3, 4, 5, 6, 7, or 8 Supports 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, and 2:1.
Enable On-Die
Termination
On or off When on, enables an on-die 100-ohm resistor.
MIPI
The MIPI CSI-2 interface is the most widely used camera interface for mobile.(7). You can use
this interface to build single- or multi-camera designs for a variety of applications.
T13 FPGAs include two hardened MIPI D-PHY blocks (4 data lanes and 1 clock lane) with
MIPI CSI-2 IP blocks. The MIPI RX and MIPI TX can operate independently with dedicated
I/O banks.
Note: The MIPI D-PHY and CSI-2 controller are hard blocks; users cannot bypass the CSI-2 controller to
access the D-PHY directly for non-CSI-2 applications.
The MIPI TX/RX interface supports the MIPI CSI-2 specification v1.3 and the MIPI D-PHY
specification v1.1. It has the following features:
•Programmable data lane configuration supporting 1, 2, or 4 lanes
•High-speed mode supports up to 1.5 Gbps data rates per lane
•Operates in continuous and non-continuous clock modes
•64 bit pixel interface for cameras
•Supports Ultra-Low Power State (ULPS)
Table 19: MIPI Supported Data Types
Supported
Data Type
Format
RAW RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
YUV YUV420 8-bit (legacy), YUV420 8-bit, YUV420 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit
(CSPS), YUV422 8-bit, YUV422 10-bit
RGB RGB444, RGB555, RGB565, RGB666, RGB888
User Defined 8 bit format
(7) Source: MIPI Alliance https://www.mipi.org/specifications/csi-2
www.efinixinc.com 21
REF_CLK PIXEL_CL ESC_CLK DPHY_RSTN FRAME_MODE vo[1 :0] ULPS_CLK_ENTER[3:D] ULPS_CLK_EXIT[3:0] TXDP/N4 TXDP/N3 TXDP/N2 TXDP/N1 TXDP/NO
T13 Data Sheet
With more than one MIPI TX and RX blocks, Trion® FPGAs support a variety of video
applications.
Figure 18: MIPI Example System
MIPI TX
The MIPI TX is a transmitter interface that translates video data from the Trion® core into
packetized data sent over the HSSI interface to the board. Five high-speed differential pin
pairs (four data, one clock), each of which represent a lane, connect to the board. Control and
video signals connect from the MIPI interface to the core.
Figure 19: MIPI TX x4 Block Diagram
REF_CLK
PIXEL_CLK
ESC_CLK
DPHY_RSTN
RSTN
LANES[1:0]
TXDP/N4
TXDP/N3
TXDP/N2
TXDP/N1
TXDP/N0
TX CSI-2
Controller
TX
DPHY
PPI
Interface
VSYNC
HSYNC
VALID
HRES[15:0]
DATA[63:0]
TYPE[5:0]
FRAME_MODE
VC[1:0]
ULPS_CLK_ENTER[3:0]
ULPS_CLK_EXIT[3:0]
ULPS_ENTER[4:0]
ULPS_EXIT[4:0]
Control
Video
Pads
MIPI TX Block
The control signals determine the clocking and how many transceiver lanes are used. All
control signals are required except the two reset signals. The reset signals are optional,
however, you must use both signals or neither.
The MIPI block requires an escape clock (ESC_CLK) for use when the MIPI interface is in
escape (low-power) mode, which runs between 11 and 20 MHz.
Note: Efinix recommends that you set the escape clock frequency as close to 20 MHz as possible.
The video signals receive the video data from the core. The MIPI interface block encodes is
and sends it out through the MIPI D-PHY lanes.
www.efinixinc.com 22
T13 Data Sheet
Figure 20: MIPI TX Interface Block Diagram
Core
MIPI
Block
GPIO
Block
Reference
Clock
Control and
Video Signals
Trion FPGA
TXDP/N4
TXDP/N3
TXDP/N2
TXDP/N1
TXDP/N0
MREFCLK
Table 20: MIPI TX Control Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Description
REF_CLK Input N/A Reference clock for the internal MIPI TX PLL used
to generate the transmitted data. The FPGA has a
dedicated GPIO resource (MREFCLK) that you must
configure to provide the reference clock. All of the MIPI
TX blocks share this resource.
The frequency is set using Interface Designer
configuration options.
PIXEL_CLK Input N/A Clock used for transferring data from the core to the
MIPI TX block. The frequency is based on the number
of lanes and video format.
ESC_CLK Input N/A Slow clock for escape mode (11 - 20 MHz).
DPHY_RSTN Input N/A (Optional) Reset for the D-PHY logic, active low. Reset
with the controller. See MIPI Reset Timing on page
43.
RSTN Input N/A (Optional) Reset for the CSI-2 controller logic, active
low. Typically, you reset the controller with the PHY (see
MIPI Reset Timing on page 43). However, when
dynamically changing the horizontal resolution, you
only need to trigger RSTN (see TX Requirements for
Dynamically Changing the Horizontal Resolution).
LANES[1:0] Input PIXEL_CLK Determines the number of lanes enabled. Can only be
changed during reset.
00: lane 0
01: lanes 0 and 1
11: all lanes
www.efinixinc.com 23
T13 Data Sheet
Table 21: MIPI TX Video Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Description
VSYNC Input PIXEL_CLK Vertical sync.
HSYNC Input PIXEL_CLK Horizontal sync.
VALID Input PIXEL_CLK Valid signal.
HRES[15:0] Input PIXEL_CLK Horizontal resolution. Can only be changed when
VSYNC is low, and should be stable for at least one TX
pixel clock cycle before VSYNC goes high.
DATA[63:0] Input PIXEL_CLK Video data; the format depends on the data type. New
data arrives on every pixel clock.
TYPE[5:0] Input PIXEL_CLK Video data type. Can only be changed when HSYNC is
low, and should be stable for at least one TX pixel clock
cycle before HSYNC goes high.
FRAME_MODE Input PIXEL_CLK Selects frame format. (8)
0: general frame
1: accurate frame
Can only be changed during reset.
VC[1:0] Input PIXEL_CLK Virtual channel (VC). Can only be changed when
VSYNC is low, and should be stable at least one TX
pixel clock cycle before VSYNC goes high.
ULPS_CLK_ENTER Input PIXEL_CLK Place the clock lane into ULPS mode. Should not be
active at the same time as ULPS_CLK_EXIT. Each high
pulse should be at least 5 μs.
ULPS_CLK_EXIT Input PIXEL_CLK Remove clock lane from ULPS mode. Should not be
active at the same time as ULPS_CLK_ENTER. Each high
pulse should be at least 5 μs.
ULPS_ENTER[3:0] Input PIXEL_CLK Place the data lane into ULPS mode. Should not be
active at the same time as ULPS_EXIT[3:0]. Each high
pulse should be at least 5 μs.
ULPS_EXIT[3:0] Input PIXEL_CLK Remove the data lane from ULPS mode. Should not be
active at the same time as ULPS_ENTER[3:0]. Each high
pulse should be at least 5 μs.
Table 22: MIPI TX Pads
Pad Direction Description
TXDP[4:0] Output MIPI transceiver P pads.
TXDN[4:0] Output MIPI transceiver N pads.
(8) Refer to the MIPI Camera Serial Interface 2 (MIPI CSI-2) for more information about frame formats.
www.efinixinc.com 24
T13 Data Sheet
Table 23: MIPI TX Settings in Efinity® Interface Designer
Tab Parameter Choices Notes
PHY Frequency (MHz) 80.00 - 1500.00 Choose one of the possible PHY frequency
values.
Frequency (reference
clock)
6, 12, 19.2, 25, 26,
27, 38.4, or 52 MHz
Reference clock frequency.
Base
Enable Continuous
PHY Clocking
On or Off Turns continuous clock mode on or off.
Escape Clock Pin Name User defined
Invert Escape Clock On or Off
Pixel Clock Pin Name User defined
Control
Invert Pixel Clock On or Off
Lane
Mapping
TXD0, TXD1, TXD2,
TXD3, TXD4
clk, data0, data1,
data2, or data3
Map the physical lane to a clock or data lane.
Clock Timer
TCLK-POST
TCLK-TRAIL
TCLK-PREPARE
TCLK-ZERO
Varies depending on
the PHY frequency
Changes the MIPI transmitter timing parameters
per the DPHY specification. Refer to D-PHY
Timing Parameters on page 32.
Escape Clock
Frequency (MHz)
User defined Specify a number between 11 and 20 MHz.
TCLK-PRE Varies depending
on the escape
clock frequency
Changes the MIPI transmitter timing parameters
per the DPHY specification. Refer to D-PHY
Timing Parameters on page 32.
Data Timer
Timing
THS-PREPARE
THS-ZERO
THS-PTRAIL
Varies depending on
the PHY frequency
Changes the MIPI transmitter timing parameters
per the DPHY specification. Refer to D-PHY
Timing Parameters on page 32.
www.efinixinc.com 25
T13 Data Sheet
MIPI TX Video Data TYPE[5:0] Settings
The video data type can only be changed when HSYNC is low.
Table 24: MIPI TX TYPE[5:0]
TYPE[5:0] Data Type Pixel Data Bits
per Pixel Clock
Pixels per Clock Bits per Pixel Maximum Data
Pixels per Line
0x20 RGB444 48 4 12 2,880
0x21 RGB555 60 4 15 2,880
0x22 RGB565 64 4 16 2,880
0x23 RGB666 54 3 18 2,556
0x24 RGB888 48 2 24 1,920
0x28 RAW6 60 10 6 7,680
0x29 RAW7 56 8 7 6,576
0x2A RAW8 64 8 8 5,760
0x2B RAW10 60 6 10 4,608
0x2C RAW12 60 5 12 3,840
0x2D RAW14 56 4 14 3,288
0x18 YUV420 8 bit Odd line: 64
Even line: 64
Odd line: 8
Even line: 4
Odd line: 8
Even line: 8, 24
2,880
0x19 YUV420 10 bit Odd line: 60
Even line: 40
Odd line: 6
Even line: 2
Odd line: 10
Even line: 10, 30
2,304
0x1A Legacy
YUV420 8 bit
48 4 8, 16 3,840
0x1C YUV420 8
bit (CSPS)
Odd line: 64
Even line: 64
Odd line: 8
Even line: 4
Odd line: 8
Even line: 8, 24
2,880
0x1D YUV420 10
bit (CSPS)
Odd line: 60
Even line: 40
Odd line: 6
Even line: 2
Odd line: 10
Even line: 10, 30
2,304
0x1E YUV422 8 bit 64 4 8, 24 2,880
0x1F YUV422 10 bit 40 2 10, 30 2,304
0x30 - 37 User
defined 8 bit
64 8 8 5,760
www.efinixinc.com 26
RXDP/N4 RXDP/N3 ' RXDP/Nz RXDP/N1 ' RXDP/NO ' 4» CAL_CLK PIXEL_CLK DPHY_RSTN VC_ENA[3:0] LANES[1 :0] VSYNC[ VC[1:0] ERROR ULPS_CLK ULPS[3:0]
T13 Data Sheet
MIPI RX
The MIPI RX is a receiver interface that translates HSSI signals from the board to video data
in the Trion® core. Five high-speed differential pin pairs (one clock, four data), each of which
represent a lane, connect to the board. Control, video, and status signals connect from the
MIPI interface to the core.
Figure 21: MIPI RX x4 Block Diagram
CAL_CLK
PIXEL_CLK
DPHY_RSTN
RSTN
VC_ENA[3:0]
LANES[1:0]
RXDP/N4
RXDP/N3
RXDP/N2
RXDP/N1
RXDP/N0
RX CSI-2
Controller
RX
DPHY
PPI
Interface
VSYNC[3:0]
HSYNC[3:0]
VALID
CNT[3:0]
DATA[63:0]
TYPE[5:0]
VC[1:0]
ERROR[17:0]
CLEAR
ULPS_CLK
ULPS[3:0]
MIPI RX Block
Control
Video
Status
Pads
The control signals determine the clocking, how many transceiver lanes are used, and how
many virtual channels are enabled. All control signals are required except the two reset
signals. The reset signals are optional, however, you must use both signals or neither.
The video signals send the decoded video data to the core. All video signals must fully
support the MIPI standard.
The status signals provide optional status and error information about the MIPI RX interface
operation.
Figure 22: MIPI RX Interface Block Diagram
Trion FPGA
Core
MIPI
Block
Control, Video,
and Status Signals
RXDP/N4
RXDP/N3
RXDP/N2
RXDP/N1
RXDP/N0
www.efinixinc.com 27
T13 Data Sheet
Table 25: MIPI RX Control Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
CAL_CLK Input N/A Used for D-PHY calibration; must be between 80 and 120
MHz.
PIXEL_CLK Input N/A Clock used for transferring data to the core from the MIPI
RX block. The frequency based on the number of lanes and
video format.
DPHY_RSTN Input N/A (Optional) Reset for the D-PHY logic, active low. Must be
used if RSTN is used. See MIPI Reset Timing on page 43.
RSTN Input N/A (Optional) Reset for the CSI-2 controller logic, active low.
Must be used if DPHY_RSTN is used. See MIPI Reset Timing
on page 43.
VC_ENA[3:0] Input PIXEL_CLK Enables different VC channels by setting their index high.
LANES[1:0] Input PIXEL_CLK Determines the number of lanes enabled:
00: lane 0
01: lanes 0 and 1
11: all lanes
Can only be set during reset.
Table 26: MIPI RX Video Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
VSYNC[3:0] Output PIXEL_CLK Vsync bus. High if vsync is active for this VC.
HSYNC[3:0] Output PIXEL_CLK Hsync bus. High if hsync is active for this VC
VALID Output PIXEL_CLK Valid signal.
CNT[3:0] Output PIXEL_CLK Number of valid pixels contained in the pixel data.
DATA[63:0] Output PIXEL_CLK Video data, format depends on data type. New data every
pixel clock.
TYPE[5:0] Output PIXEL_CLK Video data type.
VC[1:0] Output PIXEL_CLK Virtual channel (VC).
Table 27: MIPI RX Status Signals (Interface to FPGA Fabric)
Signal Direction Signal
Interface
Clock Domain Notes
ERROR[17:0] Output IN PIXEL_CLK Error bus register. Refer to Table 28: MIPI RX
Error Signals (ERROR[17:0]) on page 29 for
details.
CLEAR Input OUT PIXEL_CLK Reset the error registers.
ULPS_CLK Output IN PIXEL_CLK High when the clock lane is in the Ultra-Low-
Power State (ULPS).
ULPS[3:0] Output IN PIXEL_CLK High when the lane is in the ULPS mode.
www.efinixinc.com 28
T13 Data Sheet
Table 28: MIPI RX Error Signals (ERROR[17:0])
Bit Name Description
0 ERR_ESC Escape Entry Error. Asserted when an unrecognized escape entry
command is received.
1 CRC_ERROR_VC0 CRC Error VC0. Set to 1 when a checksum error occurs.
2 CRC_ERROR_VC1 CRC Error VC1. Set to 1 when a checksum error occurs.
3 CRC_ERROR_VC2 CRC Error VC2. Set to 1 when a checksum error occurs.
4 CRC_ERROR_VC3 CRC Error VC3. Set to 1 when a checksum error occurs.
5 HS_RX_TIMEOUT_ERR HS RX Timeout Error. The protocol should time out when no EoT is
received within a certain period in HS RX mode.
6 ECC_1BIT_ERROR ECC Single Bit Error. Set to 1 when there is a single bit error.
7 ECC_2BIT_ERROR ECC 2 Bit Error. Set to 1 if there is a 2 bit error in the packet.
8 ECCBIT_ERROR ECC Error. Asserted when an error exists in the ECC.
9 ECC_NO_ERROR ECC No Error. Asserted when an ECC is computed with a result zero. This
bit is high when the receiver is receiving data correctly.
10 FRAME_SYNC_ERROR Frame Sync Error. Asserted when a frame end is not paired with a frame
start on the same virtual channel.
11 INVLD_PKT_LEN Invalid Packet Length. Set to 1 if there is an invalid packet length.
12 INVLD_VC Invalid VC ID. Set to 1 if there is an invalid CSI VC ID.
13 INVALID_DATA_TYPE Invalid Data Type. Set to 1 if the received data is invalid.
14 ERR_FRAME Error In Frame. Asserted when VSYNC END received when CRC error is
present in the data packet.
15 CONTROL_ERR Control Error. Asserted when an incorrect line state sequence is detected.
16 SOT_ERR Start-of-Transmission (SoT) Error. Corrupted high-speed SoT leader
sequence while proper synchronization can still be achieved.
17 SOT_SYNC_ERR SoT Synchronization Error. Corrupted high-speed SoT leader sequence
while proper synchronization cannot be expected.
www.efinixinc.com 29
T13 Data Sheet
Table 29: MIPI RX Pads
Pad Direction Description
RXDP[4:0] Input MIPI transceiver P pads.
RXDN[4:0] Input MIPI transceiver N pads.
Table 30: MIPI RX Settings in Efinity® Interface Designer
Tab Parameter Choices Notes
DPHY Calibration Clock
Pin Name
User defined
Invert DPHY Calibration
Clock
On or Off
Pixel Clock Pin Name User defined
Control
Invert Pixel Clock On or Off
Status Enable Status On or Off Indicate whether you want to use the status pins.
RXD0, RXD1, RXD2,
RXD3, RXD4
clk, data0, data1,
data2, or data3
Map the physical lane to a clock or data lane.Lane
Mapping
Swap P&N Pin On or Off Reverse the P and N pins for the physical lane.
Calibration Clock Freq
(MHz)
User defined Specify a number between 80 and 120 MHz.
Clock Timer (TCLK-SETTLE) 40 - 2,590 ns Changes the MIPI receiver timing parameters per
the DPHY specification. Refer to D-PHY Timing
Parameters on page 32.
Timing
Data Timer (THS-SETTLE) 40 - 2,590 ns Changes the MIPI receiver timing parameters per
the DPHY specification. Refer to D-PHY Timing
Parameters on page 32.
www.efinixinc.com 30
T13 Data Sheet
MIPI RX Video Data TYPE[5:0] Settings
The video data type can only be changed when HSYNC is low.
Table 31: MIPI RX TYPE[5:0]
TYPE[5:0] Data Type Pixel Data Bits
per Pixel Clock
Pixels per Clock Bits per Pixel Maximum Data
Pixels per Line
0x20 RGB444 48 4 12 2,880
0x21 RGB555 60 4 15 2,880
0x22 RGB565 64 4 16 2,880
0x23 RGB666 54 3 18 2,556
0x24 RGB888 48 2 24 1,920
0x28 RAW6 48 8 6 7,680
0x29 RAW7 56 8 7 6,576
0x2A RAW8 64 8 8 5,760
0x2B RAW10 40 4 10 4,608
0x2C RAW12 48 4 12 3,840
0x2D RAW14 56 4 14 3,288
0x18 YUV420 8 bit Odd line: 64
Even line: 64
Odd line: 8
Even line: 4
Odd line: 8
Even line: 8, 24
2,880
0x19 YUV420 10 bit Odd line: 40
Even line: 40
Odd line: 4
Even line: 2
Odd line: 10
Even line: 10, 30
2,304
0x1A Legacy YUV420 8 bit 48 4 8, 16 3,840
0x1C YUV420 8 bit (CSPS) Odd line: 64
Even line: 64
Odd line: 8
Even line: 4
Odd line: 8
Even line: 8, 24
2,880
0x1D YUV420 10 bit (CSPS) Odd line: 40
Even line: 40
Odd line: 4
Even line: 2
Odd line: 10
Even line: 10, 30
2,304
0x1E YUV422 8 bit 64 4 8, 24 2,880
0x1F YUV422 10 bit 40 2 10, 30 2,304
0x30 - 37 User defined 8 bit 64 8 8 5,760
www.efinixinc.com 31
Last Packet a! Data Frame End Packet 7 7 Frame Start Packet Fm Packe‘ a! Data #\ 7 , Long Packet» wx H5 pawns E 171 Note. 1. To emer mgh-speed mode‘ |he D-PHV goes |hrough smes LFHL LF-OL and LP-au, The D»FHV genelales LP-M to em mgn-speed mode. Clock Lane Dlsmnned Tenmnamr
T13 Data Sheet
D-PHY Timing Parameters
During CSI-2 data transmission, the MIPI D-PHY alternates between low power mode and
high-speed mode. The D-PHY specification defines timing parameters to facilitate the correct
hand-shaking between the MIPI TX and MIPI RX during mode transitions.
You set the timing parameters to correspond to the specifications of your hardware in the
Efinity® Interface Designer.
•RX parameters—TCLK-SETTLE, THS-SETTLE (see Table 25: MIPI RX Control Signals
(Interface to FPGA Fabric) on page 28)
•TX parameters—TCLK-POST, TCLK-TRAIL, TCLK-PREPARE, TCLK-ZERO, TCLK-PRE, THS-
PREPARE, THS-ZERO, THS-TRAIL (see Table 23: MIPI TX Settings in Efinity Interface
Designer on page 25)
Figure 23: High-Speed Data Transmission in Bursts Waveform
V
IDTH
(max)
V
IL
(max)
Dp/Dn
CLK
Disconnect
Terminator
V
IH
(min)
V
TERM-EN
(max)
T
HS-PREPARE
T
HS-ZERO
T
LPX
T
D-TERM-EN
T
HS-SETTLE
LP-00LP-01
LP-11 (1)
Capture First
Data Bit
T
HS-TRAIL
LP-11
T
HS-EXIT
T
EOT
T
HS-SKIP
T
REOT
Note:
1. To enter high-speed mode, the D-PHY goes through states LP-11, LP-01, and LP-00. The D-PHY generates LP-11 to exit high-speed mode.
Last Packet of Data
Data
SoT
SoT SoTSoTEoT
LPS
LPS LPS
EoT EoT EoT
PH
PF FE FS
Long Packet
Frame Blanking
Frame End Packet
Frame Start Packet
First Packet of Data
Long Packet
Data
PH PF
Figure 24: Switching the Clock Lane between Clock Transmission and Low Power Mode Waveform
T
D-TERM-EN
Data Lane
Clock Lane
Disconnect Terminator
Dp/Dn
Dp/Dn
Disconnect
Terminator
T
HS-SETTLE
T
CLK-PREPARE
T
HS-EXIT
T
CLK-TRAIL
T
HS-SKIP
T
CLK-MISS
T
CLK-POST
T
EOT
T
CLK-SETTLE
T
CLK-TERM-EN
T
CLK-PRE
T
CLK-ZERO
T
LPX
T
LPX
T
HS-PREPARE
V
IL
(max)
V
IH
(min)
V
IL
(max)
V
IH
(min)
www.efinixinc.com 32
T13 Data Sheet
Table 32: D-PHY Timing Specifications
Parameter Description Min Typ Max Unit
TCLK-POST Time that the transmitter continues to
send HS clock after the last associated
Data Lane has transitioned to LP Mode.
Interval is defined as the period from the
end of THS-TRAIL to the beginning of TCLK-
TRAIL.
60 ns + 52*UI – – ns
TCLK-PRE Time that the HS clock shall be driven by
the transmitter prior to any associated
Data Lane beginning the transition from
LP to HS mode.
8 – – UI
TCLK-PREPARE Time that the transmitter drives the
Clock Lane LP-00 Line state immediately
before the HS-0 Line state starting the HS
transmission.
38 – 95 ns
TCLK-SETTLE Time interval during which the HS
receiver should ignore any Clock Lane HS
transitions, starting from the beginning of
TCLK-PREPARE.
95 – 300 ns
TCLK-TRAIL Time that the transmitter drives the HS-0
state after the last payload clock bit of a
HS transmission burst.
60 – – ns
TCLK-PREPARE +
TCLK-ZERO
TCLK-PREPARE + time that the transmitter
drives the HS-0 state prior to starting the
Clock.
300 – – ns
THS-PREPARE Time that the transmitter drives the
Data Lane LP-00 Line state immediately
before the HS-0 Line state starting the HS
transmission
40 ns + 4*UI – 85 ns + 6*UI ns
THS-SETTLE Time interval during which the HS receiver
shall ignore any Data Lane HS transitions,
starting from the beginning of THS-PREPARE.
The HS receiver shall ignore any Data
Lane transitions before the minimum
value, and the HS receiver shall respond
to any Data Lane transitions after the
maximum value.
85 ns + 6*UI – 145 ns + 10*UI ns
THS-TRAIL Time that the transmitter drives the
flipped differential state after last payload
data bit of a HS transmission burst
max( n*8*UI,
60 ns + n*4*UI)
– – ns
TLPX Transmitted length of any Low-Power state
period
50 – – ns
THS-PREPARE +
THS-ZERO
THS-PREPARE + time that the transmitter
drives the HS-0 state prior to transmitting
the Sync sequence.
145 ns + 10*UI – – ns
www.efinixinc.com 33
VCC
T13 Data Sheet
Power Up Sequence
Efinix® recommends the following power up sequence when powering Trion® FPGAs:
1. Power up VCC and VCCA_xx first.
2. When VCC and VCCA_xx are stable, power up all VCCIO pins. There is no specific
timing delay between the VCCIO pins.
3. Apply power to VCC12A_MIPI_TX, VCC12A_MIPI_RX, and VCC25A_MIPI at least
tMIPI_POWER after VCC is stable.
4. After all power supplies are stable, hold CRESET_N low for a duration of tCRESET_N
before asserting CRESET_N from low to high to trigger active SPI programming (the
FPGA loads the configuration data from an external flash device).
When you are not using the GPIO, MIPI or PLL instances, connect the pins as shown in the
following table.
Table 33: Connection Requirements for Unused Instances
Unused Instance Pin Note
GPIO VCCIOxx Connect to either 1.8 V, 2.5 V, or 3.3 V.
PLL VCCA_PLL Connect to VCC.
VCC12A_MIPI_TX Connect to VCC.
VCC12A_MIPI_RX Connect to VCC.
MIPI
VCC25A_MIPI Connect to VCC.
Note: Refer to Configuration Timing on page 44 and MIPI Power-Up Timing on page 43 for timing
information.
Figure 25: Trion® FPGAs Power Up Sequence
VCC
VCCA_xx
VCC12A_MIPI_TX
VCC12A_MIPI_RX
VCC25A_MIPI
t
MIPI_POWER
CRESET_N
All VCCIO
t
CRESET_N
www.efinixinc.com 34
T13 Data Sheet
Power Supply Current Transient
You may observe an inrush current on the dedicated power rail during power-up. You must
ensure that the power supplies selected in your board meets the current requirement during
power-up and the estimated current during user mode. Use the Power Estimator to calculate
the estimated current during user mode.
Table 34: Maximum Power Supply Current Transient
Power Supply Maximum Power Supply
Current Transient(9)(10)
Unit
VCC 35 mA
Configuration
The T13 FPGA contains volatile Configuration RAM (CRAM). The user must configure the
CRAM for the desired logic function upon power-up and before the FPGA enters normal
operation. The FPGA's control block manages the configuration process and uses a bitstream
to program the CRAM. The Efinity® software generates the bitstream, which is design
dependent. You can configure the T13 FPGA(s) in active, passive, or JTAG mode.
Learn more: Refer to AN 006: Configuring Trion FPGAs for details on the dedicated configuration pins
and how to configure FPGA(s).
Figure 26: High-Level Configuration Options
Board
SPI Flash
SPI Active Mode
Controller
Processor
Microcontroller
JTAG
Interface
SPI Passive Mode
Controller
JTAG Mode
Controller
Configuration
Manager
User
Logic
Control Block
Trion FPGA
SPI Data
JTAG
In active mode, the FPGA controls the configuration process. An oscillator circuit within the
FPGA provides the configuration clock. The bitstream is typically stored in an external serial
flash device, which provides the bitstream when the FPGA requests it.
The control block sends out the instruction and address to read the configuration data. First,
it issues a release from power-down instruction to wake up the external SPI flash. Then, it
waits for at least 30 μs before issuing a fast read command to read the content of SPI flash
from address 24h’000000.
(9) Inrush current for other power rails are not significant in Trion® FPGAs.
(10) Measured at room temperature.
www.efinixinc.com 35
¢¢¢J¢¢ ¢ ¢¢¢¢¢¢¢¢J¢
T13 Data Sheet
In passive mode, the FPGA is the slave and relies on an external master to provide the
control, bitstream, and clock for configuration. Typically the master is a microcontroller or
another FPGA in active mode.
In JTAG mode, you configure the FPGA via the JTAG interface.
Supported Configuration Modes
Table 35: T13 Configuration Modes by Package
Configuration Mode Width BGA256 BGA169
x1
x2
Active
x4
x1
x2
x4
x8
x16
Passive
x32
JTAG x1
Learn more: Refer to AN 006: Configuring Trion FPGAs for more information.
Mask-Programmable Memory Option
The T13 FPGA is equipped with one-time programmable MPM. With this feature, you use
on-chip MPM instead of an external serial flash device to configure the FPGA. This option
is for systems that require an ultra-small factor and the lowest cost structure such that an
external serial flash device is undesirable and/or not required at volume production. MPM is
a one-time factory programmable option that requires a Non-Recurring Engineering (NRE)
payment. To enable MPM, submit your design to our factory; our Applications Engineers
(AEs) convert your design into a single configuration mask to be specially fabricated.
www.efinixinc.com 36
T13 Data Sheet
DC and Switching Characteristics
Table 36: Absolute Maximum Ratings
Conditions beyond those listed may cause permanent damage to the device. Device operation at the absolute
maximum ratings for extended periods of time has adverse effects on the device.
Symbol Description Min Max Units
VCC Core power supply -0.5 1.42 V
VCCIO I/O bank power supply -0.5 4.6 V
VCCA_PLL PLL analog power supply -0.5 1.42 V
VCC25A_MIPI0
VCC25A_MIPI1
2.5 V analog power supply for MIPI -0.5 2.75 V
VCC12A_MIPI0_TX
VCC12A_MIPI1_TX
1.2 V TX analog power supply for MIPI -0.5 1.42 V
VCC12A_MIPI0_RX
VCC12A_MIPI1_RX
1.2 V RX analog power supply for MIPI -0.5 1.42 V
VIN I/O input voltage -0.5 4.6 V
TJOperating junction temperature -40 125 °C
Table 37: Recommended Operating Conditions (C3, C4, Q4, and I4 Speed Grades) (11)
Symbol Description Min Typ Max Units
VCC Core power supply 1.15 1.2 1.25 V
1.8 V I/O bank power supply 1.71 1.8 1.89 V
2.5 V I/O bank power supply 2.38 2.5 2.63 V
VCCIO
3.3 V I/O bank power supply 3.14 3.3 3.47 V
VCCA_PLL PLL analog power supply 1.15 1.2 1.25 V
VCC25A_MIPI0
VCC25A_MIPI1
2.5 V analog power supply for MIPI 2.38 2.5 2.63 V
VCC12A_MIPI0_TX
VCC12A_MIPI1_TX
1.2 V TX analog power supply for MIPI 1.15 1.2 1.25 V
VCC12A_MIPI0_RX
VCC12A_MIPI1_RX
1.2 V RX analog power supply for MIPI 1.15 1.2 1.25 V
VIN I/O input voltage(12) -0.3 – VCCIO
+ 0.3
V
TJCOM Operating junction temperature, commercial 0 – 85 °C
TJIND Operating junction temperature, industrial -40 – 100 °C
TJAUT Operating junction temperature, automotive -40 – 105 °C
(11) Supply voltage specification applied to the voltage taken at the device pins with respect to ground, not at the power supply.
(12) Values applicable to both input and tri-stated output configuration.
www.efinixinc.com 37
Out 92
T13 Data Sheet
Table 38: Recommended Operating Conditions (C4L and I4L Speed Grades) (11)
Symbol Description Min Typ Max Units
VCC Core power supply 1.05 1.1 1.15 V
1.8 V I/O bank power supply 1.71 1.8 1.89 V
2.5 V I/O bank power supply 2.38 2.5 2.63 V
VCCIO
3.3 V I/O bank power supply 3.14 3.3 3.47 V
VCCA_PLL PLL analog power supply 1.05 1.1 1.15 V
VCC25A_MIPI0
VCC25A_MIPI1
2.5 V analog power supply for MIPI 2.38 2.5 2.63 V
VCC12A_MIPI0_TX
VCC12A_MIPI1_TX
1.1 V TX analog power supply for MIPI 1.05 1.1 1.15 V
VCC12A_MIPI0_RX
VCC12A_MIPI1_RX
1.1 V RX analog power supply for MIPI 1.05 1.1 1.15 V
VIN I/O input voltage(13) -0.3 – VCCIO
+ 0.3
V
TJCOM Operating junction temperature, commercial 0 – 85 °C
TJIND Operating junction temperature, industrial -40 – 100 °C
Table 39: Power Supply Ramp Rates
Symbol Description Min Max Units
tRAMP Power supply ramp rate for all supplies. 0.01 10 V/ms
Table 40: Single-Ended I/O DC Electrical Characteristics
VIL (V) VIH (V) VOL (V) VOH (V)I/O Standard
Min Max Min Max Max Min
3.3 V LVCMOS -0.3 0.8 2 VCCIO + 0.3 0.2 VCCIO - 0.2
3.3 V LVTTL -0.3 0.8 2 VCCIO + 0.3 0.4 2.4
2.5 V LVCMOS -0.3 0.7 1.7 VCCIO + 0.3 0.5 1.8
1.8 V LVCMOS -0.3 0.35 * VCCIO 0.65 * VCCIO VCCIO + 0.3 0.45 VCCIO - 0.45
Table 41: Single-Ended I/O and Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic
Voltage (V) VT+ (V) Schmitt
Trigger Low-to-
High Threshold
VT- (V) Schmitt
Trigger High-to-
Low Threshold
Input Leakage
Current (μA)
Tri-State Output
Leakage
Current (μA)
3.3 1.73 1.32 ±10 ±10
2.5 1.37 1.01 ±10 ±10
1.8 1.05 0.71 ±10 ±10
(13) Values applicable to both input and tri-stated output configuration.
www.efinixinc.com 38
(v p
T13 Data Sheet
Table 42: Single-Ended I/O Buffer Drive Strength Characteristics
Junction temperature at TJ = 25 °C, power supply at nominal voltage.
I/O Standard 3.3 V 2.5 V 1.8 V
Drive Strength IOH (mA) IOL (mA) IOH (mA) IOL (mA) IOH (mA) IOL (mA)
1 14.4 8.0 9.1 8.0 4.4 5.1
2 19.1 10.5 12.2 10.5 5.8 6.8
3 23.9 13.3 15.2 13.4 7.3 8.6
4 28.7 15.8 18.2 15.9 8.6 10.3
Table 43: Single-Ended I/O Internal Weak Pull-Up and Pull-Down Resistors
Internal Pull-Up Internal Pull-DownI/O Standard
Min Typ Max Min Typ Max
Units
3.3 V LVTTL/LVCMOS 27 40 65 30 47 83 kΩ
2.5 V LVCMOS 35 55 95 37 62 118 kΩ
1.8 V LVCMOS 53 90 167 54 99 202 kΩ
Table 44: LVDS Pins Configured as Single-Ended I/O DC Electrical Characteristics
VIL (V) VIH (V) VOL (V) VOH (V)I/O Standard
Min Max Min Max Max Min
3.3 V LVCMOS -0.3 0.8 2 VCCIO + 0.3 0.2 VCCIO - 0.2
3.3 V LVTTL -0.3 0.8 2 VCCIO + 0.3 0.4 2.4
Table 45: LVDS Pins Configured as Single-Ended I/O DC Electrical Characteristics
Voltage (V) Input Leakage Current (μA) Tri-State Output Leakage Current (μA)
3.3 ±10 ±10
Table 46: LVDS Pins as Single-Ended I/O Buffer Drive Strength Characteristics
Junction temperature at TJ = 25 °C, power supply at nominal voltage, device in nominal process (TT).
Drive StrengthI/O Standard
IOH (mA) IOL (mA)
3.3 V 37.6 22
Table 47: LVDS Pins Configured as Single-Ended I/O Internal Weak Pull-Up Resistors
Internal Pull-UpI/O Standard
Min Typ Max
Units
3.3 V LVTTL/LVCMOS 27 40 65 kΩ
www.efinixinc.com 39
T13 Data Sheet
Table 48: Single-Ended I/O and LVDS Pins Configured as Single-Ended I/O Characteristics
Symbol Description All Speed Grades Units
fMAX Single-ended I/O and LVDS configured as single-ended
I/O maximum frequency. Test condition at 10 pF output
loading. Applicable to all I/O standards.
200 MHz
Table 49: Block RAM Characteristics
Speed GradeSymbol Description
C3, C4L, I4L C4, I4, Q4
Units
fMAX Block RAM maximum frequency. 310 400 MHz
Table 50: Multiplier Block Characteristics
Speed GradeSymbol Description
C3, C4L, I4L C4, I4, Q4
Units
fMAX Multiplier block maximum frequency. 310 400 MHz
www.efinixinc.com 40
T13 Data Sheet
LVDS I/O Electrical and Timing Specifications
The LVDS pins comply with the EIA/TIA electrical specifications.
Note: The LVDS RX supports the sub-lvds, slvs, HiVcm, RSDS and 3.3 V LVPECL differential I/O standards
with a transfer rate of up to 800 Mbps.
Table 51: LVDS I/O Electrical Specifications
Parameter Description Test Conditions Min Typ Max Unit
VCCIO LVDS I/O Supply Voltage – 2.97 3.3 3.63 V
LVDS TX
VOD Output Differential Voltage – 250 – 450 mV
Δ VOD Change in VOD – – – 50 mV
VOCM Output Common Mode Voltage RT = 100 Ω 1,125 1,250 1,375 mV
Δ VOCM Change in VOCM – – – 50 mV
VOH Output High Voltage RT = 100 Ω – – 1475 mV
VOL Output Low Voltage RT = 100 Ω 925 – – mV
ISAB Output Short Circuit Current – – – 24 mA
LVDS RX
VID Input Differential Voltage – 100 – 600 mV
VICM Input Common Mode Voltage – 100 – 2,000 mV
VTH Differential Input Threshold – -100 – 100 mV
IIL Input Leakage Current – – – 20 μA
Figure 27: LVDS RX I/O Electrical Specification Waveform
-ve
0 V
+ve
V
ID
V
ICM
Table 52: LVDS Timing Specifications
Parameter Description Min Typ Max Unit
tLVDS_DT LVDS TX reference clock output duty cycle 45 50 55 %
tLVDS_skew LVDS TX lane-to-lane skew – 200 – ps
ESD Performance
Refer to the Trion Reliability Report for ESD performance data.
www.efinixinc.com 41
T13 Data Sheet
MIPI Electrical Specifications and Timing
The MIPI D-PHY transmitter and receiver are compliant to the MIPI Alliance Specification
for D-PHY Revision 1.1.
Table 53: High–Speed MIPI D–PHY Transmitter (TX) DC Specifications
Parameter Description Min Typ Max Unit
VCMTX High–speed transmit static common–mode voltage 150 200 250 mV
|Δ VCMTX(1,0)| VCMTX mismatch when output is Differential–1 or
Differential–0
– – 5 mV
|VOD| High–speed transmit differential voltage 140 200 270 mV
|Δ VCMTX| VOD mismatch when output is Differential–1 or
Differential–0
– – 14 mV
VOHHS High–speed output high voltage – – 360 mV
ZOS Single ended output impedance 40 50 62.5 Ω
Δ ZOS Single ended output impedance mismatch – – 10 %
Table 54: Low–Power MIPI D–PHY Transmitter (TX) DC Specifications
Parameter Description Min Typ Max Unit
VOH Thevenin output high level 0.99 – 1.21 V
VOL Thevenin output low level –50 – 50 mV
ZOLP Output impedance of low–power transmitter 110 – – Ω
Table 55: High–Speed MIPI D–PHY Receiver (RX) DC Specifications
Parameter Description Min Typ Max Unit
VCMRX(DC) Common mode voltage high–speed receive mode 70 – 330 mV
VIDTH Differential input high threshold – – 70 mV
VIDTL Differential input low threshold –70 – – mV
VIHHS Single–ended input high voltage – – 460 mV
VILHS Single–ended input low voltage –40 – – mV
VTERM–EN Single–ended threshold for high–speed termination
enable
– – 450 mV
ZID Differential input impedance 80 100 125 Ω
Table 56: Low–Power MIPI D–PHY Receiver (RX) DC Specifications
Parameter Description Min Typ Max Unit
VIH Logic 1 input voltage 880 – – mV
VIL Logic 0 input voltage, not in ULP state – – 550 mV
VIL–ULPS Logic 0 input voltage, ULP state – – 300 mV
VHYST Input hysteresis 25 – – mV
www.efinixinc.com 42
t 1 clk Mmlmum
T13 Data Sheet
MIPI Power-Up Timing
Apply power to VCC12A_MIPI_TX, VCC12A_MIPI_RX, and VCC25A_MIPI at least
tMIPI_POWER after VCC is stable. See Power Up Sequence on page 34 for a power-up sequence
diagram.
Table 57: MIPI Timing
Symbol Parameter Min Typ Max Units
tMIPI_POWER Minimum time after VCC and VCCA_xx are
stable before powering VCC12A_MIPI_TX,
VCC12A_MIPI_RX, and VCC25A_MIPI.
1 – – μs
MIPI Reset Timing
The MIPI RX and TX interfaces have two signals (RSTN and DPHY_RSTN) to reset the CSI-2
and D-PHY controller logic. These signals are active low, and you should use them together
to reset the MIPI interface.
The following waveform illustrates the minimum time required to reset the MIPI interface.
Figure 28: RSTN and DPHY_RSTN Timing Diagram
DPHY_RSTN
RX or TX Data
t
INIT_A
100 us Minimum
RSTN
t
INIT_D
1 clk Minimum
Table 58: MIPI Timing
Symbol Parameter Min Typ Max Units
tINIT_A Minimum time between the rising edge of
DPHY_RSTN and the start of MIPI RX or TX data.
100 – – μs
tINIT_D Minimum time between the rising edge of
RSTN and the start of MIPI RX or TX data.
1 – – clk
www.efinixinc.com 43
T13 Data Sheet
Configuration Timing
The T13 FPGA has the following configuration timing specifications. Refer to AN 006:
Configuring Trion FPGAs for detailed configuration information.
Timing Waveforms
Figure 29: SPI Active Mode (x1) Timing Sequence
CCK
CRESET_N
SS_N
CDI0
CDI1
Read
24 bit Start Address Dummy Byte
t
CRESET_N
t
H
t
SU
Data
VCC
Figure 30: SPI Passive Mode (x1) Timing Sequence
CCK
CRESET_N
SSL_N
CDI
CDONE
Header and Data
t
CRESET_N
t
H
t
USER
GND
The FPGA enters user mode; configuration
I/O pins are released for user functions
t
SU
t
DMIN
t
CLK
t
CLKL
Figure 31: Boundary-Scan Timing Waveform
TMS
TDI
TCK
TDO
t
TMSSU
t
TDISU
t
TMSH
t
TDIH
t
TCKTDO
Timing Parameters
www.efinixinc.com 44
T13 Data Sheet
Table 59: All Modes
Symbol Parameter Min Typ Max Units
tCRESET_N Minimum creset_n low pulse width required to
trigger re-configuration.
320 – – ns
tUSER Minimum configuration duration after CDONE
goes high before entering user mode.(14)(15)
Test condition at 10 kΩ pull-up resistance and
10 pF output loading on CDONE pin.
12 – – μs
Table 60: Active Mode
Symbol Parameter Frequency Min Typ Max Units
DIV4 14 20 26 MHzfMAX_M Active mode configuration clock frequency.
DIV8 7 10 13 MHz
tSU Setup time. Test condition at 3.3 V I/O
standard and 0 pF output loading.
– 7.5 – – ns
tHHold time. Test condition at 3.3 V I/O
standard and 0 pF output loading.
– 1 – – ns
Table 61: Passive Mode
Symbol Parameter Min Typ Max Units
Passive mode X1 configuration clock frequency. – – 25 MHzfMAX_S
Passive mode X2, X4 or X8 configuration clock
frequency.
– – 50 MHz
tCLKH Configuration clock pulse width high. 4.8 – – ns
tCLKL Configuration clock pulse width low. 4.8 – – ns
tSU Setup time. 6 – – ns
tHHold time. 1 – – ns
tDMIN Minimum time between deassertion of
CRESET_N to first valid configuration data.
1.2 – – μs
(14) The FPGA may go into user mode before tUSER has elapsed. However, Efinix recommends that you keep the system
interface to the FPGA in reset until tUSER has elapsed.
(15) For JTAG programming, the min tUSER configuration time is required after CDONE goes high and FPGA receives the
ENTERUSER instruction from JTAG host (TAP controller in UPDATE_IR state).
www.efinixinc.com 45
T13 Data Sheet
Table 62: JTAG Mode
Symbol Parameter Min Typ Max Units
fTCK TCK frequency. – – 33 MHz
tTDISU TDI setup time. 3.5 – – ns
tTDIH TDI hold time. 1 – – ns
tTMSSU TMS setup time. 3 – – ns
tTMSH TMS hold time. 1 – – ns
tTCKTDO TCK falling edge to TDO output. – – 10.5(16) ns
PLL Timing and AC Characteristics
The following tables describe the PLL timing and AC characteristics.
Table 63: PLL Timing
Symbol Parameter Min Typ Max Units
Input clock frequency from core. 10 – 330 MHz
Input clock frequency from GPIO. 10 – 200 MHz
FIN(17)
Input clock frequency from LVDS. 10 – 400 MHz
FOUT Output clock frequency. 0.24 – 500 MHz
FVCO PLL VCO frequency. 500 – 1,600 MHz
FPFD Phase frequency detector input frequency. 10 – 50 MHz
Table 64: PLL AC Characteristics(18)
Symbol Parameter Min Typ Max Units
tDT Output clock duty cycle. 40 50 60 %
tOPJIT (PK - PK)
(19)
Output clock period jitter (PK-PK). – – 200 ps
tILJIT (PK - PK) Input clock long-term jitter (PK-PK) – – 800 ps
tLOCK PLL lock-in time. – – 0.5 ms
(16) 0 pf output loading.
(17) When using the Dynamic clock source mode, the maximum input clock frequency is limited by the slowest clock
frequency of the assigned clock source. For example, the maximum input clock frequency of a Dynamic clock source
mode from core and GPIO is 200 MHz.
(18) Test conditions at 3.3 V and room temperature.
(19) The output jitter specification applies to the PLL jitter when an input jitter of 20 ps is applied.
www.efinixinc.com 46
T13 Data Sheet
Pinout Description
The following tables describe the pinouts for power, ground, configuration, and interfaces.
Table 65: General Pinouts
Function Group Direction Description
VCC Power – Core power supply.
VCCA_xx Power – PLL analog power supply. xx indicates location:
TL: Top left, TR: Top right, BR: bottom right
VCCIOxx Power – I/O pin power supply. xx indicates the bank location:
1A: Bank 1A, 3E: Bank 3E
4A: Bank 4A (only for 3.3 V) , 4B: Bank 4B (only for 3.3 V)
VCCIOxx_yy_zz Power – Power for I/O banks that are shorted together. xx, yy, and zz
are the bank locations. For example:
VCCIO1B_1C shorts banks 1B and 1C
VCCIO3C_TR_BR shorts banks 3C, TR, and BR
GND Ground – Ground.
CLKnAlternate Input Global clock network input. n is the number. The number of
inputs is package dependent.
CTRLnAlternate Input Global network input used for high fanout and global
reset. n is the number. The number of inputs is package
dependent.
PLLIN Alternate Input PLL reference clock resource. There are 5 PLL reference
clock resource assignments. Assign the reference clock
resource based on the PLL you are using.
MREFCLK Alternate Input MIPI PLL reference clock source.
GPIOx_n GPIO I/O General-purpose I/O for user function. User I/O pins are
single-ended.
x: Indicates the bank (L or R)
n: Indicates the GPIO number.
GPIOx_n_yyy
GPIOx_n_yyy_zzz
GPIOx_zzzn
GPIO
Multi-
Function
I/O Multi-function, general-purpose I/O. These pins are single
ended. If these pins are not used for their alternate function,
you can use them as user I/O pins.
x: Indicates the bank; left (L), right (R), or bottom (B).
n: Indicates the GPIO number.
yyy, yyy_zzz: Indicates the alternate function.
zzzn: Indicates LVDS TX or RX and number.
TXNn, TXPnLVDS I/O LVDS transmitter (TX). n: Indicates the number.
RXNn, RXPnLVDS I/O LVDS receiver (RX). n: Indicates the number.
CLKNn, CLKPnLVDS I/O Dedicated LVDS receiver clock input. n: Indicates the
number.
RXNn_EXTFBn
RXPn_EXTFBn
LVDS I/O LVDS PLL external feedback. n: Indicates the number.
REF_RES – – LVDS reference resistor pin. Connect a 12 kΩ resistor with a
tolerance of ±1% to the REF_RES pin with respect to ground.
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T13 Data Sheet
Table 66: Dedicated Configuration Pins
These pins cannot be used as general-purpose I/O after configuration.
Pins Direction Description Use External
Weak Pull-Up
CDONE Output Configuration done status pin. CDONE is an open drain output;
connect it to an external pull-up resistor to VCCIO. When CDONE
= 1, configuration is complete. If you hold CDONE low, the device
will not enter user mode.
CRESET_N Input Initiates FPGA re-configuration (active low). Pulse CRESET_N low
for a duration of tcreset_N before asserting CRESET_N from low to
high to initiate FPGA re-configuration. This pin does not perform a
system reset.
TCK Input JTAG test clock input (TCK). The rising edge loads signals applied
at the TAP input pins (TMS and TDI). The falling edge clocks out
signals through the TAP TDO pin.
TMS Input JTAG test mode select input (TMS). The I/O sequence on this
input controls the test logic operation . The signal value typically
changes on the falling edge of TCK. TMS is typically a weak pull-
up; when it is not driven by an external source, the test logic
perceives a logic 1.
TDI Input JTAG test data input (TDI). Data applied at this serial input is fed
into the instruction register or into a test data register depending
on the sequence previously applied at TMS. Typically, the signal
applied at TDI changes state following the falling edge of TCK
while the registers shift in the value received on the rising edge.
Like TMS, TDI is typically a weak pull-up; when it is not driven from
an external source, the test logic perceives a logic 1.
TDO Output JTAG test data output (TDO). This serial output from the test logic
is fed from the instruction register or from a test data register
depending on the sequence previously applied at TMS. During
shifting, data applied at TDI appears at TDO after a number of
cycles of TCK determined by the length of the register included
in the serial path. The signal driven through TDO changes state
following the falling edge of TCK. When data is not being shifted
through the device, TDO is set to an inactive drive state (e.g., high-
impedance).
Note: All dedicated configuration pins have Schmitt Trigger buffer. See Table 41: Single-Ended I/O and
Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic on page 38 for the Schmitt Trigger
buffer specifications.
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T13 Data Sheet
Table 67: Dual-Purpose Configuration Pins
In user mode (after configuration), you can use these dual-purpose pins as general I/O.
Pins Direction Description Use External
Weak Pull-Up
CBUS[2:0] Input Configuration bus width select. Connect to weak pull-up
resistors if using default mode (x1).
CBSEL[1:0] Input Optional multi-image selection input (if external multi-image
configuration mode is enabled).
N/A
CCK I/O Passive SPI input configuration clock or active SPI output
configuration clock (active low). Includes an internal weak
pull-up.
N/A
CDInI/O n is a number from 0 to 31 depending on the SPI
configuration.
0: Passive serial data input or active serial output.
1: Passive serial data output or active serial input.
n: Parallel I/O.
In multi-bit daisy chain connection, the CDIn (31:0) connects
to the data bus in parallel.
N/A
CSI Input Chip select.
0: The FPGA is not selected or enabled and will not be
configured.
1: Selects the FPGA for configuration.
CSO Output Chip select output. Selects the next device for cascading
configuration.
N/A
NSTATUS Output Status (active low). Indicates a configuration error. When the
FPGA drives this pin low, it indicates an ID mismatch, the
bitstream CRC check has failed, or remote update has failed.
N/A
SS_N Input SPI slave select (active low). Includes an internal weak
pull-up resistor to VCCIO during configuration. During
configuration, the logic level samples on this pin determine
the configuration mode. This pin is an input when sampled
at the start of configuration (SS is low); an output in active SPI
flash configuration mode.
The FPGA senses the value of SS_N when it comes out of
reset (pulse CRESET_N low to high).
0: Passive mode
1: Active mode
TEST_N Input Active-low test mode enable signal. Set to 1 to disable test
mode.
During configuration, rely on the external weak pull-up or
drive this pin high.
RESERVED_OUT Output Reserved pin during user configuration. This pin drives high
during user configuration.
BGA49 and BGA81 packages only.
N/A
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T13 Data Sheet
Table 68: MIPI Pinouts (Dedicated)
n Indicates the number. L indicates the lane
Function Group Direction Description
VCC25A_MIPI0
VCC25A_MIPI1
Power – MIPI 2.5 V analog power supply.
VCC12A_MIPI0_TX
VCC12A_MIPI1_TX
Power – MIPI 1.2 V TX analog power supply.
VCC12A_MIPI0_RX
VCC12A_MIPI1_RX
Power – MIPI 1.2 V RX analog power supply.
GNDA_MIPI Ground – Ground for MIPI analog power supply.
MIPIn_TXDPL
MIPIn_TXDNL
MIPI I/O MIPI differential transmit data lane.
MIPIn_RXDPL
MIPIn_RXDNL
MIPI I/O MIPI differential receive data lane.
MREFCLK Clock Input MIPI PLL reference clock source.
Efinity Software Support
The Efinity® software provides a complete tool flow from RTL design to bitstream
generation, including synthesis, place-and-route, and timing analysis. The software has a
graphical user interface (GUI) that provides a visual way to set up projects, run the tool flow,
and view results. The software also has a command-line flow and Tcl command console. The
Efinity® software supports simulation flows using the ModelSim, NCSim, or free iVerilog
simulators. An integrated hardware Debugger with Logic Analyzer and Virtual I/O debug
cores helps you probe signals in your design. The software-generated bitstream file configures
the T13 FPGA. The software supports the Verilog HDL and VHDL languages.
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T13 Data Sheet
T13 Interface Floorplan
Note: The numbers in the floorplan figures indicate the GPIO and LVDS number ranges. Some packages
may not have all GPIO or LVDS pins in the range bonded out. Refer to the T13 pinout for information on
which pins are available in each package.
Figure 32: Floorplan Diagram for BGA169 Packages (with MIPI)
Right
Left
1A
0
Quantum
Core Fabric
Dimensions not to scale
43
10
1B
27
28
1C
44
61
1D
62
75
1E
76 89
3A
3E
158
141
3D
123
124
3C
90
3B
107
108
143
TL
TR
BR
PLL_TL0
PLL_TL1
PLL_TR0
PLL_TR1
PLL_BR0 (1)
Note:
1. PLL_BR0 has an LVDS
reference clock
0
12
4B
LVDS TX
0 12
4A
LVDS RX
I/O bank
GPIO blocks
Dedicated blocks
PLL reference clock
LVDS block
LVDS clock
9
BL
2A 2B
MIPI block
TX
RX
MIPI 0
TX RX
MIPI 1
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T13 Data Sheet
Figure 33: Floorplan Diagram for BGA256 Packages
Right
Left
1A
0
Quantum
Core Fabric
Dimensions not to scale
43
10
1B
27
28
1C
44
61
1D
62
75
1E
76 89
3A
3E
158
141
3D
123
124
3C
90
3B
107
108
143
TL TR
BR
PLL_TL0
PLL_TL1
PLL_TR0
PLL_TR1
PLL_BR0 (1)
Note:
1. PLL_BR0 has an LVDS
reference clock
0
12
4B
LVDS
TX
0 12
4A
LVDS RX
I/O bank
GPIO blocks
Dedicated blocks
PLL reference clock
LVDS block
LVDS clock
9
BL
Ordering Codes
Refer to the Trion Selector Guide for the full listing of T13 ordering codes.
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T13 Data Sheet
Revision History
Table 69: Revision History
Date Version Description
August 2021 2.13 Added internal weak pull-up and pull-down resistor specs.
(DOC-485)
Updated table title for Single-Ended I/O Schmitt Trigger Buffer
Characteristic. (DOC-507)
Added note in Pinout Description stating all dedicated
configuration pins have Schmitt Trigger buffer. (DOC-507)
June 2021 2.12 Updated CRESET_N pin description. (DOC-450)
April 2021 2.11 Updated PLL specs; tILJIT (PK - PK) and tDT. (DOC-403)
Added note about limiting number of LVDS as GPIO output and
bidirectional per I/O bank to avoid switching noise. (DOC-411)
March 2021 2.10 Added LVDS TX reference clock output duty cycle and lane-to-lane
skew specs. (DOC-416)
March 2021 2.9 Added automotive speed grade (Q4) specs for BGA169 package.
(DOC-399)
February 2021 2.8 Added I/O input voltage, VIN specification. (DOC-389)
Added LVDS TX data and timing relationship waveform.
(DOC-359)
Added LVDS RX I/O electrical specification waveform. (DOC-346)
December 2020 2.7 Updated NSTATUS pin description. (DOC-335)
Added data for C4L and I4L DC speed grades. (DOC-268)
Updated PLL reference clock input note by asking reader to refer
to PLL Timing and AC Characteristics. (DOC-336)
Added other PLL input clock frequency sources in PLL Timing and
AC Characteristics. (DOC-336)
Removed OE and RST from LVDS block as they are not supported
in software. (DOC-328)
Added a table to Power Up Sequence topic describing pin
connection when PLL, GPIO, or MIPI is not used. (DOC-325)
Updated fMAX_S for passive configuration modes. (DOC-350)
Updated fMAX_S for passive configuration modes. (DOC-350)
September 2020 2.6 Updated pinout links.
Corrected speed grades for single-ended I/O and LVDS
configured as single-ended I/O fMAX.
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T13 Data Sheet
Date Version Description
August 2020 2.5 Update MIPI TX and RX Interface Block Diagram to include signal
names.
Updated REF_CLK description for clarity.
Added recommended operating conditions and fMAX for C4L and
I4L speed grades.
Updated tUSER timing parameter values and added a note about
the conditions for the values.
Updated description for GPIO pins state during configuration to
exclude LVDS as GPIO.
Added fMAX for single-ended I/O and LVDS configured as single-
ended I/O.
Added maximum power supply current transient during power-up.
July 2020 2.4 Removed preliminary note from MIPI electrical specifications and
timing. These specifications are final.
Updated timing parameter symbols in boundary scan timing
waveform to reflect JTAG mode parameter symbols.
Added supported GPIO features.
Updated the maximum FVCO for PLL to 1,600 MHz.
Updated the C divider requirement for the 90 degrees phase shift
in the PLL Interface Designer Settings - Manual Configuration Tab.
Updated LVDS electrical specifications note about RX differential
I/O standard support, and duplicated the note in LVDS functional
description topic.
Added note to LVDS RX interface block diagram.
Added note to recommended power-up sequence about MIPI
power guideline.
Updated I/O bank names from TL_CORNER, BL_CORNER,
TR_CORNER, and BR_CORNER to TL, BL, TR, and BR respectively.
Updated the term DSP to multiplier.
Updated power up sequence description about holding
CRESET_N low.
Updated PLLCLK pin name to PLL_CLKIN.
Added PLL_EXTFB and MIPI_CLKIN as an alternative input in GPIO
signals table for complex I/O buffer.
Updated PLL names in PLL reference clock resource assignments.
Updated supported configuration modes.
Updated typical leakage current to 6.8 mA and add a note stating
it is applicable to BGA256 package.
February 2020 2.3 Added fMAX for DSP blocks and RAM blocks.
In MIPI RX and TX interface description, updated maximum data
pixels for RAW10 data type.
Added MIPI reset timing information.
Added Trion power-up sequence. MIPI power-up moved to this
topic.
VCC12A_MIPI_TX, VCC12A_MIPI_RX maximum recommended
operating condition changed to 1.25 V.
Added number of global clocks and controls that can come from
GPIO pins to package resources table.
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T13 Data Sheet
Date Version Description
December 2019 2.2 Updated PLL Interface Designer settings.
Removed MIPI data type bit settings. Refer to AN 015: Designing
with the Trion MIPI Interface for the bit settings.
Removed DIV1 and DIV2 active mode configuration frequencies;
they are not supported.
Added note to LVDS electrical specifications about RX differential
I/O standard support.
October 2019 2.1 Added explanation that 2 unassigned pairs of LVDS pins should be
located between and GPIO and LVDS pins in the same bank.
Updated the reference clock pin assignments for TL_PLL0 and
TL_PLL1.
Added waveforms for configuration timing.
August 2019 2.0 Updated MIPI interface description.
Under Ordering Codes, linked to Trion FPGA Selector Guide.
May 2019 1.0 Updated MIPI description, DC characteristics, and pin information.
Updated timing specifications.
Added information on the signal interface.
January 2019 0.5 Added information on DDIO support.
December 2018 0.4 Updated the package options.
November 2018 0.3 Added GNDA_xx (PLL analog ground) to pinout.
Change VSSxxA_MIPI pinout to GNDxxA_MIPI.
Updated PLL block diagram and clarified feedback paths.
Added floorplan information.
Updated pinout table.
Updated packaging options.
October 2018 0.2 Updated LVDS serialization factors.
October 2018 0.1 Initial release.
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