XC6127 Series Datasheet by Torex Semiconductor Ltd

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XC6127 fl / R0217-010 Ultra Small Voltage Detector with High Precision Delay Circuit and Manual Reset Function IGENERAL DESCRIPTION IAPPLICATIONS l FEATURES I TYPICAL PERFORMANCE % ,7, fir
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Ultra Small Voltage Detector with High Precision Delay Circuit and Manual Reset Function
XC6127
Series
GENERAL DESCRIPTION
XC6127 series is ultra small highly accurate voltage detector with delay circuit built-in.
The device includes a highly accurate reference voltage source, manufactured using CMOS process technology and laser
trimming technologies, it maintains high accuracy, low power consumption, and accurate releases delay time over the full
operation temperature range.
The release delay time periods are internally set in a range from 50ms to 800ms.
Moreover, with the manual reset function, reset can be asserted at any time.
The device is available in both CMOS and N-channel open drain output configurations. Also detect logic is available in both
RESETB (Active Low) and RESET (Active High).
Ultra small package USPN-4 is ideally suited for small design of portable devices and high densely mounting applications.
The conventional packages SSOT-24, SOT-25 is also available for upper compatible replacements.
FEATURES
High Accuracy
:
±0.8% (25
)
Temperature Characteristics : ±50ppm/
Low Power Consumption :
0.6
μ
A TYP. (Detect: V
DF
=1.8V, V
IN
=1.62V)
0.7
μ
A TYP. (Release: V
DF
=1.8V, V
IN
=1.98V)
Operating Voltage Range
:
0.7V ~ 6.0V
Detect Voltage Range : 1.5V ~ 5.5V (0.1V increments)
Manual Reset Input : MRB Pin (Built-in Pull-up resistance)
Output Configuration : N-channel open drain or CMOS
Output Logic
:
RESETB (Active Low)
RESET (Active High)
Release Delay Time :
50ms/100ms/200ms/400ms/800ms±15%
Operating Ambient Temperature
Packages
:
:
-40 ~ 85
USPN-4, SSOT-24, SOT-25
Environmentally Friendly : EU RoHS Compliant, Pb Free
ETR0217-
010
APPLICATIONS
Microprocessor logic reset circuitry
System battery life and charge voltage monitors
Memory battery back-up circuits
Power-on reset circuits
Power failure Detection
Delay circuit
TYPICAL APPLICATION CIRCUIT
TYPICAL PERFORMANCE
CHARACTERISTICS
V
IN
V
IN
MRB
RESETB
RESET
RESET
SW
V
IN
MRB
RESETB
RESET
RESET
SW
Rpull
Vpull-Up
CMOS output
N-ch open drain output
XC6127 series
XC6127 series
RESETB/RESET
INPUT
VCC
μP
VSS
RESETB/RESET
INPUT
VCC
μP
VSS
V
IN
V
SS
V
SS
XC6127x27Bx
85
90
95
100
105
110
115
-50 -25 025 50 75 100
Ambient Temperature: Ta (℃)
Release Delay Time: t
DR
(ms)
V
IN
=V
DFL
×0.9→V
DFL
×1.1 , MRB=OPEN
I BLOCK DIAGRAMS 1))(06127 Series. Type CxxA/CxxB/CxxC/CxxD/CXXE (CMOS Ou X
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XC6127 Series
1) XC6127 Series, Type CxxA/CxxB/CxxC/CxxD/CxxE (CMOS Output, Output Logic: Active Low)
V
IN
RESETB
+
-
Comparator
Voltage
Reference
MRB
Delay
Circuit
V
SS
R
MRB
R1
R2
R1
+
-
Comparator
R2 Voltage
Reference
Delay
Circuit
V
IN
RESETB
MRB
V
SS
R
MRB
BLOCK DIAGRAMS
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
* Diodes inside the circuits are ESD protection diodes
2) XC6127 Series, Type NxxA/NxxB/NxxC/NxxD/NxxE (N-ch Open Drain Output, Output Logic: Active Low)
X66127 IBLOCK DIAGRAMS (Continued) 3) XC6127 Series. Type CxxF/CxxG/CxxH/CxxJ/CXXK (CMOS Ou X 4) X06127 Series, Type NxxF/NxxG/NxxH/NxxJ/NxxK (Nrch Open Drain Ompun Ou‘pu‘ LogiczAcfive High). fiim
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XC6127
Series
3) XC6127 Series, Type CxxF/CxxG/CxxH/CxxJ/CxxK (CMOS Output, Output Logic: Active High)
R1
+
-
Comparator
R2 Voltage
Reference
Delay
Circuit
V
IN
RESET
MRB
V
SS
R
MRB
R1
+
-
Comparator
R2 Voltage
Reference
Delay
Circuit
V
IN
RESET
MRB
V
SS
R
MRB
BLOCK DIAGRAMS (Continued)
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
* Diodes inside the circuits are ESD protection diodes.
4) XC6127 Series, Type NxxF/NxxG/NxxH/NxxJ/NxxK (N-ch Open Drain Output, Output Logic: Active High).
M I PRODUCT CLASSIFICATION W CMOS oulpux W The G 5qu denmes Halogen and Amimuny lree as well as bemg fuIly EU RoHS compnam,
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XC6127 Series
DESIGNATOR
ITEM
SYMBOL
DESCRIPTION
Output Configuration
C
CMOS output
N
N-ch open drain output
②③
Detect Voltage
15 ~ 55
e.g. 2.7V →
=2,
=7
Type
A
Reset Active Low, Release Delay Time: 50ms
B
Reset Active Low, Release Delay Time: 100ms
C
Reset Active Low, Release Delay Time: 200ms
D
Reset Active Low, Release Delay Time: 400ms
E
Reset Active Low, Release Delay Time: 800ms
F
Reset Active High, Release Delay Time: 50ms
G
Reset Active High, Release Delay Time: 100ms
H
Reset Active High, Release Delay Time: 200ms
J
Reset Active High, Release Delay Time: 400ms
K
Reset Active High, Release Delay Time: 800ms
⑤⑥-(*1) Packages (Order Unit)
7R-G
USPN-4 (5,000pcs/Reel)
MR-G
SOT-25 (3,000pcs/Reel)
NR-G
SSOT-24 (3,000pcs/Reel)
2) Selection Guide
TYPE Release Delay Time Output Logic
A 50ms Active Low
B 100ms Active Low
C 200ms Active Low
D 400ms Active Low
E 800ms Active Low
F 50ms Active High
G 100ms Active High
H 200ms Active High
J 400ms Active High
K 800ms Active High
PRODUCT CLASSIFICATION
Ordering Information
XC6127
①②③④-
(*1)
(*1) The “-G suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant.
X66127 IPIN CONFIGURATION H H i * |:| r:| |:| |:| E El 7 D , USPN-4 SSOT—24 SOT-25 IPIN ASSIGNMENT IFUNCTION CHART
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XC6127
Series
PIN NUMBER PIN NAME FUNCTIONS
USPN-4 SSOT-24 SOT-25
1 4 4 RESETB Signal Output (Active Low) (*1)
RESET Signal Output (Active High) (*2)
2 3 1 MRB Manual Reset Input
3 2 2 VSS Ground
4 1 5 VIN Power Input
- - 3 NC No Connection
PIN NAME SIGNAL STATUS
MRB
L Forced Reset
H Normal Operation
OPEN Normal Operation
PIN ASSIGNMENT
PIN CONFIGURATION
(*1) Type A ~ E (Refer to the in Ordering Information table)
(*2) Type F ~ K (Refer to the in Ordering Information table)
FUNCTION CHART
RESETB
RESET
V
IN
12
34
MRB
23
14
MRB
V
SS
13
2
54
SOT-25
(TOP VIEW)
SSOT-24
(TOP VIEW)
USPN-4
(BOTTOM VIEW)
V
IN
V
SS
RESETB
RESET
V
IN
V
SS
RESETB
RESET
MRB NC
SOT-25
(TOP VIEW)
SSOT-24
(TOP VIEW)
USPN-4
(BOTTOM VIEW)
M IABSOLUTE MAXIMUM RATINGS
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XC6127 Series
PARAMETER SYMBOL RATINGS UNITS
Input Voltage VIN VSS - 0.3 ~ VSS + 6.5 V
MRB Input Voltage VMRB VSS ~ VSS+6.5 V
Output Current (*1) 20 mA
Output Voltage XC6127C (*2) (*4) VSS - 0.3 ~ VIN + 0.3 VSS + 6.5 V
XC6127N (*3) VSS - 0.3 ~ VSS + 6.5
Power Dissipation
(Ta=25)
USPN-4
Pd
100
mW
600 (40mm x 40mm Standard board) (*5)
SOT-25
250
600 (40mm x 40mm Standard board) (*5)
760 (JESD51-7 board)) (*5)
SSOT-24
150
500 (40mm x 40mm Standard board) (*5)
680 (JESD51-7 board) (*5)
Operating Ambient Temperature Topr -40 ~ 85
Storage Temperature Ts t g -55 ~ 125
(*1) SYMBOL is different for each product.
IRBOUT: Type XC6127CxxA/CxxB/CxxC/CxxD/CxxE, Type XC6127NxxA/NxxB/NxxC/NxxD/NxxE
IROUT: Type XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, Type XC6127NxxF/NxxG/NxxH/NxxJ/NxxK
(*2) CMOS Output
(*3) N-ch Open Drain Output
(*4) SYMBOL is different for each product.
VRESETB: Type XC6127CxxA/CxxB/CxxC/CxxD/CxxE, Type XC6127NxxA/NxxB/NxxC/NxxD/NxxE
VRESET: Type XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, Type XC6127NxxF/NxxG/NxxH/NxxJ/NxxK
(*5) This power dissipation figure shown is PCB mounted and is for reference only.
The mounting condition is please refer to PACKAGING INFORMATION.
ABSOLUTE MAXIMUM RATINGS
X66127 I ELECTRICAL CHARACTERISTICS XCEI27CxxA/CxxB/CxxC/CxxD/CXXE, X06IZ7NxxA/NxxB/NxxC/NxxD/NXXE (Output Logic. Active Low) PARAMETER SYMBOL CONDITIONS MIN, TVP MAX. UNITS CIRCUI 5.1“! RESETB RESETE CMOS Leaka e CquuI(PCh) g NChOperI DraInOuLpuI Avun/ (ATopr-va AppIIed pulse Io MRB pm‘ I“! v .NomInaI deIecl voIIage TOIEEX
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XC6127
Series
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
CIRCUI
Operating Voltage VIN
V
DF(T)(*1)
=1.5 ~ 5.5V, MRB=OPEN
(*2)
0.7 (*3)
6.0 V -
Detect Voltage VDFL VDF(T)=1.5 ~ 5.5V, MRB=OPEN
V
DF(T)
×0.992 V
DF(T)
V
DF(T)
×1.008
V
E-1
(*4)
Hysteresis Width VHYS
V
DFL
×0.02 V
DFL
×0.05 V
DFL
×0.08
V
Supply Current 1 ISS1
VIN=VDFL×0.9 , MRB=OPEN
μA
VDF(T)=1.5 ~ 1.8V
-
0.6
1.4
VDF(T)=1.9 ~ 3.0V - 0.7 1.6
VDF(T)=3.1 ~ 5.5V
-
1.0
1.9
Supply Current 2 ISS2
VIN=VDFL×1.1
(*5)
, MRB=OPEN
μA
VDF(T)=1.5 ~ 1.8V
-
0.7
1.6
VDF(T)=1.9 ~ 3.0V - 0.8 1.9
VDF(T)=3.1 ~ 5.5V
-
1.1
2.35
RESETB
Output Current
IRBOUT1
V
IN
=0.7V, V
RESETB
=0.5V(Nch) , MRB=OPEN
0.014 0.2 -
mA
V
IN
=1.0V, V
RESETB
=0.5V(Nch) , MRB=OPEN
0.5 1.6 -
V
IN
=2.0V
(*6)
, V
RESETB
=0.5V(Nch) , MRB=OPEN
4.4 7.0 -
V
IN
=3.0V
(*7)
, V
RESETB
=0.5V(Nch) , MRB=OPEN
7.0 9.0 -
V
IN
=4.0V
(*8)
, V
RESETB
=0.5V(Nch) , MRB=OPEN
8.5 11.0 -
V
IN
=5.0V
(*9)
, V
RESETB
=0.5V(Nch) , MRB=OPEN
9.0 12.0 -
IRBOUT2(*10)
V
IN
=6.0V, V
RESETB
=5.5V(Pch) , MRB=OPEN
- -4.5 -3.0 mA
RESETB
Leakage
Current
CMOS
Output(Pch)
ILEAK
V
IN
=V
DFL
×0.9, V
RESETB
=0V , MRB=OPEN
- -0.01 - μA
Nch Open
Drain Output
V
IN
=6.0V, V
RESETB
=6.0V , MRB=OPEN
- 0.01 0.15 μA
Temperature Characteristics
ΔV
DFL
/
(ΔTopr
V
DFL
)
-40℃≦Topr85 - ±50 - ppm/
Detect Delay Time
(*11)
tDF
V
IN
=V
DFL
×1.1→V
DFL
×0.9
(*11)
, MRB=OPEN
- - 100 μs
Release Delay Time
(*12)
tDR
V
IN
=V
DFL
×0.9→V
DFL
×1.1
(*12)
, MRB=OPEN
E-2 (*13) ms
MRB “Low” Level Voltage
(*14)
VMRL VDFL×1.1VIN6.0V VSS - 0.3 V
MRB “High” Level Voltage
(*14)
VMRH VDFL×1.1VIN6.0V 1.0 - 6.0 V
MRB pull-up Resistance RMRB 0.4 0.8 3.0
Minimum MRB Pulse Width
TMRB
V
IN
=6.0V,
Applied pulse to MRB pin,
150 - - ns
ELECTRICAL CHARACTERISTICS
Ta=25
XC6127CxxA/CxxB/CxxC/CxxD/CxxE, XC6127NxxA/NxxB/NxxC/NxxD/NxxE (Output Logic: Active Low)
(*1) V
DF (T)
: Nominal detect voltage
(*2) For the N-ch Open Drain, Rpull=100kΩ, Vpull-Up=VIN
Rpull: An External Pull-up resistor
Vpull-Up: Pull-up Voltage
(*3) VIN voltage for VOUT0.3V is under detect state.
(*4) For the detail value, please refer to Voltage Tablein P10.
(*5) VDF (T) = 5.5V where VIN=6.0V
(*6) For VDF(T)2.0V products.
(*7) For VDF(T)3.0V products.
(*8) For VDF(T)4.0V products.
(*9) For VDF(T)5.0V products.
(*10) For the XC6127C (CMOS output)
(*11) A time between VIN=VDFL and VRESETB=VDFL×0.45 when VIN falls.
(*12) A time between VIN=VDFL+VHYS and VRESETB=VDFL×0.55 when VIN rises.
(*13) For the detail value, please refer to Release Delay Timein P11.
(*14) For MRB pin, please do not apply the voltage below VSS.
IELECTRICAL CHARACTERISTICS (Continued) XCS127CxxF/CxxG/CxxH/CxxJ/CXXKI XC6127NxxF/NxxG/NxxH/NxxJ/NXXK (Output Logic. Active ngh) PARAMETER SYMBOL CONDiTIONS MIN. TYP. MAX UNITS CIRCUIT E-I mm 9 I MRB=OPEN vumr .5 ~ 1.8V - o 6 1 4 vum, .9 ~ 3.0V - o 7 1 6 - I o 1 g VIN- mm 1'» MRB=OPEN vum,:1.5 ~1.sv - o 7 16 vum, .9 ~ 3.0V - o s 1 g vum,:3.1 ~ 5.5V - I I 2.35 RESET IRuuTz CMOS RESET Leakage N-ch Open Temperalure LII/W
8/30
XC6127 Series
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CIRCUIT
Operating Voltage
VIN
V
DF(T)
(*1)
=1.5
~
5.5V, MRB=OPEN
(*2)
0.7
(*3)
6.0
V
-
Detect Voltage VDFH
V
DF(T)
=1.5
~
5.5V, MRB=OPEN V
DF(T)
×0.992
VDF(T)
V
DF(T)
×1.008
V
E-1
(*4)
Hysteresis Width VHYS
V
DFH
×0.02 V
DFH
×0.05 V
DFH
×0.08
V
Supply Current 1 ISS1
VIN=VDFH×0.9 , MRB=OPEN
μA
VDF(T)=1.5 ~ 1.8V
-
0.6
1.4
VDF(T)=1.9 ~ 3.0V
-
0.7
1.6
VDF(T)=3.1 ~ 5.5V
-
1.0
1.9
Supply Current 2 ISS2
VIN=VDFH×1.1
(*5)
, MRB=OPEN
μA
VDF(T)=1.5 ~ 1.8V
-
0.7
1.6
VDF(T)=1.9 ~ 3.0V
-
0.8
1.9
VDF(T)=3.1 ~ 5.5V
-
1.1
2.35
RESET
Output Current
IROUT1
V
IN
=1.65V
(*6)
, V
RESET
=0.5V(Nch) , MRB=OPEN
0.5 1.6 -
mA
V
IN
=2.0V
(*7)
, V
RESET
=0.5V(Nch) , MRB=OPEN
4.4 7.0 -
V
IN
=3.0V
(*8)
, V
RESET
=0.5V(Nch) , MRB=OPEN
7.0 9.0 -
V
IN
=4.0V
(*9)
, V
RESET
=0.5V(Nch) , MRB=OPEN
8.5 11.0 -
V
IN
=5.0V
(*10)
, V
RESET
=0.5V(Nch) , MRB=OPEN
9.0 12.0 -
V
IN
=6.0V, V
RESET
=0.5V(Nch) , MRB=OPEN
9.0 12.0 -
IROUT2
(*11)
V
IN
=0.7V, V
RESET
=0.2V(Pch) , MRB=OPEN
- -0.07 -0.001
mA
V
IN
=1.0V, V
RESET
=0.5V(Pch) , MRB=OPEN
- -0.4 -0.09
V
IN
=2.0V
(*12)
, V
RESET
=1.5V(Pch) , MRB=OPEN
- -2.0 -1.3
V
IN
=3.0V
(*13)
, V
RESET
=2.5V(Pch) , MRB=OPEN
- -3.0 -1.8
V
IN
=4.0V
(*14),
V
RESET
=3.5V(Pch) , MRB=OPEN
- -4.0 -2.5
V
IN
=5.0V
(*15)
, V
RESET
=4.5V(Pch) , MRB=OPEN
- -4.5 -3.0
RESET
Leakage
Current
CMOS
Output (P-ch)
ILEAK
VIN=6.0V, VRESET=0V, MRB=OPEN - -0.01 - μA
N-ch Open
Drain Output
V
IN
=V
DFH
×0.9, V
RESET
=6.0V, MRB=OPEN
- 0.01 0.15 μA
Temperature
Characteristics
ΔV
DFH
/
Topr
V
DFH
)
-40℃≦Topr85 - ±50 - ppm/
Detect Delay Time(*16) tDF
V
IN
=V
DFH
×1.1→V
DFH
×0.9
(*16)
, MRB=OPEN
- - E-3(*17) μs
Release Delay Time(*18) tDR
V
IN
=V
DFH
×0.9→V
DFH
×1.1
(*18)
, MRB=OPEN
E-2(*19) ms
MRB “Low” Level Voltage
(*20)
VMRL VDFH×1.1VIN6.0V VSS - 0.3 V
MRB “High” Level Voltage
(*20)
VMRH VDFH×1.1VIN6.0V 1.0 - 6.0 V
MRB pull-up Resistance
RMRB 0.4 0.8 3.0
Minimum MRB Pulse Width
TMRB
V
IN
=6.0V, Applied pulse to MRB pin, 6.0V→0V
150 - - ns
Ta=25
XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, XC6127NxxF/NxxG/NxxH/NxxJ/NxxK (Output Logic: Active High)
ELECTRICAL CHARACTERISTICS (Continued)
X06127 I ELECTRICAL CHARACTERISTICS (Continued) TOIflEX
9/30
XC6127
Series
ELECTRICAL CHARACTERISTICS (Continued)
(*1) V
DF (T)
: Nominal detect voltage
(*2) For the N-ch Open Drain, Rpull=100kΩ, Vpull-Up=VIN
Rpull: An External Pull-up resistor
Vpull-Up: Pull-up Voltage
(*3) VIN voltage for VOUT0.4V is under detect state.
(*4) For the detail value, please refer to Voltage Tablein P10.
(*5) VDF (T) = 5.5V where VIN=6.0V
(*6) For VDF (T) =1.5V products.
(*7) For VDF(T)1.8V products.
(*8) For VDF(T)2.7V products.
(*9) For VDF(T)3.6V products.
(*10) For VDF(T)4.6V products.
(*11) For the XC6127C (CMOS output)
(*12) For VDF(T)2.0V products.
(*13) For VDF(T)3.0V products.
(*14) For VDF(T)4.0V products.
(*15) For VDF(T)5.0V products.
(*16) A time between VIN=VDFH and VRESET=VDFH×0.45 when VIN falls.
(*17) For the detail value, please refer to Detect Delay Timein P11.
(*18) A time between VIN=VDFH+VHYS and VRESET=VDFH×0.55 when VIN rises.
(*19) For the detail value, please refer to Release Delay Timein P11.
(*20) For MRB pin, please do not apply the voltage below VSS.
M I ELECTRICAL CHARACTERISTICS (Continued)
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XC6127 Series
NOMINAL
DETECT
VOLTAGE
(V)
DETECT VOLTAGE
NOMINAL
DETECT
VOLTAGE
(V)
DETECT VOLTAGE
(V)
(V)
E-1
E-1
VDF(T) VDFL or VDFH VDF(T) VDFL or VDFH
MIN. MAX.
MIN. MAX.
1.50 1.4880 1.5120 4.10 4.0672 4.1328
1.60 1.5872 1.6128 4.20 4.1664 4.2336
1.70 1.6864 1.7136 4.30 4.2656 4.3344
1.80 1.7856 1.8144 4.40 4.3648 4.4352
1.90 1.8848 1.9152 4.50 4.4640 4.5360
2.00 1.9840 2.0160 4.60 4.5632 4.6368
2.10 2.0832 2.1168 4.70 4.6624 4.7376
2.20 2.1824 2.2176 4.80 4.7616 4.8384
2.30 2.2816 2.3184 4.90 4.8608 4.9392
2.40 2.3808 2.4192 5.00 4.9600 5.0400
2.50 2.4800 2.5200 5.10 5.0592 5.1408
2.60 2.5792 2.6208 5.20 5.1584 5.2416
2.70 2.6784 2.7216 5.30 5.2576 5.3424
2.80 2.7776 2.8224 5.40 5.3568 5.4432
2.90 2.8768 2.9232 5.50 5.4560 5.5440
3.00 2.9760 3.0240
3.10 3.0752 3.1248
3.20 3.1744 3.2256
3.30 3.2736 3.3264
3.40 3.3728 3.4272
3.50 3.4720 3.5280
3.60 3.5712 3.6288
3.70 3.6704 3.7296
3.80 3.7696 3.8304
3.90 3.8688 3.9312
4.00 3.9680 4.0320
ELECTRICAL CHARACTERISTICS (Continued)
Voltage Table 1
Voltage Table 2
XC6127 IELECTRICAL CHARACTERISTICS (Continued)
11/30
XC6127
Series
TYPE
RELEASE DELAY TIME
(ms)
E-2
tDR
MIN. TYP. MAX.
XC6127CxxA / XC6127NxxA 42.5 50 57.5
XC6127CxxB / XC6127NxxB 85 100 115
XC6127CxxC / XC6127NxxC 170 200 230
XC6127CxxD / XC6127NxxD 340 400 460
XC6127CxxE / XC6127NxxE 680 800 920
XC6127CxxF / XC6127NxxF 42.5 50 57.5
XC6127CxxG / XC6127NxxG 85 100 115
XC6127CxxH / XC6127NxxH 170 200 230
XC6127CxxJ / XC6127NxxJ 340 400 460
XC6127CxxK / XC6127NxxK 680 800 920
TYPE
DETECT DELAY TIME (μs)
E-3
tDF
MAX.
XC6127CxxF/CxxG/CxxH/CxxJ/CxxK 100
XC6127NxxF/NxxG/NxxH/NxxJ/NxxK 200
ELECTRICAL CHARACTERISTICS (Continued)
Release Delay Time Table
Detect Delay Time Table
M ITEST CIRCUITS 3 WC 9 fi fi
12/30
XC6127 Series
A
VIN
VSS
RESETB
RESET
MRB
A
VIN
VSS
RESETB
RESET
MRB
Rpull = 100 kohm
(Unused for the CMOS
output products)
V
V
VIN
VSS
RESETB
RESET
MRB
Rpull = 100 kohm
VIN
VSS
RESETB
RESET
MRB
Waveform Measurement Point
(Unused for the CMOS
output products)
TEST CIRCUITS
Circuit
Circuit
Circuit
Circuit
X66127 ITEST CIRCUITS (Continued) TOIEEX
13/30
XC6127
Series
VIN
VSS
RESETB
RESET
MRB
A
Rpull = 100 kohm
V
VIN
VSS
RESETB
RESET
MRB
V
(Unused for the CMOS
output products)
Rpull = 100 kohm
VIN
VSS
RESETB
RESET
MRB
(Unused for the CMOS
output products)
Waveform Measurement Point
Waveform
Measurement
Point
TEST CIRCUITS (Continued)
Circuit
Circuit
Circuit
M IOPERATIONAL EXPLANATION 1. Detect/ Release operafion using X06127CxxA/CxxB/CxxC/CxxD/CxxE % %
14/30
XC6127 Series
1. Detect / Release operation using XC6127CxxA/CxxB/CxxC/CxxD/CxxE, XC6127NxxA/NxxB/NxxC/NxxD/NxxE
(Output Logic: Active Low)
Typical Application Circuit
Timing Chart
OPERATIONAL EXPLANATION
VIN
V
IN
RESETB
V
SS
Rpull
XC6127 Series
VOUT
MRB
(Unused for the CMOS
output products)
Input Voltage: V
IN
Release Voltage: V
DR
=V
DFL
+V
HYS
Detect Voltage: V
DFL
Minimum Operating Voltage(0.7V)
Ground VoltageV
SS
Ground VoltageV
SS
Release Delay Time:
DR
Detect Delay Time:
DF
Output Voltage: V
RESETB
A timing chart is used to explain the operation of the typical application circuit when MRB is open.
In the initial state, an input voltage (VIN) higher than the release voltage (VDR) is applied, and then VIN gradually falls.
While the input voltage (VIN) is higher than the detect voltage (VDFL), an output voltage (VRESETB) equal to the input voltage (VIN) goes out.
*In the case of an N-ch open drain output product, the RESETB pin is in a high-impedance state, and if the output is pulled up, the output
voltage (VRESETB) is equal to the pull-up voltage.
②③After the elapse of the detect delay time (tDF) that starts when the input voltage (VIN) falls below the detect voltage (VDFL), an output voltage
(VRESETB) equal to the ground voltage (VSS) goes out (detection state).
*This is the same on the N-ch open drain output product.
The input voltage (VIN) drops further, and if it falls below the minimum operating voltage (0.7V), the output becomes undefined state.
*When an N-ch open drain output product is used and the output pin is pulled up, an output voltage (VRESETB) equal to the pull-up voltage
may be output.
The input voltage (VIN) rises past the minimum operating voltage (0.7V), and until it reaches the release voltage (VDR), the output voltage
(VRESETB) is equal to the ground voltage.
From the time that the input voltage (VIN) becomes higher than the release voltage (VDR) until the release delay time (tDR) elapses, the output
voltage (VRESETB) remains at the ground voltage due to the delay circuit.
After the release delay time (tDR) elapses, the output voltage (VRESETB) is equal to the input voltage (VIN) (release state).
*In the case of an N-ch open drain output product, the RESETB pin will be in a high impedance state like . If the output is pulled up, an
output voltage (VRESETB) equal to the pull-up voltage will be output.
The difference between the release voltage (VDR) and the detect voltage (VDFL) is the hysteresis width (VHYS).
X66127 I OPERATIONAL EXPLANATION (Continued)
15/30
XC6127
Series
2. XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, XC6127NxxF/NxxG/NxxH/NxxJ/NxxK (Output Logic: Active High)
Typical Application Circuit
Timing Chart
OPERATIONAL EXPLANATION (Continued)
V
IN
V
IN
RESET
V
SS
XC6127 Series
V
OUT
MRB
Rpull
(Unused for the CMOS
output products)
① ③ ④ ⑤
Release Delay Time:
DR
Detect Delay Time:
DF
Ground VoltageV
SS
Input Voltage: V
IN
Detect Voltage: V
DFH
Minimum Operating Voltage(0.7V)
Ground VoltageV
SS
Release Voltage: V
DR
=V
DFH
+V
HYS
Output Voltage: V
RESET
A timing chart is used above to explain the operation of the typical application circuit when MRB is open.
In the initial state, an input voltage (VIN) higher than the release voltage (VDR) is applied, and then VIN gradually falls.
While the input voltage (VIN) is higher than the detect voltage (VDFH), an output voltage (VRESET) equal to the ground voltage (VSS) goes
out.
*This is the same on the N-ch open drain output product.
②③After the elapse of the detect delay time (tDF) that starts when the input voltage (VIN) falls below the detect voltage (VDFH), the output
voltage (VRESET) is equal to the input voltage (VIN) (detection state).
*In the case of an N-ch open drain output product, the RESET pin is in a high-impedance state, and if the output is pulled up, the output
voltage (VRESET) is equal to the pull-up voltage.
The input voltage (VIN) drops further, and if it falls below the minimum operating voltage (0.7V), the output becomes undefined state.
The input voltage (VIN) rises past the minimum operating voltage (0.7V), and until it reaches the release voltage (VDR), the output voltage
(VRESET) is equal to the VIN voltage.
*In the case of an N-ch open drain output product, the RESET pin is in a high-impedance state, and if the output is pulled up, the output
voltage (VRESET) is equal to the pull-up voltage.
From the time that the input voltage (VIN) becomes higher than the release voltage (VDR) until the release delay time (tDR) elapses, the
output voltage (VRESET) remains equal to the VIN voltage due to the delay circuit.
After the release delay time (tDR) elapses, the output voltage (VRESET) is equal to the ground voltage (VSS) (release state).
The difference between the release voltage (VDR) and the detect voltage (VDFH) is the hysteresis width (VHYS).
M I OPERATIONAL EXPLANATION (Continued) 3. MRS Pin
16/30
XC6127 Series
3. MRB Pin
Timing Chart
OPERATIONAL EXPLANATION (Continued)
The output pin signal can be forcibly changed to the detect state by an input signal to the MRB pin.
The operation of the circuit at MRB signal input is explained using a timing chart.
When an H level (VMRH) signal and then an L (or less) level (VMRL) signal are input to the MRB input voltage (VMRB) with a voltage equal to or
higher than VDR applied to the input voltage (VIN), the output pin outputs release state (*1) and then detect state (*2) signals.
During the release delay time (tDR) after the MRB input voltage (VMRB) changes from the L level (VMRL) to the H level (VMRH), the output pin
maintains the detection state. After the release delay time (tDR) elapses, the output pin outputs the release state signal.
(*1) The output voltage in the release state is indicated below by product type.
XC6127xxxA/xxxB/xxxC/xxxD/xxxE types (output logic: Active Low) : Input voltage (VIN) (*3)
XC6127xxxF/xxxG/xxxH/xxxJ/xxxK types (output logic: Active High) : Ground voltage (VSS)
(*2) The output voltage in the detect state is indicated below by product type.
XC6127xxxA/xxxB/xxxC/xxxD/xxxE types (output logic: Active Low) : Ground voltage (VSS)
XC6127xxxF/xxxG/xxxH/xxxJ/xxxK types (output logic: Active High) : Input voltage (VIN) (*3)
(*3) On an N-ch open drain output product, if the output is pulled up, the output voltage is the pull-up voltage.
(*4) A pull-up resistance (RMRB) is built-
in between the MRB pin and the VIN pin, and thus if a voltage is applied to the MRB pin, current
will flow from the VIN pin to the MRB pin.
(*5) The voltage input to the MRB pin should be within the range VSS to 6.0 V.
Release Delay Time:
DR
Ground VoltageV
SS
Input Voltage: V
IN
Detect Voltage: V
DFL
or V
DFH
Ground VoltageV
SS
Release Voltage: V
DR
Output Voltage: V
RESET
Ground VoltageV
SS
Release Delay Time:
DR
Output Voltage: V
RESETB
MRB Input Voltage: V
MRB
MRB “High” Level Voltage: V
MRH
MRB “Low” Level Voltage: V
MRL
Ground VoltageV
SS
X06127 INOTES ON USE Usmg XC6127NxxA/NxxB/NxxC/NxxD/NXXE oulgut \ogic, Aclwe Low Usmq theC6127NxxF/NxxG/NxxH/NxxJ/NXXK (cutout loaic, Acme Hiqh) TOIflEX 17/30
17/30
XC6127
Series
1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is liable to
malfunction should the ratings be exceeded.
2. Note that there is a possibility of malfunctioning if the input voltage changes sharply or undergoes repeated, cyclical changes.
3. If the resistance RIN is connected between the VIN pin and the power supply VDD, the voltage drop due to the flow through current in the internal
circuit and RIN may cause oscillation when release takes place. When using the CMOS output product, oscillation due to RIN and the flow
through current may occur without relation to release and detection, and thus RIN should not be connected.
4. When N-ch open drain output is used, the output voltage at detection is determined by the pull-up resistance connected to the output pin. Select
the resistance based on the following considerations:
Using XC6127NxxA/NxxB/NxxC/NxxD/NxxE (output logic: Active Low)
At detection: VRESETB= (Vpull-Up)/ (1+Rpull/RON)
Vpull-Up: Voltage after pull-up
RON (*1): ON resistance of N-ch driver (calculated from VRESETB/IRBOUT1 in electrical characteristics) (*3)
Example calculation:
When VIN=2.0V (*2), RON=0.5/4.4×10-3114Ω(MAX.). If you wish to make the VRESETB voltage at detection 0.1V or lower with Vpull-Up=3.0V,
Rpull=(Vpull-Up /VRESETB-1)×RON=(3/0.1-1)×1143.3kΩ, and thus to make the output voltage at detection 0.1V or less under the above
conditions, the pull-up resistance must be 3.3kΩ or higher.
(*1) The smaller VIN is, the larger RON becomes.
(*2) When selecting VIN, calculate using the lowest value of the input voltage range you will use.
(*3) IRBOUT1 specified in the electrical characteristics is the value at Ta=25. IRBOUT1 varies depending on the ambient temperature.
To select the pull-up resistance taking ambient temperature into account, please consult us.
At release: VRESETB = (Vpull-Up)/ (1+Rpull/ROFF)
Vpull-Up: Voltage after pull-up
ROFF: Resistance value 40MΩ(MIN.) when N-ch driver is OFF (calculated from VRESETB/ILEAK in electrical characteristics)
Calculation example:
If you wish to make VRESETB 5.99V or higher with Vpull-Up=6.0V
Rpull=(Vpull-Up/VRESETB-1)×ROFF=(6/5.99-1)×40×10666kΩ, and thus to make the output voltage 5.99V or higher at release under the above
conditions, the pull-up resistance must be 66kΩ or less.
Using theC6127NxxF/NxxG/NxxH/NxxJ/NxxK (output logic: Active High)
At detectionVRESET=(Vpull-Up)/(1+Rpull/ROFF)
Vpull-Up: Voltage after pull-up
ROFF: When the N-ch driver is OFF, the resistance is 40MΩ(MIN.) (calculated from VRESET/ILEAK in the electrical characteristics)
Calculation example:
If you wish to make VRESET 5.99V or higher with Vpull-Up = 6.0V
Rpull=(Vpull-Up/VRESET-1)×ROFF=(6/5.99-1)×40×10666kΩ and thus to make the output voltage 5.99V or higher at detection under the above
conditions, the pull-up resistance must be 66kΩ or less.
At releaseVRESET=(Vpull-Up)/(1+Rpull/RON)
Vpull-UpVoltage after pull-up
RON(*1)ON resistance of N-ch driver (calculated from VRESET/IROUT1 in the electrical characteristics)(*3)
Calculation example:
When VIN=2.0V (*2), RON=0.5/4.4×10-3114Ω (MAX.). If you wish to make the VRESET voltage 0.1V or lower at detection with Vpull-Up=3.0 V,
Rpull=(Vpull-Up /VRESET-1)×RON=(3/0.1-1)×1143.3kΩ and thusto make the output voltage 0.1V or lower at release under the above
conditions, the pull-up resistance must be 3.3kΩ or higher.
(*1) The smaller VIN is the larger RON becomes.
(*2) When selecting VIN, calculate using the lowest value of the input voltage range you will be using.
(*3) IROUT1 specified in the electrical characteristics is the value at Ta=25. IROUT1 varies depending on the ambient temperature.
To select the pull-up resistance taking ambient temperature into account, please consult us.
NOTES ON USE
NOTES ON USE(Continued) 5. ”the input swgnal to the MRS pin is forced to be sel to the delecflon slate, Ihe d ,_ V VpuH _\ \ Efim \ .‘ Ma'unnng HM % mm H, MCJ an: ,~ _ we: :53 5mm —p my ‘ L RESEYB (RVMM n Type)
18/30
XC6127 Series
5. If the input signal to the MRB pin is forced to be set to the detection state, the detection signal may be erroneously pulse output to the output
within the period until the output pin constantly outputs the detection signal. (See the figure below)
When taking the above measures, connect an output capacitor to the output terminal and smooth the output signal. Please connect the output
capacitance (Cfilter) of 0.1μF or more
6. We are striving to improve our products and reliability. However, in the unlikely event of an emergency, we recommend fail-safe design and
aging treatment, as well as sufficient safety design on the device or system.
NOTES ON USE(Continued)
Example of incorrect output signal (Active Low Type)
Counter measure circuit example (Nch-Open Drain Type)
X06127 ITYPICAL PERFORMANCE CHARACTERISTICS (1) Supply Currem vs. Input Voltage (2) Supply Current vs. Ambient Temperature | | | 7 7 7" vm :VDFL / v‘u :VDFL n/ / /€7' f/ /// | | Input Voltage : VMV) Amman: Temperamre (”c) I ‘ ‘ / ,7: v :'V ‘ — v :v, , if 7 ‘ if 4 y‘_ .% / /:’ ’ 4 , , 4 ‘ ’ A J _ ’ ’ ’ ’ I I Input Voltage: VMV) Arrbienl Termeralure: (”0) 2) / 1 / /U , , , , ’ ’ ’ / , — / , , // _ // i — — — vIN =v _ _ v _ . — ‘ \ \ |
19/30
XC6127
Series
(1) Supply Current vs. Input Voltage (2) Supply Current vs. Ambient Temperature
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0123456
Supply Current : I
SS
(μA )
Input Voltage : V
IN
(V)
VDF(T)=2.7V
-40
25
85
V
IN
=0V→6.0V→0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
- 50 - 25 025 50 75 100
Supply Current : I
SS
(μA )
Ambient Temperature : ()
VDF(T)=2.7V
VIN=VDFL*0.9
VIN=VDFL*1.1
DFL
DFL
IN
IN
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 1 234 5 6
Supply Current : I
SS
(μA )
Input Voltage : V
IN
(V)
VDF(T)=1.5V
-40
25
85
V
IN
=0V→6.0V→0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
- 50 - 25 025 50 75 100
Supply Current : I
SS
(μA )
Ambient Temperature : ()
VDF(T)=1.5V
VIN=VDFL*0.9
VIN=VDFL*1.1
IN
IN
DFL
DFL
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0123456
Supply Current : I
SS
(μA )
Input Voltage : V
IN
(V)
VDF(T)=5.5V
-40
25
85
V
IN
=0V→6.0V→0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-50 -25 025 50 75 100
Supply Current : I
SS
(μA )
Ambient Temperature : ()
VDF(T)=5.5V
VIN=VDFL*0.9
VIN=6.0V
DFL
IN
IN
TYPICAL PERFORMANCE CHARACTERISTICS
M ITYPICAL PERFORMANCE CHARACTERISTICS(Continued) ———-an _ -50 -25 0 25 50 75 100 fifi— \ x ———V 7V
20/30
XC6127 Series
(3) Output Voltage vs. Input Voltage1 (4) Detect Voltage, Release Voltage
vs. Ambient Temperature
TYPICAL PERFORMANCE CHARACTERISTICS(Continued)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.4 1.5 1.6 1.7 1.8
Output Voltage : VOUT (V)
VDF(T)=1.5V
-40
25
85
1.3
1.4
1.5
1.6
1.7
1.8
- 50 - 25 025 50 75 100
etect Voltage, Release Voltage : VDFL, VDR (V)
VDF(T)=1.5V
VDFL
VDR
DFL
DR
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
2.4 2.6 2.8 33.2
Output Voltage : V
OUT
(V)
Input Voltage : V
IN
(V)
VDF(T)=2.7V
-40
25
85
2.5
2.6
2.7
2.8
2.9
3.0
- 50 - 25 025 50 75 100
Detect Voltage, Release Voltage : V
DFL
, V
DR
(V)
Ambient Temperature : ()
VDF(T)=2.7V
VDFL
VDR
DFL
DR
0.0
1.0
2.0
3.0
4.0
5.0
6.0
4.8 55.2 5.4 5.6 5.8 6
Output Voltage : V
OUT
(V)
Input Voltage : V
IN
(V)
V
DF(T)
=5.5V
-40
25
85
5.4
5.5
5.6
5.7
5.8
5.9
6.0
- 50 - 25 025 50 75 100
Detect Voltage, Release Voltage : V
DFL
, V
DR
(V)
Ambient Temperature : ()
VDF(T)=5.5V
VDFL
VDR
DFL
DR
VDF (T) =5.5V
X66127 ITYPICAL PERFORMANCE CHARACTERISTICS(Continued) (5) Omput Voltage vs. InpmVonageZ // Input Voltage : \/‘N (V)
21/30
XC6127
Series
(5) Output Voltage vs. Input Voltage2
(6) Output Current (Nch Driver) vs. Input Voltage (7) Output Current (Pch Driver) vs. Input Voltage
(8) Leakage Current vs. Ambient temperature
0
4
8
12
16
20
0123456
Output Current : I
OUT
( mA )
Input Voltage : V
IN
(V)
VDF(T)=5.5V
-40
25
85
V
OUT
=0.5V
7
6
5
4
3
2
1
0
0 1 2 3 4 5 6
Output Current : I
OUT
( mA )
Input Voltage : V
IN
(V)
VDF(T)=1.5V
-40
25
85
V
OUT
=V
IN
-0.5V
TYPICAL PERFORMANCE CHARACTERISTICS(Continued)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
00.2 0.4 0.6 0.8 11.2 1.4
Output Voltage : V
OUT
(V)
Input Voltage : V
IN
(V)
CMOS Output
-0
25
85
0
1
2
3
4
5
6
7
00.2 0.4 0.6 0.8 11.2 1.4
Output Voltage : V
OUT
(V)
Input Voltage : V
IN
(V)
N-ch Open Drain Output
-0
25
85
Vpull-Up=6.5V, Rpull=100kΩ
0
0.01
0.02
0.03
0.04
0.05
25 35 45 55 65 75 85
Leakage Current : ILeak (μA)
Ambient Temperature : ()
N-ch Open Drain Output
VIN=VOUT =6.0V
M wwwjorexse om/‘echmca\-suggorI/Qackages SOT»25 PKG SOT-25 Power stsigafion SSOT»24 PKG SSDT—24 Power stsigafion USPN-4 PKG USPN-4 Power Dissigaxion
22/30
XC6127 Series
PACKAGING INFORMATION
For the latest package information go to, www.torexsemi.com/technical-support/packages
PACKAGE OUTLINE / LAND PATTERN THERMAL CHARACTERISTICS
SOT-25 SOT-25 PKG
Standard Board
SOT-25 Power Dissipation
JESD51-7 Board
SSOT-24 SSOT-24 PKG
Standard Board
SSOT-24 Power Dissipation
JESD51-7 Board
USPN-4 USPN-4 PKG Standard Board USPN-4 Power Dissipation
XC6127
23/30
XC6127
Series
MARKING RULE
USPN-4
represents product series and output configuration.
MARK OUTPUT CONFIGURATION PRODUCT SERIES
F CMOS XC6127C*****-G
H
Nch
XC6127N*****-G
represents detect voltage.
MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V)
A
1.5
1.6
K
2.9
3.0
T
4.3
4.4
B
1.7
1.8
L
3.1
3.2
U
4.5
4.6
C
1.9
2.0
M
3.3
3.4
V
4.7
4.8
D 2.1 2.2 N 3.5 3.6 X 4.9 5.0
E
2.3
2.4
P
3.7
3.8
Y
5.1
5.2
F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4
H 2.7 2.8 S 4.1 4.2 0 5.5 -
represents detect voltage range and release delay time / detect logic.
MARK
DETECT
VOLTAGE [V]
RELEASE DELAY TIME/
DETECT LOGIC
PRODUCT SERIES
A
Odd number
50ms/Low
XC6127*15A**-G
XC6127*55A**-G
B 100ms/Low XC6127*15B**-G XC6127*55B**-G
C
200ms/Low
XC6127*15C**-G
XC6127*55C**-G
D
400ms/Low
XC6127*15D**-G
XC6127*55D**-G
E 800ms/Low XC6127*15E**-G XC6127*55E**-G
F
50ms/High
XC6127*15F**-G XC6127*55F**-G
H
100ms/High
XC6127*15G**-G
XC6127*55G**-G
K 200ms/High XC6127*15H**-G XC6127*55H**-G
L 400ms/High XC6127*15J**-G XC6127*55J**-G
M
800ms/High
XC6127*15K**-G
XC6127*55K**-G
N
Even number
50ms/Low
XC6127*16A**-G
XC6127*54A**-G
P 100ms/Low XC6127*16B**-G XC6127*54B**-G
R
200ms/Low
XC6127*16C**-G
XC6127*54C**-G
S
400ms/Low
XC6127*16D**-G
XC6127*54D**-G
T 800ms/Low XC6127*16E**-G XC6127*54E**-G
U
50ms/High
XC6127*16F**-G XC6127*54F**-G
V
100ms/High
XC6127*16G**-G
XC6127*54G**-G
X 200ms/High XC6127*16H**-G XC6127*54H**-G
Y 400ms/High XC6127*16J**-G XC6127*54J**-G
Z
800ms/High
XC6127*16K**-G
XC6127*54K**-G
represents production lot number.
0 to 9, A to Z repeated. (G, I, J, O, Q, W excepted.)
* No character inversion used.
1 2
3
① ②
③ ④
4
M IMARKING RULE (Continued) (Wixh me oriemafion bar a: me mp) (Wilh xhe oriemaxion bar ax me bonom)
24/30
XC6127 Series
SSOT-24
-1 represents product series and detect voltage range, output configuration.
MARK
OUTPUT
CONFIGURATION
DETECT
VOLTAGE [V]
RELEASE DELAY
TIME/ DETECT LOGIC
PRODUCT SERIES
5
CMOS
Odd
number
50ms/Low
XC6127C15A**-G
XC6127C55A**-G
6 100ms/Low XC6127C15B**-G XC6127C55B**-G
7
200ms/Low
XC6127C15C**-G XC6127C55C**-G
8
400ms/Low
XC6127C15D**-G
XC6127C55D**-G
9 800ms/Low XC6127C15E**-G XC6127C55E**-G
A 50ms/High XC6127C15F**-G XC6127C55F**-G
B
100ms/High
XC6127C15G**-G
XC6127C55G**-G
C
200ms/High
XC6127C15H**-G
XC6127C55H**-G
D 400ms/High XC6127C15J**-G XC6127C55J**-G
E
800ms/High
XC6127C15K**-G
XC6127C55K**-G
F
Even
number
50ms/Low
XC6127C16A**-G
XC6127C54A**-G
H 100ms/Low XC6127C16B**-G XC6127C54B**-G
K
200ms/Low
XC6127C16C**-G XC6127C54C**-G
N
400ms/Low
XC6127C16D**-G
XC6127C54D**-G
P 800ms/Low XC6127C16E**-G XC6127C54E**-G
R 50ms/High XC6127C16F**-G XC6127C54F**-G
S
100ms/High
XC6127C16G**-G
XC6127C54G**-G
T
200ms/High
XC6127C16H**-G
XC6127C54H**-G
U 400ms/High XC6127C16J**-G XC6127C54J**-G
V
800ms/High
XC6127C16K**-G
XC6127C54K**-G
* The products of CMOS output configuration are shipped in the package having the orientation bar marked in the top.
MARKING RULE (Continued)
SSOT-24
(With the orientation bar at the top)
SSOT-24
(With the orientation bar at the bottom)
1
2
3
4
1
2
3
4
XC6127 I MARKING RULE (Continued)
25/30
XC6127
Series
-2 represents product series and detect voltage range, output configuration.
MARK
OUTPUT
CONFIGURATIO
N
DETECT
VOLTAGE [V]
RELEASE DELAY TIME/
DETECT LOGIC 品名表記例
0
Nch
Odd
number
50ms/Low
XC6127N15A**-G
XC6127N55A**-G
1
100ms/Low
XC6127N15B**-G
XC6127N55B**-G
2
200ms/Low
XC6127N15C**-G
XC6127N55C**-G
3
400ms/Low
XC6127N15D**-G
XC6127N55D**-G
4
800ms/Low
XC6127N15E**-G
XC6127N55E**-G
5
50ms/High
XC6127N15F**-G
XC6127N55F**-G
6
100ms/High
XC6127N15G**-G
XC6127N55G**-G
7
200ms/High
XC6127N15H**-G
XC6127N55H**-G
8
400ms/High
XC6127N15J**-G
XC6127N55J**-G
9
800ms/High
XC6127N15K**-G
XC6127N55K**-G
A
Even
number
50ms/Low XC6127N16A**-G XC6127N54A**-G
B
100ms/Low
XC6127N16B**-G
XC6127N54B**-G
C
200ms/Low
XC6127N16C**-G
XC6127N54C**-G
D 400ms/Low XC6127N16D**-G XC6127N54D**-G
E
800ms/Low
XC6127N16E**-G
XC6127N54E**-G
F
50ms/High
XC6127N16F**-G
XC6127N54F**-G
H
100ms/High
XC6127N16G**-G
XC6127N54G**-G
K
200ms/High
XC6127N16H**-G
XC6127N54H**-G
L
400ms/High
XC6127N16J**-G
XC6127N54J**-G
M
800ms/High
XC6127N16K**-G
XC6127N54K**-G
* The products of Nch output configuration are shipped in the package having the orientation bar marked in the bottom.
represents detect voltage.
MARK
DETECT VOLTAGE(V)
MARK
DETECT VOLTAGE(V)
MARK
DETECT VOLTAGE(V)
A
1.5
1.6
K
2.9
3.0
T
4.3
4.4
B
1.7
1.8
L
3.1
3.2
U
4.5
4.6
C
1.9
2.0
M
3.3
3.4
V
4.7
4.8
D
2.1
2.2
N
3.5
3.6
X
4.9
5.0
E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2
F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4
H 2.7 2.8 S 4.1 4.2 0 5.5 -
③④ represents production lot number. 0109, 0A0Z, 119Z, A1A9, AAAZB1ZZ repeated.
(G, I, J, O, Q, W excluded.)
* No character inversion used.
MARKING RULE (Continued)
M IMARKING RULE (Continued) SOT»25(Under do!)
26/30
XC6127 Series
SOT-25
represents product series and output configuration.
* SOT-25 with the under-dot marking is used.
represents detect voltage.
represents detect voltage range and release delay time / detect logic.
③④ represents production lot number. 0109, 0A0Z, 119Z, A1A9, AAAZB1ZZ repeated.
(G, I, J, O, Q, W excluded.)
* No character inversion used.
MARK OUTPUT
CONFIGURATION PRODUCT SERIES
5 CMOS XC6127C*****-G
6
Nch
XC6127N*****-G
MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V) MARK DETECT VOLTAGE(V)
A 1.5 1.6 K 2.9 3.0 T 4.3 4.4
B 1.7 1.8 L 3.1 3.2 U 4.5 4.6
C 1.9 2.0 M 3.3 3.4 V 4.7 4.8
D 2.1 2.2 N 3.5 3.6 X 4.9 5.0
E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2
F
2.5
2.6
R
3.9
4.0
Z
5.3
5.4
H 2.7 2.8 S 4.1 4.2 0 5.5 -
MARK DETECT VOLTAGE
[V]
RELEASE DELAY TIME/
DETECT LOGIC PRODUCT SERIES
A
Odd
number
50ms/Low
XC6127*15A**-G
XC6127*55A**-G
B
100ms/Low
XC6127*15B**-G
XC6127*55B**-G
C
200ms/Low
XC6127*15C**-G
XC6127*55C**-G
D
400ms/Low
XC6127*15D**-G
XC6127*55D**-G
E
800ms/Low
XC6127*15E**-G
XC6127*55E**-G
F
50ms/High
XC6127*15F**-G
XC6127*55F**-G
H
100ms/High
XC6127*15G**-G
XC6127*55G**-G
K
200ms/High
XC6127*15H**-G
XC6127*55H**-G
L 400ms/High XC6127*15J**-G XC6127*55J**-G
M
800ms/High
XC6127*15K**-G
XC6127*55K**-G
N
Even
number
50ms/Low
XC6127*16A**-G
XC6127*54A**-G
P 100ms/Low XC6127*16B**-G XC6127*54B**-G
R
200ms/Low
XC6127*16C**-G
XC6127*54C**-G
S
400ms/Low
XC6127*16D**-G
XC6127*54D**-G
T
800ms/Low
XC6127*16E**-G
XC6127*54E**-G
U
50ms/High
XC6127*16F**-G
XC6127*54F**-G
V
100ms/High
XC6127*16G**-G
XC6127*54G**-G
X
200ms/High
XC6127*16H**-G
XC6127*54H**-G
Y
400ms/High
XC6127*16J**-G
XC6127*54J**-G
Z
800ms/High
XC6127*16K**-G
XC6127*54K**-G
1
2
3
5
4
拡大
SOT-25(Under dot)
MARKING RULE (Continued)
X06127
27/30
XC6127
Series
1. The product and product specifications contained herein are subject to change without notice to
improve performance characteristics. Consult us, or our representatives before use, to confirm that
the information in this datasheet is up to date.
2. The information in this datasheet is intended to illustrate the operation and characteristics of our
products. We neither make warranties or representations with respect to the accuracy or
completeness of the information contained in this datasheet nor grant any license to any intellectual
property rights of ours or any third party concerning with the information in this datasheet.
3. Applicable export control laws and regulations should be complied and the procedures required by
such laws and regulations should also be followed, when the product or any information contained in
this datasheet is exported.
4. The product is neither intended nor warranted for use in equipment of systems which require
extremely high levels of quality and/or reliability and/or a malfunction or failure which may cause loss
of human life, bodily injury, serious property damage including but not limited to devices or equipment
used in 1) nuclear facilities, 2) aerospace industry, 3) medical facilities, 4) automobile industry and
other transportation industry and 5) safety devices and safety equipment to control combustions and
explosions. Do not use the product for the above use unless agreed by us in writing in advance.
5. Although we make continuous efforts to improve the quality and reliability of our products;
nevertheless Semiconductors are likely to fail with a certain probability. So in order to prevent personal
injury and/or property damage resulting from such failure, customers are required to incorporate
adequate safety measures in their designs, such as system fail safes, redundancy and fire prevention
features.
6. Our products are not designed to be Radiation-resistant.
7. Please use the product listed in this datasheet within the specified ranges.
8. We assume no responsibility for damage or loss due to abnormal use.
9. All rights reserved. No part of this datasheet may be copied or reproduced unless agreed by Torex
Semiconductor Ltd in writing in advance.
TOREX SEMICONDUCTOR LTD.

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