TPS1101, TPS1101Y Datasheet by Texas Instruments

Available in Ultrathin TSSOP Package (PW) ESD Protection Up to 2 kV per MlL-STD-883C, Method 3015 descrip "on PRODuc'liolt mu Inl Producls mntnrm tn sueolmlmns per the term! or rem irlxlmmenix Stun-11rd wnmmy Prnflucilan preeesslrlg does nothesesuuly include lestlhg el .ll parameters The TPS1101 is a single, IowerS on): Pachannel, enhancementrmode MOSFET. he device has been optimized for 37V or 57V power distribution in batteryrpowered systems by means of the Texas Instruments LinBiCMOS process. With a maximum VGSth) 0171.5 V and an IDSS of only 0.5 pA, the TP 1101 is the ideal highrside switch lor lowrvoltage, portable batteryrmanagement systems where maximizing battery life is a primary concern. The low rpswn) and excellent ac characteristics (rise time 5.5 ns typical) of the TPS1101 make it the logical choice for lowrvoltage switching applications such as power switches for pulserwidthrmodulated (PWM) controllers or motor/bridge drivers. The ultrathin thin shrink smallroutline package or TSSOP (PW) version fits in heightrrestricted places where other Pachannel MOSFETS cannot. The size advantage is especially important where board height restrictions do not allow lor an smallroutline integrated circuit (SOIC) package. Such applications include notebook computers, personal digital assistants (PDAs), cellular GATE DRAIN r—u—u—u—t SOURCE SOURCE SOURCE GATE NC telephones, and PCMCIA cards. For existing designs, the Dapackaged version has a pinout common with other Pachannel MOSFETS in SOIC packages. AVAILABLE OPTIONS PACKAGED DEVICEST CHIP FORM TJ SMALL OUTLINE TSSOP (V) (D) (PW) r40“Ct0150°C TPSitDtD TPSthi FWLE TPSitOtY TThe D package is avaliabie taped and reeled. Add an R suttlx to devlce type (eg, TPS1101 DR), The PW package is only avaliable lettrend taped and reeled (lndlcated by the LE sutilx on the device type. e p. TPSiiDiPWLE), The Chlp term is tested at zsac. Please be aware that art lmportant notlce concernlng avallablllly, standard warranty and use In crltlcal appllcatlons ol Texas instruments semlconductor products and dlscialmers thereto appears at the end at thls data sheet, LlnBICMOS ls a trademark at Texas instruments Incorporated, *9 TEXAS stlah ix current .s m uuhllmmn m. Copyrlght 1995, Texas lrlstrumertls Incorporated INSTRUMENTS POST OFFICE aox $55303 - DALLAS TEXAS 75285 t
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Low rDS(on) . . . 0.09 Typ at VGS = –10 V
3 V Compatible
Requires No External VCC
TTL and CMOS Compatible Inputs
VGS(th) = –1.5 V Max
Available in Ultrathin TSSOP Package (PW)
ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015
description
The TPS1101 is a single, low-rDS(on), P-channel,
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of the
Texas Instruments LinBiCMOS process. With a
maximum VGS(th) of –1.5 V and an IDSS of only
0.5 µA, the TPS1101 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low rDS(on) and excellent ac
characteristics (rise time 5.5 ns typical) of the
TPS1101 make it the logical choice for
low-voltage switching applications such as power
switches for pulse-width-modulated (PWM)
controllers or motor/bridge drivers.
The ultrathin thin shrink small-outline package or
TSSOP (PW) version fits in height-restricted
places where other P-channel MOSFETs cannot.
The size advantage is especially important where
board height restrictions do not allow for an
small-outline integrated circuit (SOIC) package.
Such applications include notebook computers,
personal digital assistants (PDAs), cellular
telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other
P-channel MOSFETs in SOIC packages.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP FORM
TJSMALL OUTLINE
(D) TSSOP
(PW)
CHIP
FORM
(Y)
–40°C to 150°C TPS1101D TPS1101PWLE TPS1101Y
The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1101DR). The PW package is only available left-end taped and reeled (indicated by
the LE suffix on the device type; e.g., TPS1101PWLE). The chip form is tested at 25°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
1
2
3
4
8
7
6
5
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
GATE
NC
NC
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
NC
PW PACKAGE
(TOP VIEW)
NC – No internal connection
D PACKAGE
PW PACKAGE
r ————— ‘l | | I L ,,,,, J NOTE A. For an applxcamns‘ an source connectedandal‘dramlermmal *9 TEXAS INSTRUMENTS POST OFFICE sex 555
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
schematic
NOTE A: For all applications, all source terminals should be
connected and all drain terminals should be connected.
SOURCE
DRAIN
GATE
ESD-
Protection
Circuitry
TPS1101Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1101. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
80
92
TPS1100Y
(2)
(6)
(1)
(3)
(7)
(8)
(5)(4)
DRAINSOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
(2)
(1) (3) (4)
(6)
(7)(8) (5)
D package PW package D package PW package Contmua-sdram current {T 150%?) 1»: D package PW package D package PW package V TEXAS INSTRUMENTS
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
UNIT
Drain-to-source voltage, VDS – 15 V
Gate-to-source voltage, VGS 2 or – 15 V
D
p
ackage
TA = 25°C±0.62
VGS =27V
D
package
TA = 125°C±0.39
V
GS = –
2
.
7
V
PW
p
ackage
TA = 25°C±0.61
PW
package
TA = 125°C±0.38
D
p
ackage
TA = 25°C±0.88
VGS =3V
D
package
TA = 125°C±0.47
V
GS = –
3
V
PW
p
ackage
TA = 25°C±0.86
Continuous drain current (TJ= 150
°
C) ID
PW
package
TA = 125°C±0.45
A
Contin
u
o
u
s
drain
c
u
rrent
(T
J =
150°C)
,
I
D
D
p
ackage
TA = 25°C±1.52
A
VGS =45V
D
package
TA = 125°C±0.71
V
GS = –
4
.
5
V
PW
p
ackage
TA = 25°C±1.44
PW
package
TA = 125°C±0.67
D
p
ackage
TA = 25°C±2.30
VGS =10V
D
package
TA = 125°C±1.04
V
GS = –
10
V
PW
p
ackage
TA = 25°C±2.18
PW
package
TA = 125°C±0.98
Pulsed drain current, IDTA = 25°C±10 A
Continuous source current (diode conduction), ISTA = 25°C 1.1 A
Storage temperature range, Tstg 55 to 150 °C
Operating junction temperature range, TJ40 to 150 °C
Operating free-air temperature range, TA40 to 125 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Maximum values are calculated using a derating factor based on RθJA = 158°C/W for the D package and RθJA = 176°C/W for the PW package.
These devices are mounted on an FR4 board with no special thermal considerations.
DISSIPATION RATING TABLE
PACKAGE TA 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D791 mW 6.33 mW/°C506 mW 411 mW 158 mW
PW 710 mW 5.68 mW/°C454 mW 369 mW 142 mW
Maximum values are calculated using a derating factor based on RθJA = 158°C/W for the D package and RθJA = 176°C/W
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations.
PARAMETER TEST CONDITIONS Scam: dramrtorsou rce PARAMETER TEST CONDITIONS
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics at TJ = 25°C (unless otherwise noted)
static
PARAMETER
TPS1101 TPS1101Y
UNIT
PARAMETER
MIN TYP MAX MIN TYP MAX
UNIT
VGS(th) Gate-to-source
threshold voltage VDS = VGS, ID = –250 µA–1 1.25 –1.5 1.25 V
VSD Source-to-drain voltage
(diode-forward voltage)IS = –1 A, VGS = 0 V 1.04 1.04 V
IGSS
Reverse gate current,
drain short circuited to
source VDS = 0 V, VGS = –12 V ±100 nA
IDSS
Zero-gate-voltage drain
VDS =12V
VGS =0V
TJ = 25°C –0.5
µA
I
DSS
gg
current
V
DS = –
12
V
,
V
GS =
0
V
TJ = 125°C–10 µ
A
VGS = –10 V ID = –2.5 A 90 90
rDS( )
Static drain-to-source VGS = –4.5 V ID = –1.5 A 134 190 134
m
r
DS(on)
Static
drain to source
on-state resistanceVGS = –3 V
ID=05A
198 310 198
m
VGS = –2.7 V
I
D = –
0
.
5
A
232 400 232
gfs Forward
transconductanceVDS = –10 V, ID = –2 A 4.3 4.3 S
Pulse test: pulse duration 300 µs, duty cycle 2%
dynamic
PARAMETER
TEST CONDITIONS
TPS1101, TPS1101Y
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
QgTotal gate charge 11.25
Qgs Gate-to-source charge VDS = –10 V, VGS = –10 V, ID = –1 A 1.5 nC
Qgd Gate-to-drain charge 2.6
td(on) Turn-on delay time 6.5 ns
td(off) Turn-off delay time V
DD
= –10 V, R
L
= 10 ,I
D
= –1 A, 19 ns
trRise time
DD ,
RG = 6 ,
L,
See Figures 1 and 2
D,
5.5
tfFall time 13 ns
trr(SD) Source-to-drain reverse recovery time IF = 5.3 A, di/dt = 100 A/µs 16
Figure 1. Switching-Time Test C *9 TEXAS INSTRUMENTS p0
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 1. Switching-Time Test Circuit
RG
DUT
RL
VDD
+
VGS
VDS
Figure 2. Switching-Time Waveforms
td(on)
tr
VDS
td(off)
tf
VGS
90%
10%
0 V
10 V
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Drain current vs Drain-to-source voltage 3
Drain current vs Gate-to-source voltage 4
Static drain-to-source on-state resistance vs Drain current 5
Capacitance vs Drain-to-source voltage 6
Static drain-to-source on-state resistance (normalized) vs Junction temperature 7
Source-to-drain diode current vs Source-to-drain voltage 8
Static drain-to-source on-state resistance vs Gate-to-source voltage 9
Gate-to-source threshold voltage vs Junction temperature 10
Gate-to-source voltage vs Gate charge 11
//w *9 TEXAS INSTRUMENTS
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
– 5
– 4
– 2
– 1
0
– 9
– 3
0 1– 2– 3– 4– 5– 6
– Drain Current – A
– 7
– 6
– 8
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
– 10
– 7 – 8 – 9 – 10
VGS = –8 V
VGS = –3 V
VGS = –4 V
VGS = –2 V
ID
VDS – Drain-to-Source Voltage – V
VGS = –5 V
TJ = 25°C
Figure 4
– 6
– 4
– 2
00 – 2 – 3 – 5
– 8
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
– 10
– 1 – 4
– Drain Current – A
ID
TJ = 25°C
TJ = 150°C
VGS – Gate-to-Source Voltage – V
TJ = –40°C
VDS = –10 V
Figure 5
0.3
0.2
0.1
0
– 0.1 – 1
– Static Drain-to-Source On-State
0.4
0.5
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
– 10
ID – Drain Current – A
rDS(on)
VGS = –4.5 V
VGS = –10 V
TJ = 25°C
Resistance –
VGS = –2.7 V
VGS = –3 V
Figure 6
500
400
200
100 0 – 1 – 2 – 3 – 4 – 5 – 6
C – Capacitance – pF
600
700
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
800
– 7 – 8 – 9 –12
300
–10 –11
Coss
Crss
VDS – Drain-to-Source Voltage – V
Ciss
VGS = 0 V
f = 1 MHz
TJ = 25°C
Crss Cgd,C
oss Cds
Cgs Cgd
Cgs Cgd Cds Cgd
Ciss Cgs Cgd,C
ds(shorted)
*9 TEXAS INSTRUMENTS
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 7
1.2
0.9
0.8
0.6
1.3
1.4
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE (NORMALIZED)
vs
JUNCTION TEMPERATURE
1.5
1.1
1
0.7
50 0 50 100 150
TJ – Junction Temperature – °C
VGS = –10 V
ID = –1A
– Static Drain-to-Source
rDS(on)
On-State Resistance (normalized)
Figure 8
– 0.1
– 0.1
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
– 1
– 10
– 0.3 – 0.5 – 0.7
VSD – Source-to-Drain Voltage – V
– 0.9 – 1.1 – 1.3
TJ = 25°C
TJ =40°C
TJ = 150°C
– Source-to-Drain Diode Current – A
ISD
Pulse Test
Figure 9
0.2
0.1
0
– 1 – 3 – 5 – 7
0.3
0.4
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
GATE-TO-SOURCE VOLTAGE
0.5
– 9 – 11 – 13 – 15
VGS – Gate-to-Source Voltage – V
ID = –1 A
TJ = 25°C
– Static Drain-to-Source On-State
rDS(on) Resistance –
Figure 10
– 1.2
– 1.1
– Gate-to-Source Threshold Voltage – V
– 1.3
– 1.4
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– 1.5
50 0 50 100 150
– 1
– 0.9
TJ – Junction Temperature – °C
VGS(th)
ID = –250 µA
*9 TEXAS INSTRUMENTS
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
– 6
– 4
– 2
004610
– 8
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
– 10
2812
Q
g
– Gate Charge – nC
VDS = –10 V
ID = –1 A
TJ = 25°C
– Gate-to-Source Voltage – VVGS
Figure 11
3V075V Microconlloller j Load Microcnmrnller j 4 ¥ L “F Figure 14. Notebook Load Management *9 TEXAS INSTRUMENTS p057 OFFICE aox $553133 - DALLAS IEXAS 752%
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THERMAL INFORMATION
Figure 12
– 1
– 0.1
– 0.01
– 10
– 0.1 – 1 – 10 – 100
– Drain Current – A
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
ID
VDS – Drain-to-Source Voltage – V
– 100
DC
10 s
1 s
0.1 s
0.01 s
0.001 s
Single Pulse
See Note A
TJ = 150°C
TA = 25°C
NOTE A: Values are for the D package and are
FR4-board-mounted only.
Figure 13
10
1
0.1
100
0.001 0.01 0.1 1 10
Single Pulse
See Note A
– Transient Junction-to-AmbientZ C/W
°
θJA Thermal Impedance –
TRANSIENT JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
vs
PULSE DURATION
tw – Pulse Duration – s
NOTE A: Values are for the D package and are
FR4-board-mounted only.
APPLICATION INFORMATION
Load
3 V or 5 V
Microcontroller
Figure 14. Notebook Load Management
Microcontroller Charge
Pump
5 V
–4 V GaAs FET
Amplifier
Driver
Figure 15. Cellular Phone Output Drive
I TEXAS INSTRUMENTS Sample: Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS1101D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 1101
TPS1101DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 1101
TPS1101PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM PS1101
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS1101DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS1101PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS1101DR SOIC D 8 2500 340.5 336.1 25.0
TPS1101PWR TSSOP PW 16 2000 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS1101D D SOIC 8 75 507 8 3940 4.32
Pack Materials-Page 3
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