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654P/L Series Datasheet by CTS-Frequency Controls
View All Related Products | Download PDF Datasheet
ROHS E Connect
(mm.
Standard Frequenmes
Type subrlixy Range anlage
654 P xxx or xxxx 3 I 3 T
code Output Code vouage
P LVPECL Pm 1 Enema 2 +2 SVdC
was , Pm 1 Enable 3 +3 Zvdc
LVPECL Pm 2 Emma
LVDS , Pm 2 Enable
(Mr—
Code Frequency Code Temp Range
VAD‘C [0 cas c
Reier m document 0167149170, Frequency Cede Tamas
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
DOC# 008-0549-0 Rev. C Page 1 of 8
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
Features
Ceramic Surface Mount Package
Low Phase Jitter Performance, 500fs Typical
Advanced PLL Design w/ Low Fundamental Crystal
Frequency Range 10MHz – 800MHz *
+2.5V or +3.3V Operation
Output Enable Standard, Pin 2 Option Available
Tape and Reel Packaging, EIA-418
Applications
Broadcast Video Systems
Storage Area Networking
Broadband Access
PCI Express
Networking Equipment
Ethernet/GbE/SyncE
Fiber Channel
Test and Measurement
Description
CTS Model 654P/L is a low cost, high performance PLL clock oscillator supporting differential LVPECL or LVDS
outputs. Employing the latest IC technology, M654P/L has excellent stability and low phase jitter performance.
Ordering Information
Model
654
Code Code Code
P62
L 5 3
E 4
V3
Code Code Code
CT
I
Notes:
1]
2]
3]
Check factory availability when paired with 'I' temperature code.
Contact your local CTS Representative or CTS Customer Service for availability.
Not all performance combinations and frequencies may be available.
Refer to document 016-1454-0, Frequency Code Tables.
3-digits for frequencies <100MHz, 4-digits for frequencies 100MHz or greater.
6I Stability/Temperature combination not available.
P
Frequency
Product Frequency Code
1
Packaging
Frequency Code
[MHz]
Frequency
Stability
Temperature
Range
Supply
Voltage
Output
Type
XXX or XXXX
3
I
3
T
Temp. Range
-20°C to +70°C
-40°C to +85°C
Packing
1k pcs./reel
Output
LVPECL - Pin 1 Enable
LVDS - Pin 1 Enable
LVPECL - Pin 2 Enable
LVDS - Pin 2 Enable
Stability
±20ppm
2
±25ppm
3
±30ppm
Voltage
+2.5Vdc
+3.3Vdc
±50ppm
This product is specified for use only in standard commercial applications. Supplier disclaims all express and implied warranties and liability in connection with any use of this
product in any non-commercial applications or in any application that may expose the product to conditions that are outside of the tolerances provided in its specification.
Part Dimensions:
5.0 × 3.2 × 1.2mm • 62.00mg
Standard Frequencies
- 25.00MHz - 125.00MHz - 250.00MHz
- 27.00MHz - 148.50MHz - 312.50MHz
- 50.00MHz - 153.60MHz - 322.265625MHz
- 74.25MHz - 155.52MHz - 400.00MHz
- 100.00MHz - 156.25MHz
- 106.25MHz - 200.00MHz
* See Page 8 for additional developed frequencies.
Check with factory for availability of frequencies not listed.
[Mme I]
www.ctscorp.com
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
DOC# 008-0549-0 Rev. C Page 2 of 8
Electrical Specifications
Operating Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Maximum Supply Voltage
V
CC
--0.5 -4.0 V
2.375 2.5 2.625
3.135 3.3 3.465
Supply Current
LVPECL -54 88
LVDS -23 65
-20
+70
-40
+85
Storage Temperature
T
STG
--55 -+125 °C
Frequency Stability
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Frequency Range f
O
-MHz
Frequency Stability
[Note 1]
Δf/f
O
-±ppm
Aging Δf/f
25
First Year @ +25°C, nominal V
CC
-3 - 3 ppm
Output Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Output Type - - -
Output Load
R
L
Terminated to V
CC
- 2.0V -50 -Ohms
V
OH
V
CC
- 1.03 - V
CC
- 0.60
V
OL
V
CC
- 1.85 - V
CC
- 1.60
Output Duty Cycle SYM @ V
CC
- 1.3V 45 -55 %
Rise and Fall Time T
R
, T
F
@ 20%/80% Levels, R
L
= 50 Ohms -0.25 0.60 ns
Output Type - - -
Output Load
R
L
Between Outputs -100 -Ohms
V
OH
-1.43 1.60
V
OL
0.90 1.10 -
Output Duty Cycle SYM @ 1.25V 45 -55 %
Differential Output Voltage V
OD
R
L
= 100 Ohms 175 330 454 mV
Offset Voltage V
OS
LVDS Load 1.20 1.25 1.30 V
Rise and Fall Time T
R
, T
F
@ 20%/80% Levels, R
L
= 100 Ohms - - 0.5 ns
10 - 800
LVDS
Output Voltage Levels
LVDS Load
1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
LVPECL
20, 25 or 50
V
V
°C
Operating Temperature
T
A
-
+25
Output Voltage Levels
PECL Load
mA
±5%
V
Supply Voltage
V
CC
I
CC
Maximum Load
Maximum Current Value @ +3.3V
CS
PlnlorPan PIn4&PlnS
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
DOC# 008-0549-0 Rev. C Page 3 of 8
Electrical Specifications
Enable Truth Table
Pin 1 or Pin 2
Pin 4 & Pin 5
Logic ‘1’
Output
Open Output
Logic ‘0’
High Imp.
Test Circuit
LVPECL LVDS
Output Waveform
LVPECL or LVDS
Output Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Start Up Time T
S
Application of V
CC
- 3 5 ms
Enable Function [Tri-State]
Enable Input Voltage
V
IH
Pin 1 or 2 Logic '1', Output Enabled 0.7V
CC
- - V
Disable Input Voltage V
IL
Pin 1 or 2 Logic '0', Output Disabled - - 0.3V
CC
V
Disable Current I
IL
Pin 1 or 2 Logic '0', Output Disabled -16 22 mA
Enable Time T
PLZ
Pin 1 or 2 Logic '1', Output Enabled - - 200 ns
Phase Jitter, RMS tjrms Bandwidth 12 kHz - 20 MHz -500 <1000 fs
Period Jitter, RMS pjrms - - 2.5 -ps
Period Jitter, pk-pk pjpk-pk - - 25 -ps
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equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
DOC# 008-0549-0 Rev. C Page 4 of 8
Electrical Specifications
Performance Data
Phase Noise [typical]
100.00MHz, LVPECL, VCC = 3.3V, TA = +25°C 156.25MHz, LVPECL, VCC = 3.3V, TA = +25°C
312.50MHz, LVPECL, VCC = 3.3V, TA = +25°C
www.ctscorp.com
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
DOC# 008-0549-0 Rev. C Page 5 of 8
Performance Data
Phase Noise Tabulated
Typical, HCMOS, VCC = 3.3V, TA = +25°C
PARAMETER SYMBOL CONDITIONS TYP UNIT PARAMETER SYMBOL CONDITIONS TYP UNIT
LVPECL @ 100.00MHz LVPECL @ 156.25MHz
Phase Noise Single Side Band Phase Noise Single Side Band
@ 10Hz -69.70 @ 10Hz -88.60
@ 100Hz -92.90 @ 100Hz -97.80
@ 1kHz -115.90 @ 1kHz -111.40
@ 10kHz -126.80 @ 10kHz -121.00
@ 100kHz -129.50 @ 100kHz -127.00
@ 1MHz -143.50 @ 1MHz -141.80
@ 10MHz -154.90 @ 10MHz -151.50
@ 40MHz -155.30 @ 40MHz -153.30
Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 714.35 fs Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 869.93 fs
PARAMETER SYMBOL CONDITIONS TYP UNIT
LVPECL @ 312.50MHz
Phase Noise Single Side Band
@ 10Hz -81.30
@ 100Hz -91.80
@ 1kHz -105.30
@ 10kHz -115.50
@ 100kHz -120.80
@ 1MHz -136.40
@ 10MHz -153.20
@ 40MHz -153.20
Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 496.03 fs
-
dBc/Hz
-
dBc/Hz
-
dBc/Hz
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654OST
o xxxx
1. JEDECtermmanon code (e4) Barnehp‘atmgis
Citrus
9;.
a o
:3::;::::
o ‘o ‘
2,1
1.4
L 3
——| 1.0 m: m
Pin Symbol Function
2 MO or EOH N0 Connect 0r Enable [opt]
3 GND Circuit & Package Ground
4 Output RF Output
5 Output Comphmentary RF Output
cc
MONTH
YEAR
2001 2005 2009 2013 2017 A a c 0 E r G H 1 K L M
2002 2006 2010 2014 2013 N P Q R s T u v w x v z
2003 2007 2011 2015 2019 a u ( d e f g t. 1 k 1 m
2004 2003 2012 2015 2020 n p q r 5 t u v w x y z
www.ctscorp.com
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
DOC# 008-0549-0 Rev. C Page 6 of 8
Mechanical Specifications
Package Drawing Marking Information
Recommended Pad Layout Notes
Pin Assignments
Pin
Symbol
Function
1
EOH or N.C.
Enable [std] or No Connect
2
N.C. or EOH
No Connect or Enable [opt]
3
GND
Circuit & Package Ground
4
Output
RF Output
5
Output
Complimentary RF Output
6 V
CC
Supply Voltage
Table I - Date Code
2001 2005 2009 2013 2017 A B C D E F G H J K L M
2002 2006 2010 2014 2018 N P Q R S T U V W X Y Z
2003 2007 2011 2015 2019 a b c d e f g h j k l m
2004 2008 2012 2016 2020 n p q r s t u v w x y z
NOV
DEC
YEAR
MAY
JUN
JUL
AUG
SEP
OCT
MONTH
JAN
FEB
MAR
APR
1. ** - Manufacturing Site Code.
2. D – Date Code. See Table I for codes.
3. O – Output Type; P = LVPECL, L = LVDS.
3. ST – Frequency Stability/Temperature Code.
[Refer to Ordering Information]
4. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.
5. xxxx – Frequency Code.
3-digits, frequencies below 100MHz
4-digits, frequencies 100MHz or greater
[See document 016-1454-0, Frequency Code Tables.]
1. JEDEC termination code (e4). Barrier-plating is
nickel [Ni] with gold [Au] flash plate.
2. Reflow conditions per JEDEC J-STD-020; +260°C
maximum, 20 seconds.
3. MSL = 1.
CTS**D
654OSTV
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equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
DOC# 008-0549-0 Rev. C Page 7 of 8
Packaging - Tape and Reel
Tape Drawing
Reel Drawing
Notes
1. Device quantity is 1k pieces per 180mm reel.
2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels.
CS
CODE CODE CODE CODE
CODE CODE CODE CODE
www.ctscorp.com
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©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 654P/L
Advanced PLL LVPECL or LVDS Clock
DOC# 008-0549-0 Rev. C Page 8 of 8
Addendum
Additional Developed Frequencies – MHz
Frequency Codes for Cover Page Table – MHz
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
38.840000 38D 77.760000 777 135.000000 1350 184.320000 1843
38.880000 388 86.700000 867 144.500000 1445 204.800000 2048
43.350000 433 87.351542 873 148.351600 148A 233.000000 2330
45.000000 450 92.160000 921 148.351648 148B 245.760000 2457
54.000000 540 96.000000 960 150.000000 1500 300.000000 3000
62.500000 625 104.000000 1040 156.253906 156A 349.400000 3494
74.175800 74A 122.880000 1228 160.000000 1600
76.800000 768 132.000000 1320 161.132800 1611
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
25.000000 250 106.250000 1062 156.250000 1562 400.000000 4000
27.000000 270 125.000000 1250 200.000000 2000
50.000000 500 148.500000 1485 250.000000 2500
74.250000 742 153.600000 1536 312.500000 3125
100.000000 1000 155.520000 1555 322.265625 322A
