CM1293A-04SO Datasheet by onsemi

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0M1 293A-O4SO L ON Semiconductor8 w
Semiconductor Components Industries, LLC, 2012
January, 2012 Rev. 0
1Publication Order Number:
CM1293A04SO/D
CM1293A-04SO
4-Channel
Low Capacitance
ESD Protection Array
Product Description
CM1293A04SO has been designed to provide ESD protection for
electronic components or subsystems requiring minimal capacitive
loading. This device is ideal for protecting systems with high data and
clock rates or for circuits requiring low capacitive loading. Each ESD
channel consists of a pair of diodes in series that steer the positive or
negative ESD current pulse to either the positive (VP) or negative (VN)
supply rail. A Zener diode is embedded between VP and VN which
helps protect the VCC rail against ESD strikes. This device protects
against ESD pulses up to 8 kV contact discharge) per the
IEC 6100042 Level 4 standard.
This device is particularly wellsuited for protecting systems using
highspeed ports such as USB2.0, IEEE1394 (FireWire, i.LINKt),
Serial ATA, DVI, HDMI, and corresponding ports in removable
storage, digital camcorders, DVDRW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
Features
Four Channels of ESD Protection
Provides ESD Protection to IEC6100042
8 kV Contact Discharge
Low Loading Capacitance of 2.0 pF Max
Low Clamping Voltage
Channel I/O to I/O Capacitance 1.5 pF Typical
Zener Diode Protects Supply Rail and Eliminates the Need for
External ByPass Capacitors
Each I/O Pin Can Withstand over 1000 ESD Strikes*
This Device is PbFree and is RoHS Compliant**
Applications
DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
Serial ATA Ports in Desktop PCs and Hard Disk Drives
PCI Express Ports
General Purpose HighSpeed Data Line ESD Protection
**Standard test condition is IEC6100042 level 4 test circuit with each pin
subjected to 8 kV contact discharge for 1000 pulses. Discharges are timed at
1 second intervals and all 1000 strikes are completed in one continuous test run.
The part is then subjected to standard production test to verify that all of the
tested parameters are within spec after the 1000 strikes.
**For additional information on our PbFree strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM
Device Package Shipping
ORDERING INFORMATION
http://onsemi.com
SC74
(PbFree)
3,000 /
Tape & Reel
CM1293A04SO
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
SC74
SO SUFFIX
CASE 318F
BLOCK DIAGRAM
CH2CH1 CH3 CH4
VN
VP
CM1293A04SO
1
XXXMG
G
XXX = Specific Device Code
M = Date Code
G= PbFree Package
(Note: Microdot may be in either location)
CM1293A04SO
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2
Table 1. PIN DESCRIPTIONS
Pin Name Type Description
1 CH1 I/O ESD Channel
2 VNGND Negative Voltage Supply Rail
3 CH2 I/O ESD Channel
4 CH3 I/O ESD Channel
5 VPPWR Positive Voltage Supply Rail
6 CH4 I/O ESD Channel
PACKAGE/PINOUT DIAGRAM
Top View
CH2
VP
4Channel SC74
VN
CH3
CH1 CH4
635
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Operating Supply Voltage (VP VN) 6.0 V
Operating Temperature Range –40 to +85 C
Storage Temperature Range –65 to +150 C
DC Voltage at any Channel Input (VN 0.5) to (VP + 0.5) V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter Rating Units
Operating Temperature Range –40 to +85 C
Package Power Rating 225 mW
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol Parameter Conditions Min Typ Max Units
VPOperating Supply Voltage (VPVN) 3.3 5.5 V
IPOperating Supply Current (VPVN) = 3.3 V 8.0 mA
VFDiode Forward Voltage IF = 8 mA, TA = 25C 0.90 V
ILEAK Channel Leakage Current TA = 25C, VP = 5 V, VN = 0 V 0.1 1.0 mA
CIN Channel Input Capacitance At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 2.0 pF
DCIO Channel I/O to I/O Capacitance 1.5 pF
VESD ESD Protection
Peak Discharge Voltage at any
Channel Input, in System
Contact Discharge per
IEC 6100042 Standard
TA = 25C (Notes 2 and 3) 8
kV
VCL Channel Clamp Voltage
Positive Transients
Negative Transients
TA = 25C, IPP = 1A, tP = 8/20 mS
(Note 3) +9.9
–1.6
V
RDYN Dynamic Resistance
Positive Transients
Negative Transients
TA = 25C, IPP = 1A, tP = 8/20 mS
(Note 3) 0.96
0.5
W
1. All parameters specified at TA = –40C to +85C unless otherwise noted.
2. Standard IEC 6100042 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.
3. These measurements performed with no external capacitor on VP
.
lmln QpanitancemF) 2.0 "5-5 1.5 0| 2 II / :5 1.0 N M n. .u u ‘5 0.5 n 5 0.0 0,0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Input Voltage (w 0V DC Input Bias — — _ 155V DC Input Bias 0.920 0.900 0.840 4’ asapfié 0.860 // ’ .4— / 0.820 " 0.300 / 0.780 .50 .25 0 25 5!] Tem perature (° C) 75 100
CM1293A04SO
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3
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)
Figure 2. Typical Variation of CIN vs. Temp
(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)
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CM1293A04SO
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4
PERFORMANCE INFORMATION (Cont’d)
Typical Filter Performance (nominal conditions unless specified otherwise, 50 Environment)
Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP = 3.3 V)
Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP = 3.3 V)
S r————————————————+
CM1293A04SO
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5
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a
connector) and the ESD protection device. Refer to Figure 5, which illustrates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the
line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC6100042 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be
approximated by DIESD/Dt, or 30/(1x109). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance
L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when
VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 F ceramic chip
capacitor be connected between VP and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
POSITIVE SUPPLY RAIL
CHANNEL
INPUT
GROUND RAIL
CHASSIS GROUND
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
LINE BEING
PROTECTED
ONE
CHANNEL
D2
D1L1
L2VCC
VCL
VN
VP
0.22 mF
PATH OF ESD CURRENT PULSE IESO
Figure 5. Application of Positive ESD Pulse between Input Channel and Ground
0 A
25 A
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CM1293A04SO
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6
PACKAGE DIMENSIONS
SC74
CASE 318F05
ISSUE M
23
456
D
1
e
b
E
A1
A
0.05 (0.002)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. 318F01, 02, 03, 04 OBSOLETE. NEW
STANDARD 318F05.
C
L
0.7
0.028
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.95
0.037
ǒmm
inchesǓ
SCALE 10:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
HE
DIM
A
MIN NOM MAX MIN
MILLIMETERS
0.90 1.00 1.10 0.035
INCHES
A1 0.01 0.06 0.10 0.001
b0.25 0.37 0.50 0.010
c0.10 0.18 0.26 0.004
D2.90 3.00 3.10 0.114
E1.30 1.50 1.70 0.051
e0.85 0.95 1.05 0.034
0.20 0.40 0.60 0.008
0.039 0.043
0.002 0.004
0.015 0.020
0.007 0.010
0.118 0.122
0.059 0.067
0.037 0.041
0.016 0.024
NOM MAX
2.50 2.75 3.00 0.099 0.108 0.118
HE
L
010010
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81358171050
CM1293A04SO/D
FireWire is a registered trademark of Apple Computer, Inc.
i.LINK is a trademark of Sony Corporation.
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