Datenblatt für SN74LVC1G66 von Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G66
SCES323Q –JUNE 2001REVISED MARCH 2017
SN74LVC1G66 Single Bilateral Analog Switch
1
1 Features
1 Available in the Texas Instruments NanoFree™
Package
1.65-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 0.8 ns at 3.3 V
High On-Off Output Voltage Ratio
High Degree of Linearity
High Speed, Typically 0.5 ns (VCC = 3 V,
CL= 50 pF)
Low ON-State Resistance, Typically 5.5 (VCC
= 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
2 Applications
Wireless Devices
Audio and Video Signal Routing
Portable Computing
Wearable Devices
Signal Gating, Chopping, Modulation or
Demodulation (Modem)
Signal Multiplexing for Analog-to-Digital and
Digital-to-Analog Conversion Systems
3 Description
This single analog switch is designed for 1.65-V to
5.5-V VCC operation.
The SN74LVC1G66 device can handle analog and
digital signals. The device permits bidirectional
transmission of signals with amplitudes of up to 5.5 V
(peak).
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G66DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74LVC1G66DCK SC70 (5) 2.00 mm × 1.25 mm
SN74LVC1G66DRL SOT (5) 1.60 mm × 1.20 mm
SN74LVC1G66DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1G66YZP DSBGA (5) 1.39 mm × 0.89 mm
SN74LVC1G66DSF SON (6) 1.00 mm x 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 6
6.7 Analog Switch Characteristics .................................. 7
6.8 Operating Characteristics.......................................... 7
6.9 Typical Characteristics.............................................. 8
7 Parameter Measurement Information .................. 9
8 Detailed Description............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
9 Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1 Documentation Support ........................................ 17
12.2 Trademarks........................................................... 17
12.3 Electrostatic Discharge Caution............................ 17
12.4 Glossary................................................................ 17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (March 2016) to Revision Q Page
Changed the YZP package pin out graphic............................................................................................................................ 4
Changes from Revision O (March 2015) to Revision P Page
Added Junction temperature spec to Absolute Maximum Ratings table................................................................................ 5
Added "Control" to "Input transition rise and fall time" in Recommended Operating Conditions table .................................. 5
Changes from Revision N (December 2012) to Revision O Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Removed Ordering Information table ..................................................................................................................................... 1
Added Device Information table ............................................................................................................................................. 1
Changes from Revision M (January 2012) to Revision N Page
Added jumbo reel to Ordering Information table .................................................................................................................... 1
Changes from Revision L (January 2007) to Revision M Page
Added DSF and DRY package to pin out graphic.................................................................................................................. 3
l TEXAS INSTRUMENTS [I 31c E 30 E [I E 3 [I 3] El: CE 13 |:||:| [E |:||:| [E j: DUI BED
A
GND
B
VCC
C
NC
6
5
4
2
3
1
3
2
4
51
A VCC
C
B
GND
B NC
A6
5
4
2
3
GND C
VCC
1
3
2
4
51
A VCC
C
B
GND
3
SN74LVC1G66
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
(Top View)
DCK Package
5-Pin SC70
(Top View)
DRL Package
5-Pin SOT
(Top View)
DSF Package
6-Pin X2SON
(Top View)
DRY Package
6-Pin USON
(Top View)
Pin Functions
PIN
I/O DESCRIPTION
NAME SOT NO. USON,
X2SON
NO.
A 1 1 I/O Bidirectional signal to be switched
B 2 2 I/O Bidirectional signal to be switched
C 4 4 I Controls the switch (L = OFF, H = ON)
GND 3 3 Ground pin
NC 5 Do not connect
VCC 5 6 Power pin
l TEXAS INSTRUMENTS
1 2
B
C
A
GND C
VCC
B
A
4
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YZP Package
5-Pin DSBGA
(Bottom View)
Pin Functions
PIN I/O DESCRIPTION
NAME DSBGA NO.
A A1 I/O Bidirectional signal to be switched
B B1 I/O Bidirectional signal to be switched
C C2 I Controls the switch (L = OFF, H = ON)
GND C1 Ground pin
VCC A2 Power pin
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(2) –0.5 6.5 V
VIInput voltage(2)(3) –0.5 6.5 V
VI/O Switch I/O voltage(2)(3)(4) –0.5 VCC + 0.5 V
IIK Control input clamp current VI< 0 –50 mA
IIOK I/O port diode current VI/O < 0 or VI/O > VCC ±50 mA
ITON-state switch current VI/O < 0 to VCC ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage Temperature –65 150 °C
TjJunction Temperature 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) +2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) +1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,SCBA004.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VI/O I/O port voltage. 0 VCC V
VIH High-level input voltage, control input
VCC = 1.65 V to 1.95 V VCC × 0.65
V
VCC = 2.3 V to 2.7 V VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7
VIL Low-level input voltage, control input
VCC = 1.65 V to 1.95 V VCC × 0.35
V
VCC = 2.3 V to 2.7 V VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3
VIControl input voltage 0 5.5 V
Δt/Δv Control input transition rise and fall time
VCC = 1.65 V to 1.95 V 20
ns/V
VCC = 2.3 V to 2.7 V 20
VCC = 3 V to 3.6 V 10
VCC = 4.5 V to 5.5 V 10
TAOperating free-air temperature –40 85 °C
l TEXAS INSTRUMENTS
6
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SCES323Q JUNE 2001REVISED MARCH 2017
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6.4 Thermal Information
THERMAL METRIC
SN74LVC1G66
UNIT
DBV
(SOT-23) DCK
(SC70) DRL (SOT) DRY
(USON) DSF
(X2SON) YZP
(DSBGA)
5 PINS 5 PINS 5 PINS 6 PINS 6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 206 252 142 132 °C/W
(1) TA= 25°C
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
ron ON-state switch resistance
VI= VCC or GND,
VC= VIH
(see Figure 2 and
Figure 1)
IS= 4 mA 1.65 V 12 30
IS= 8 mA 2.3 V 9 20
IS= 24 mA 3 V 7.5 15
IS= 32 mA 4.5 V 5.5 10
ron(p) Peak on resistance
VI= VCC or GND,
VC= VIH
(see Figure 2 and
Figure 1)
IS= 4 mA 1.65 V 74.5 120
IS= 8 mA 2.3 V 20 30
IS= 24 mA 3 V 11.5 20
IS= 32 mA 4.5 V 7.5 15
IS(off) OFF-state switch leakage current VI= VCC and VO= GND or
VI= GND and VO= VCC,
VC= VIL (see Figure 3)5.5 V ±1
μA
TA= 25°C ±0.1
IS(on) ON-state switch leakage current VI= VCC or GND, VC= VIH,
VO= Open
(see Figure 4)5.5 V ±1
μA
TA= 25°C ±0.1
IIControl input current VC= VCC or GND 5.5 V ±1 μA
TA= 25°C ±0.1
ICC Supply current VC= VCC or GND 5.5 V 10 μA
TA= 25°C 1
ΔICC Supply current change VC= VCC – 0.6 V 5.5 V 500 μA
Cic Control input capacitance 5 V 2 pF
Cio(off) Switch input and output capacitance 5 V 6 pF
Cio(on) Switch input and output capacitance 5 V 13 pF
(1) tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical ON-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
(2) tPZL and tPZH are the same as ten.
(3) tPLZ and tPHZ are the same as tdis.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tpd(1) A or B B or A 2 1.2 0.8 0.6 ns
ten(2) C A or B 2.5 12 1.9 6.5 1.8 5 1.5 4.2 ns
tdis(3) C A or B 2.2 10 1.4 6.9 2 6.5 1.4 5 ns
l TEXAS INSTRUMENTS
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(1) Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
(2) Adjust fin voltage to obtain 0 dBm at input.
6.7 Analog Switch Characteristics
TA= 25°C
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST
CONDITIONS VCC TYP UNIT
Frequency response(1)
(switch ON) A or B B or A
CL= 50 pF, RL= 600 ,
fin = sine wave
(see Figure 6)
1.65 V 35
MHz
2.3 V 120
3 V 175
4.5 V 195
CL= 5 pF, RL= 50 ,
fin = sine wave
(see Figure 6)
1.65 V >300
2.3 V >300
3 V >300
4.5 V >300
Crosstalk
(control input to signal output) C A or B CL= 50 pF, RL= 600 ,
fin = 1 MHz (square wave)
(see Figure 7)
1.65 V 35
mV
2.3 V 50
3 V 70
4.5 V 100
Feedthrough attenuation(2)
(switch OFF) A or B B or A
CL= 50 pF, RL= 600 ,
fin = 1 MHz (sine wave)
(see Figure 8)
1.65 V –58
dB
2.3 V –58
3 V –58
4.5 V –58
CL= 5 pF, RL= 50 ,
fin = 1 MHz (sine wave)
(see Figure 8)
1.65 V –42
2.3 V –42
3 V –42
4.5 V –42
Sine-wave distortion A or B B or A
CL= 50 pF, RL= 10 k,
fin = 1 kHz (sine wave)
(see Figure 9)
1.65 V 0.1%
2.3 V 0.025%
3 V 0.015%
4.5 V 0.01%
CL= 50 pF, RL= 10 k,
fin = 10 kHz (sine wave)
(see Figure 9)
1.65 V 0.15%
2.3 V 0.025%
3 V 0.015%
4.5 V 0.01%
6.8 Operating Characteristics
TA= 25°C
PARAMETER TEST
CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 8 9 9 11 pF
l TEXAS INSTRUMENTS \ Vm
100
10
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VIN − V
ron
8
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6.9 Typical Characteristics
TA= 25°C
Figure 1. Typical ron as a Function of Input Voltage (VI) for VI= 0 to VCC
l TEXAS INSTRUMENTS V|=VccfllGND “'5 m i WE VI (3 Aan C v.L 7M (om GN Condilinn 1 GND, v0 = vcc 7 Condilinn 2. Vcc. Va = GND , 0 Anna Vm (0N) v0 = Open
VCC
VO
GND(ON)
B or A
C
A or B
VCC
VIH VC
A
VI = VCC or GND
VO = Open
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
VCC
VIVO
GND(OFF)
B or A
C
A or B
VCC
VIL VC
A
VCC
VI = VCC or GND VO
ron +VI*VO
IS
W
VI − VO
GND(ON)
V
B or A
C
A or B
VCC
VIH VC
IS
9
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7 Parameter Measurement Information
Figure 2. ON-State Resistance Test Circuit
Figure 3. OFF-State Switch Leakage-Current Test Circuit
Figure 4. ON-State Switch Leakage-Current Test Circuit
l TEXAS INSTRUMENTS From Oulpul Under Test CL 7, (see Note A) LOAD CIRCUIT Vcc 1.8 V 10.15 V 2.5 V :02 V 3.3 V :03 V 5 V :05 V T T Input V" v" VOLTAGE WAVEFORMS PULSE DURATION Output VOLTAGE WAVEFORMS PROPAGATION DELAV TIMES INVERTING AND NONINVERTING OUTP NOTES. A CLTnCTudespmbeandpg capacman a Wavemrm 1 s car an ompu: mm m Wavelarm 2 s car an ompu: mm mt Ipnmoo AH mpm pu‘ses are supphed by gen The oulpms are measured me at a «m and :sz are me same as «ms. IPZL and mm are me same as ten 1le and TM are me same as 'm A” parameTers and wavelorms are
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V
VOH − V
0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 k
500
500
500
VCC RL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
VCC
VCC
VI
VCC/2
VCC/2
VCC/2
VCC/2
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
10
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Parameter Measurement Information (continued)
Figure 5. Load Circuit and Voltage Waveforms
VCC
VO
GND
B or A
C
A or B
VCC
VC
CL
50 pF
50 VCC/2
VCC/2
Rin
600
RL
600
VCC
VO
GND
B or A
C
A or B
VCC
VC
VIH RLCL
50
0.1 µF
(ON) VCC/2
RL/CL: 600 /50 pF
RL/CL: 50 /5 pF
fin
11
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Parameter Measurement Information (continued)
Figure 6. Frequency Response (Switch ON)
Figure 7. Crosstalk (Control Input – Switch Output)
l TEXAS INSTRUMENTS Vcc ‘ A or a a or A ‘ l c fm an n W Vc RL I GND , Vcc Vcc ‘ ‘ A or a N B or A ‘ x x l x ’7 0 RL CL son 0 V'" Vc m km :|’ so p Vcc = 4.5 v, v. = 4 vp,P N)
VCC
VO
GND
B or A
C
A or B
VCC
VC
VIH
RL
10 kCL
50 pF
600
10 µF
(ON) VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
VCC = 3 V, VI = 2.5 VP-P
VCC = 4.5 V, VI = 4 VP-P
fin
10 µF
VCC
VO
GND
B or A
C
A or B
VCC
VC
VIL RLCL
50
0.1 µF
(OFF) VCC/2
RL/CL: 600 /50 pF
RL/CL: 50 /5 pF
fin RL
VCC/2
12
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Parameter Measurement Information (continued)
Figure 8. Feedthrough (Switch OFF)
Figure 9. Sine-Wave Distortion
l TEXAS INSTRUMENTS
B
C
A1
4
2
13
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8 Detailed Description
8.1 Overview
This single analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G66 device can handle analog and digital signals. The device permits bidirectional transmission
of signals with amplitudes of up to 5.5 V (peak). Like all analog switches, the SN74LVC1G66 is bidirectional.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
8.2 Functional Block Diagram
Figure 10. Logic Diagram (Positive Logic)
8.3 Feature Description
The TI NanoFree package is one of TI’s smallest packages and allows customers to save board space while the
solder bumps allow for easy testing. The SN74LVC1G66 has a wide VCC range, allowing rail-to-rail operation of
signals anywhere from a 1.8-V system to a 5-V system. In addition, the control input (C Pin) is 5.5-V tolerant,
allowing higher-voltage logic to interface to the switch control system.
8.4 Device Functional Modes
Table 1. Function Table
CONTROL INPUT (C) SWITCH
L OFF
H ON
l TEXAS INSTRUMENTS
C
or
System Logic B
GND
2.5 V
A
VCC
C
To/From
System
14
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G66 can be used in any situation where an SPST switch would be used and a solid-state,
voltage-controlled version is preferred.
9.2 Typical Application
Figure 11. Typical Application Schematic
9.2.1 Design Requirements
The SN74LVC1G66 allows on and off control of analog and digital signals with a digital control signal. All input
signals should remain between 0 V and VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
For rise time and fall time specifications, see Δt/ΔvinRecommended Operating Conditions.
For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
Inputs and outputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
Load currents should not exceed ±50 mA.
3. Frequency Selection Criterion:
Maximum frequency tested is 150 MHz.
Added trace resistance/capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout.
l TEXAS INSTRUMENTS
VI
0
5
10
15
20
0 1 2 3
ron
25°C
85 C°
−40 C°
15
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Typical Application (continued)
9.2.3 Application Curve
Figure 12. ron vs VI, VCC = 2.5 V (SN74LVC1G66)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 13 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
l TEXAS INSTRUMENTS
WORST BETTER BEST
1W min.
W
2W
16
SN74LVC1G66
SCES323Q JUNE 2001REVISED MARCH 2017
www.ti.com
Product Folder Links: SN74LVC1G66
Submit Documentation Feedback Copyright © 2001–2017, Texas Instruments Incorporated
11.2 Layout Example
Figure 13. Trace Example
l TEXAS INSTRUMENTS
17
SN74LVC1G66
www.ti.com
SCES323Q –JUNE 2001REVISED MARCH 2017
Product Folder Links: SN74LVC1G66
Submit Documentation FeedbackCopyright © 2001–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Implications of Slow or Floating CMOS Inputs,SCBA004
12.2 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Apr-2022
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1G66DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (C665, C66J, C66R,
C66T)
SN74LVC1G66DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C665, C66J, C66R,
C66T)
SN74LVC1G66DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C665, C66J, C66R,
C66T)
SN74LVC1G66DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (C665, C66J, C66R)
SN74LVC1G66DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C665, C66J, C66R)
SN74LVC1G66DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (C65, C6F, C6J, C6
K, C6O, C6R, C
6T)
SN74LVC1G66DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C65, C6F, C6J, C6
K, C6O, C6R, C
6T)
SN74LVC1G66DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (C65, C6F, C6J, C6
K, C6O, C6R, C
6T)
SN74LVC1G66DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (C65, C6J, C6R, C6
T)
SN74LVC1G66DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 (C67, C6R)
SN74LVC1G66DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 (C67, C6R)
SN74LVC1G66DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C6
SN74LVC1G66DSF2 ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C6
SN74LVC1G66DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C6
SN74LVC1G66YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C6N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 28-Apr-2022
Addendum-Page 2
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G66 :
Automotive : SN74LVC1G66-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Width onhe carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O D O O D O iSDrOckethes —> User Dtrecllnn 0' Feed \i/ Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G66DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G66DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G66DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G66DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G66DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G66DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G66DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G66DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G66DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G66DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G66DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G66DSF2 SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3
SN74LVC1G66DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G66YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Mar-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G66DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G66DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G66DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G66DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G66DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74LVC1G66DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G66DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G66DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G66DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G66DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1G66DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G66DSF2 SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G66DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G66YZPR DSBGA YZP 5 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Mar-2022
Pack Materials-Page 2
MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane fit Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com
LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencfl tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'fle' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercfl des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncfl rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4207181/G
www.ti.com
PACKAGE OUTLINE
C
6X 0.25
0.15
4X
0.5
5X 0.35
0.25
2X
1
0.6 MAX
0.05
0.00
3X 0.6
0.4
0.3
B1.05
0.95 A
1.5
1.4
(0.05) TYP (0.127) TYP
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
SCALE 8.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
SYMM
1
34
6
SYMM
www.ti.com
PACKAGE OUTLINE
C
6X 0.22
0.12
6X 0.45
0.35
2X
0.7 4X
0.35
0.4 MAX
0.05
0.00
B1.05
0.95 A
1.05
0.95
(0.11) TYP
(0.1)
PIN 1 ID
4220597/B 06/2022
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
1
34
6
0.07 C B A
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
SCALE 10.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
6X (0.6)
6X (0.17)
4X (0.35)
(0.8)
(R0.05) TYP
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
4220597/B 06/2022
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
SYMM
SYMM
1
34
6
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
““‘+“‘w‘
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.6)
6X (0.15)
4X (0.35)
(0.8)
(R0.05) TYP
X2SON - 0.4 mm max heightDSF0006A
PLASTIC SMALL OUTLINE - NO LEAD
4220597/B 06/2022
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.09 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
SYMM
SYMM
1
34
6
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
‘ ‘ E g ***** $1 Li, ‘0 Q) / n ‘ --II- (£4
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1
TYP
0.5 TYP
5X 0.25
0.21
0.5
TYP
B E A
D
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
SCALE 8.000
D: Max =
E: Max =
1.418 mm, Min =
0.918 mm, Min =
1.358 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
5X ( 0.23)
(0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
5X ( 0.25) (R0.05) TYP
METAL
TYP
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
www.ti.com
PACKAGE OUTLINE
C
1.7
1.5
2X 0.5
2X 1
5X 0.3
0.1
0.6 MAX
5X 0.18
0.08
5X 0.4
0.2
0.05
0.00 TYP
5X 0.27
0.15
B1.3
1.1
A
1.7
1.5
NOTE 3
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
4220753/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1
15
PIN 1
ID AREA
34
SEATING PLANE
0.05 C
SCALE 8.000
0.1 C A B
0.05
SYMM
SYMM
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
AROUND 0.05 MIN
AROUND
5X (0.67)
5X (0.3)
(1.48)
2X (0.5)
(R0.05) TYP
(1)
4220753/B 12/2020
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
SYMM
1
34
5
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
vi“‘+\‘\‘\
www.ti.com
EXAMPLE STENCIL DESIGN
(1.48)
2X (0.5)
5X (0.67)
5X (0.3)
(R0.05) TYP
(1)
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
4220753/B 12/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
SYMM
SYMM
1
34
5
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