Datenblatt für CDx4HC405x, CDx4HCT405x von Texas Instruments

V'.‘ 1!. B X E I TEXAS INSTRUMENTS
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M –NOVEMBER 1997REVISED MAY 2019
CDx4HC405x, CDx4HCT405x High-Speed CMOS Logic Analog
Multiplexers and Demultiplexers
1
1 Features
1 Wide Analog Input Voltage Range: ±5-V Maximum
Low ON-Resistance
– 70-ΩTypical (VCC – VEE = 4.5 V)
– 40-ΩTypical (VCC – VEE = 9 V)
Low Crosstalk Between Switches
Fast Switching and Propagation Speeds
Break-Before-Make Switching
Wide Operating Temperature Range:
–55°C to +125°C
CD54HC and CD74HC Types
Operation Control Voltage: 2 V to 6 V
Switch Voltage: 0 V to 10 V
CD54HCT and CD74HCT Types
Operation Control Voltage: 4.5 V to 5.5 V
Switch Voltage: 0 V to 10 V
Direct LSTTL Input Logic Compatibility
VIL = 0.8-V Max, VIH = 2-V Min
CMOS Input Compatibility
II1 µA at VOL, VOH
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
2 Applications
Digital Radio
Signal Gating
Factory Automation
• Televisions
• Appliances
Programmable Logic Circuits
• Sensors
3 Description
The CDx4HC405x and CDx4HCT405x devices are
digitally controlled analog switches that use silicon
gate CMOS technology to achieve operating speeds
similar to LSTTL with the low-power consumption of
standard CMOS integrated circuits.
These analog multiplexers and demultiplexers control
analog voltages that may vary across the voltage
supply range (for example, VCC to VEE). They are
bidirectional switches that allow any analog input to
be used as an output and vice versa. The switches
have low ON resistance and low OFF leakages. In
addition, all these devices have an enable control
that, when high, disables all switches to their OFF
state.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
CD54HCx405xF CDIP (16) 19.56 mm × 6.92 mm
CD74HCx405xE PDIP (16) 19.30 mm × 6.35 mm
CD74HCx405xM SOIC (16) 9.90 mm × 3.91 mm
CD74HCx405xNS SOP (16) 10.30 mm × 5.30 mm
CD74HCx405xPW TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Diagram of HC4051 and HCT4051
l TEXAS INSTRUMENTS
2
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions ...................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics: HC Devices...................... 7
6.6 Electrical Characteristics: HCT Devices ................. 10
6.7 Switching Characteristics, VCC = 5 V...................... 12
6.8 Switching Characteristics, CL= 50 pF .................... 13
6.9 Analog Channel Specifications ............................... 16
6.10 Typical Characteristics.......................................... 17
7 Parameter Measurement Information ................ 18
8 Detailed Description............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagrams ..................................... 20
8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 22
9 Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Application ................................................. 23
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1 Documentation Support ........................................ 26
12.2 Related Links ........................................................ 26
12.3 Receiving Notification of Documentation Updates 26
12.4 Community Resources.......................................... 26
12.5 Trademarks........................................................... 26
12.6 Electrostatic Discharge Caution............................ 26
12.7 Glossary................................................................ 27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (February 2017) to Revision M Page
Changed Feature From: 7-ΩTypical To: 70-ΩTypical ......................................................................................................... 1
Changes from Revision K (September 2015) to Revision L Page
Changed Charged device model (CDM) value from: ±1000 V to: ±200 V ............................................................................. 6
Added Receiving Notification of Documentation Updates section ...................................................................................... 26
Changes from Revision J (February 2011) to Revision K Page
Removed Ordering Information table. .................................................................................................................................... 1
Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Detailed
Description section, Applications and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section...... 1
Added Military Disclaimer to Features list. ............................................................................................................................. 1
‘5‘ TEXAS INSTRUMENTS [[1] 33333333 E_|__|:|:|:|:I:|_ ,
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A4
A6
A
A7
A5
E
GND
VEE
VCC
A1
A0
A3
S0
S1
S2
A2
CHANNEL
IN/OUT
CHANNEL
IN/OUT
CHANNEL
IN/OUT
COM OUT/IN
ADDRESS
SELECT
3
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
www.ti.com
SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation FeedbackCopyright © 1997–2019, Texas Instruments Incorporated
5 Pin Configuration and Functions
CD54HC4051, CD54HCT4051, CD74HC4051, CD74HCT4051 J, N, D, NS, PW Packages
16-Pin CDIP, PDIP, SOIC, SO, TSSOP
Top View
Pin Functions for CDx4HCx4051B
PIN I/O DESCRIPTION
NO. NAME
1 CH A4 IN/OUT I/O Channel 4 in/out
2 CH A6 IN/OUT I/O Channel 6 in/out
3 COM OUT/IN I/O Common out/in
4 CH A7 IN/OUT I/O Channel 7 in/out
5 CH A5 IN/OUT I/O Channel 5 in/out
6 E I Enable Channels (Active Low). See Table 1.
7 VEE Negative power input
8 GND — Ground
9 S2 I Channel select 2. See Table 1.
10 S1 I Channel select 1. See Table 1.
11 S0 I Channel select 0. See Table 1.
12 CH A3 IN/OUT I/O Channel 3 in/out
13 CH A0 IN/OUT I/O Channel 0 in/out
14 CH A1 IN/OUT I/O Channel 1 in/out
15 CH A2 IN/OUT I/O Channel 2 in/out
16 VCC Positive power input
{PEN INSTRUMENTS }} 33333333 EEEEEJLEE [<><|~>
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B0
B2
BN
B3
B1
E
GND
VEE
VCC
A1
AN
A0
A3
S0
S1
A2 CHANNEL
IN/OUT
CHANNEL
IN/OUT
CHANNEL
IN/OUT
COM OUT/IN
CHANNEL
IN/OUT
COM OUT/IN
4
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
CD54HC4052, CD74HC4052, CD74HCT4052 J, N, D, NS, PW Packages
16-Pin CDIP, PDIP, SOIC, SO, TSSOP
Top View
Pin Functions for CDx4HCx4052B
PIN I/O DESCRIPTION
NO. NAME
1 CH B0 IN/OUT I/O Channel B0 in/out
2 CH B2 IN/OUT I/O Channel B2 in/out
3 COM B OUT/IN I/O B common out/in
4 CH B3 IN/OUT I/O Channel B3 in/out
5 CH B1 IN/OUT I/O Channel B1 in/out
6 E I Enable channels (Active Low). See Table 2.
7 VEE Negative power input
8 GND — Ground
9 S1 I Channel select 1. See Table 2.
10 S0 I Channel select 0. See Table 2.
11 CH A3 IN/OUT I/O Channel A3 in/out
12 CH A0 IN/OUT I/O Channel A0 in/out
13 COM A IN/OUT I/O A common out/in
14 CH A1 IN/OUT I/O Channel A1 in/out
15 CH A2 IN/OUT I/O Channel A2 in/out
16 VCC Positive power input
} _l:l__l:l:|__l:|__|_ {PEN INSTRUMENTS EEEEEJLEE [I
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B1
B0
C1
CN
C0
E
GND
VEE
VCC
AN
A1
A0
S0
S1
S2
BN
CHANNEL
IN/OUT
IN/OUT
COM OUT/IN CHANNEL
IN/OUT
COM OUT/IN
COM OUT/IN
5
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
www.ti.com
SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation FeedbackCopyright © 1997–2019, Texas Instruments Incorporated
CD54HC4053 CD74HC4053 CD74HCT4053 J, N, D, NS, PW Packages
16-Pin CDIP, PDIP, SOIC, SOP, TSSOP
TOP VIEW
Pin Functions CDx4HCx4053B
PIN I/O DESCRIPTION
NO. NAME
1 B1 IN/OUT I/O B channel Y in/out
2 B0 IN/OUT I/O B channel X in/out
3 C1 IN/OUT I/O C channel Y in/out
4 COM C OUT/IN I/O C common out/in
5 C0 IN/OUT I/O C channel X in/out
6 E I Enable channels (Active Low). See Table 3.
7 VEE Negative power input
8 GND — Ground
9 S2 I Channel select 2. See Table 3.
10 S1 I Channel select 1. See Table 3.
11 S0 I Channel select 0. See Table 3.
12 A0 IN/OUT I/O A channel X in/out
13 A1 IN/OUT I/O A channel Y in/out
14 COM A OUT/IN I/O A common out/in
15 COM B OUT/IN I/O B common out/in
16 VCC Positive power input
l TEXAS INSTRUMENTS
6
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to GND unless otherwise specified.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC – VEE DC supply voltage –0.5 10.5 V
VCC DC supply voltage –0.5 7 V
VEE DC supply voltage 0.5 –7 V
IIK DC input diode current VI< – 0.5 V or VI> VCC + 0.5 V ±20 mA
IOK DC switch diode current VI< VEE – 0.5 V or VI> VCC + 0.5 V ±20 mA
DC switch current(2) VI> VEE – 0.5 V or VI< VCC + 0.5 V ±25 mA
ICC DC VCC or ground current ±50 mA
IEE DC VEE current –20 mA
TJMAX Maximum junction temperature 150 °C
TLMAX Maximum lead temperature Soldering 10 s 300 °C
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500
V
Charged device model (CDM), per JEDEC specification JESD22-C101 or
ANSI/ESDA/JEDEC JS-002(2) ±200
(1) For maximum reliability, nominal operating conditions must be selected so that operation is always within the ranges specified in the
Recommended Operating Conditions table.
(2) All voltages referenced to GND unless otherwise specified.
(3) In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC
current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed
0.6 V (calculated from rON values shown in Electrical Characteristics: HC Devices and Electrical Characteristics: HCT Devices tables).
No VCC current will flow through RLif the switch current flows into terminal 3 on the HC and HCT4051; terminals 3 and 13 on the HC
and HCT4052; terminals 4, 14, and 15 on the HC and HCT4053.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VCC
Supply voltage range
(TA= full package temperature
range)(2)
CD54 and 74HC types 2 6 V
CD54 and 74HCT types 4.5 5.5
VCC
VEE
Supply voltage range
(TA= full package temperature range) CD54 and 74HC types, CD54 and 74HCT
types (see Figure 1)2 10 V
VEE
Supply voltage range
(TA= full package temperature
range)(3)
CD54 and 74HC types, CD54 and 74HCT
types (see Figure 2)0 –6 V
VIDC input control voltage GND VCC V
VIS Analog switch I/O voltage VEE VCC V
TAOperating temperature –55 125 °C
tr, tfInput rise and fall times
2 V 0 1000
ns4.5 V 0 500
6 V 0 400
l TEXAS INSTRUMENTS
7
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
www.ti.com
SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation FeedbackCopyright © 1997–2019, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
CD74HC4051
UNITN (PDIP) NS (SO) PW (TSSOP)
16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 49.0 83.0 107.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.3 41.2 42.4 °C/W
RθJB Junction-to-board thermal resistance 29.0 43.3 52.8 °C/W
ψJT Junction-to-top characterization parameter 21.2 9.2 4.2 °C/W
ψJB Junction-to-board characterization parameter 28.9 43.0 52.2 °C/W
6.5 Electrical Characteristics: HC Devices
PARAMETERS
TEST CONDITIONS
MIN TYP MAX UNIT
VIS
(V) VI
(V) VEE
(V) VCC
(V) TA
VIH High-level input voltage
2
25°C 1.5
V
–40°C to
+85°C 1.5
–55°C to
+125°C 1.5
4.5
25°C 3.15
–40°C to
+85°C 3.15
–55°C to
+125°C 3.15
6
25°C 4.2
–40°C to
+85°C 4.2
–55°C to
+125°C 4.2
VIL Low-level input voltage
2
25°C 0.5
V
–40°C to
+85°C 0.5
–55°C to
+125°C 0.5
4.5
25°C 1.35
–40°C to
+85°C 1.35
–55°C to
+125°C 1.35
6
25°C 1.8
–40°C to
+85°C 1.8
–55°C to
+125°C 1.8
l TEXAS INSTRUMENTS
8
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
Electrical Characteristics: HC Devices (continued)
PARAMETERS
TEST CONDITIONS
MIN TYP MAX UNIT
VIS
(V) VI
(V) VEE
(V) VCC
(V) TA
rON ON
resistance IO= 1 mA
See Figure 21
VCC or VEE
VIL
or
VIH
0 4.5
25°C 70 160
Ω
–40°C to
+85°C 200
–55°C to
+125°C 240
0 6
25°C 60 140
–40°C to
+85°C 175
–55°C to
+125°C 210
–4.5 4.5
25°C 40 120
–40°C to
+85°C 150
–55°C to
+125°C 180
VCC to VEE
0 4.5
25°C 90 180
–40°C to
+85°C 225
–55°C to
+125°C 270
0 6
25°C 80 160
–40°C to
+85°C 200
–55°C to
+125°C 240
–4.5 4.5
25°C 45 130
–40°C to
+85°C 162
–55°C to
+125°C 195
ΔrON Maximum ON resistance
between any two channels
0 4.5 25°C 10
Ω0 6 25°C 8.5
–4.5 4.5 25°C 5
l TEXAS INSTRUMENTS
9
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
www.ti.com
SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation FeedbackCopyright © 1997–2019, Texas Instruments Incorporated
Electrical Characteristics: HC Devices (continued)
PARAMETERS
TEST CONDITIONS
MIN TYP MAX UNIT
VIS
(V) VI
(V) VEE
(V) VCC
(V) TA
IIZ
Switch
ON/OFF
leakage
current
1 and 2
channels
For switch OFF:
When VIS = VCC,
VOS = VEE;
When VIS = VEE,
VOS = VCC,
For switch ON:
All applicable
combinations of
VIS and VOS
voltage levels
VIL
or
VIH
0 6
25°C ±0.1
µA
–40°C to
+85°C ±1
–55°C to
+125°C ±1
4053 –5 5
25°C ±0.1
–40°C to
+85°C ±1
–55°C to
+125°C ±1
4 channels 0 6
25°C ±0.1
–40°C to
+85°C ±1
–55°C to
+125°C ±1
4052 –5 5
25°C ±0.2
–40°C to
+85°C ±2
–55°C to
+125°C ±2
8 channels 0 6
25°C ±0.2
–40°C to
+85°C ±2
–55°C to
+125°C ±2
4051 –5 5
25°C ±0.4
–40°C to
+85°C ±4
–55°C to
+125°C ±4
IIL Control input leakage current VCC
or
GND 0 6
25°C ±0.1
µA
–40°C to
+85°C ±1
–55°C to
+125°C ±1
ICC
Quiescent
device
current IO= 0
When VIS = VEE,
VOS = VCC
VCC
or
GND
0 6
25°C 8
µA
–40°C to
+85°C 80
–55°C to
+125°C 160
When VIS = VCC,
VOS = VEE –5 5
25°C 16
–40°C to
+85°C 160
–55°C to
+125°C 320
l TEXAS INSTRUMENTS
10
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
6.6 Electrical Characteristics: HCT Devices
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VIS
(V) VI
(V) VEE
(V) VCC
(V) TA
VIH High-level input voltage 4.5
to
5.5
25°C 2
V
–40°C to
+85°C 2
–55°C to
+125°C 2
VIL Low-level input voltage 4.5
to
5.5
25°C 0.8
V
–40°C to
+85°C 0.8
–55°C to
+125°C 0.8
rON ON resistance IO= 1 mA
See Figure 6
VCC or VEE
VIL
or
VIH
0 4.5
25°C 70 160
Ω
–40°C to
+85°C 200
–55°C to
+125°C 240
–4.5 4.5
25°C 40 120
–40°C to
+85°C 150
–55°C to
+125°C 180
VCC to VEE
0 4.5
25°C 90 180
–40°C to
+85°C 225
–55°C to
+125°C 270
–4.5 4.5
25°C 45 130
–40°C to
+85°C 162
–55°C to
+125°C 195
ΔrON Maximum ON resistance
between any two channels
0 4.5 25°C 10 Ω
–4.5 4.5 25°C 5
l TEXAS INSTRUMENTS
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CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
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CD54HC4052
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CD74HC4052
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Electrical Characteristics: HCT Devices (continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VIS
(V) VI
(V) VEE
(V) VCC
(V) TA
(1) Any voltage between VCC and GND.
(2) For dual-supply systems, theoretical worst-case (VI= 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
IIZ
Switch
ON/OFF
leakage
current
1 and 2
channels
For switch OFF:
When VIS = VCC,
VOS = VEE;
When VIS = VEE,
VOS = VCC
For switch ON:
All applicable
combinations of
VIS and VOS
voltage levels
VIL
or
VIH
0 6
25°C ±0.1
µA
–40°C to
+85°C ±1
–55°C to
+125°C ±1
4053 –5 5
25°C ±0.1
–40°C to
+85°C ±1
–55°C to
+125°C ±1
4 channels 0 6
25°C ±0.1
–40°C to
+85°C ±1
–55°C to
+125°C ±1
4052 –5 5
25°C ±0.2
–40°C to
+85°C ±2
–55°C to
+125°C ±2
8 channels 0 6
25°C ±0.2
–40°C to
+85°C ±2
–55°C to
+125°C ±2
4051 –5 5
25°C ±0.4
–40°C to
+85°C ±4
–55°C to
+125°C ±4
IIL Control input leakage current See(1) 5.5
25°C ±0.1
µA
–40°C to
+85°C ±1
–55°C to
+125°C ±1
ICC
Quiescent
device
current IO= 0
When VIS = VEE,
VOS = VCC
VCC
or
GND
0 5.5
25°C 8
µA
–40°C to
+85°C 80
–55°C to
+125°C 160
When VIS = VCC,
VOS = VEE –4.5 5.5
25°C 16
µA
–40°C to
+85°C 160
–55°C to
+125°C 320
ΔICC
Additional quiescent
device current per input pin:
1 unit load(2) ΔICC(2) VCC – 2.1 4.5 to 5.5
25°C 100 360
µA
–40°C to
+85°C 450
–55°C to
+125°C 490
l TEXAS INSTRUMENTS
12
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
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,
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,
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,
CD74HCT4053
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(1) CPD is used to determine the dynamic power consumption, per package. PD= CPD VCC2fI+(CL+ CS) VCC2fO, fO= output frequency,
fI= input frequency, CL= output load capacitance, CS= switch capacitance, VCC = supply voltage
6.7 Switching Characteristics, VCC = 5 V
VCC = 5 V, TA= 25°C, input tr, tf= 6 ns
PARAMETER TEST CONDITIONS CL
(pF) MIN TYP MAX UNIT
tPHL, tPLH
Propagation delay
Switch IN to OUT
CDx4HC4051
15
4
ns
CDx4HCT4051 4
CDx4HC4052 4
CDx4HCT4052 4
CDx4HC4053 4
CDx4HCT4053 4
tPHZ, tPLZ Switch turn-off (S or E)
CDx4HC4051
15
19
ns
CDx4HCT4051 19
CDx4HC4052 21
CDx4HCT4052 21
CDx4HC4053 18
CDx4HCT4053 18
tPZH, tPZL Switch turn-on (S or E)
CDx4HC4051
15
19
ns
CDx4HCT4051 23
CDx4HC4052 27
CDx4HCT4052 29
CDx4HC4053 18
CDx4HCT4053 20
CPD Power dissipation
capacitance(1)
CDx4HC4051 50
pF
CDx4HCT4051 52
CDx4HC4052 74
CDx4HCT4052 76
CDx4HC4053 38
CDx4HCT4053 42
l TEXAS INSTRUMENTS
13
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
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CD74HCT4052
,
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,
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,
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,
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6.8 Switching Characteristics, CL= 50 pF
CL= 50 pF, input tr, tf= 6 ns
PARAMETER VEE
(V) VCC
(V) TEST CONDITIONS MIN MAX UNIT
tPLH,
tPHL
Propagation delay,
switch in to out
0 2
TA= 25°C HC 60
ns
TA= –40°C to +85°C HC 75
TA= –55°C to +125°C HC 90
0 4.5
TA= 25°C HC, HCT 12
TA= –40°C to +85°C HC, HCT 15
TA= –55°C to +125°C HC, HCT 18
0 6
TA= 25°C HC 10
TA= –40°C to +85°C HC 13
TA= –55°C to +125°C HC 15
–4.5 4.5
TA= 25°C HC, HCT 8
TA= –40°C to +85°C HC, HCT 10
TA= –55°C to +125°C HC, HCT 12
tPHZ,
tPLZ
Maximum
switch turn
OFF delay
from S or E
to switch output
4051
0 2
TA= 25°C HC 225
ns
TA= –40°C to +85°C HC 280
TA= –55°C to +125°C HC 340
0 4.5
TA= 25°C HC, HCT 45
TA= –40°C to +85°C HC, HCT 56
TA= –55°C to +125°C HC, HCT 68
0 6
TA= 25°C HC 38
TA= –40°C to +85°C HC 48
TA= –55°C to +125°C HC 57
–4.5 4.5
TA= 25°C HC, HCT 32
TA= –40°C to +85°C HC, HCT 40
TA= –55°C to +125°C HC, HCT 48
tPHZ,
tPLZ
Maximum
switch turn
OFF delay
from S or E
to switch output
4052
0 2
TA= 25°C HC 250
ns
TA= –40°C to +85°C HC 315
TA= –55°C to +125°C HC 375
0 4.5
TA= 25°C HC, HCT 50
TA= –40°C to +85°C HC, HCT 63
TA= –55°C to +125°C HC, HCT 75
0 6
TA= 25°C HC 43
TA= –40°C to +85°C HC 54
TA= –55°C to +125°C HC 65
–4.5 4.5
TA= 25°C HC 38
HCT 38
TA= –40°C to +85°C HC 48
HCT 48
TA= –55°C to +125°C HC 57
HCT 57
l TEXAS INSTRUMENTS
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CD74HC4051
CD54HCT4051
,
CD74HCT4051
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CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
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Switching Characteristics, CL= 50 pF (continued)
CL= 50 pF, input tr, tf= 6 ns
PARAMETER VEE
(V) VCC
(V) TEST CONDITIONS MIN MAX UNIT
tPHZ,
tPLZ
Maximum
switch turn
OFF delay
from S or E
to switch output
4053
0 2
TA= 25°C HC 210
ns
TA= –40°C to +85°C HC 265
TA= –55°C to +125°C HC 315
0 4.5
TA= 25°C HC 42
HCT 44
TA= –40°C to +85°C HC 53
HCT 53
TA= –55°C to +125°C HC 63
HCT 66
0 6
TA= 25°C HC 36
TA= –40°C to +85°C HC 45
TA= –55°C to +125°C HC 54
–4.5 4.5
TA= 25°C HC 29
HCT 31
TA= –40°C to +85°C HC 36
HCT 39
TA= –55°C to +125°C HC 44
HCT 47
tPZL,
tPZH
Maximum
switch turn
ON delay
from S or E
to switch output
4051
0 2
TA= 25°C HC 225
ns
TA= –40°C to +85°C HC 280
TA= –55°C to +125°C HC 340
0 4.5
TA= 25°C HC 45
HCT 55
TA= –40°C to +85°C HC 56
HCT 69
TA= –55°C to +125°C HC 68
HCT 83
0 6
TA= 25°C HC 38
TA= –40°C to +85°C HC 48
TA= –55°C to +125°C HC 57
–4.5 4.5
TA= 25°C HC 32
HCT 39
TA= –40°C to +85°C HC 40
HCT 49
TA= –55°C to +125°C HC 48
HCT 59
l TEXAS INSTRUMENTS
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CD74HC4052
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Switching Characteristics, CL= 50 pF (continued)
CL= 50 pF, input tr, tf= 6 ns
PARAMETER VEE
(V) VCC
(V) TEST CONDITIONS MIN MAX UNIT
tPZL,
tPZH
Maximum
switch turn
ON delay
from S or E
to switch output
4052
0 2
TA= 25°C HC 325
ns
TA= –40°C to +85°C HC 405
TA= –55°C to +125°C HC 490
0 4.5
TA= 25°C HC 65
HCT 70
TA= –40°C to +85°C HC 81
HCT 68
TA= –55°C to +125°C HC 98
HCT 105
0 6
TA= 25°C HC 55
TA= –40°C to +85°C HC 69
TA= –55°C to +125°C HC 83
–4.5 4.5
TA= 25°C HC 46
HCT 48
TA= –40°C to +85°C HC 58
HCT 60
TA= –55°C to +125°C HC 69
HCT 72
tPZL,
tPZH
Maximum
switch turn
ON delay
from S or E
to switch output
4053
0 2
TA= 25°C HC 220
ns
TA= –40°C to +85°C HC 275
TA= –55°C to +125°C HC 330
0 4.5
TA= 25°C HC 44
HCT 48
TA= –40°C to +85°C HC 55
HCT 60
TA= –55°C to +125°C HC 66
HCT 72
0 6
TA= 25°C HC 37
TA= –40°C to +85°C HC 47
TA= –55°C to +125°C HC 56
–4.5 4.5
TA= 25°C HC 31
HCT 34
TA= –40°C to +85°C HC 39
HCT 43
TA= –55°C to +125°C HC 47
HCT 51
CIInput (control)
capacitance
TA= 25°C HC, HCT 10
pFTA= –40°C to +85°C HC, HCT 10
TA= –55°C to +125°C HC, HCT 10
l TEXAS INSTRUMENTS cc VEE
HCT
VCC − GND (V)
VCC VEE (V)
8
6
4
2
00 2 4 6 8 10 12
HC
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CD74HCT4052
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,
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(1) Adjust input voltage to obtain 0 dBm at VOS for fIN = 1 MHz.
(2) VIS is centered at (VCC – VEE) / 2.
(3) Adjust input for 0 dBm.
6.9 Analog Channel Specifications
Typical values at TA= 25°C
PARAMETER TEST CONDITIONS HC, HCT TYPES VEE
(V) VCC
(V) TYP UNIT
CISwitch input capacitance All 5 pF
CCOM Common output capacitance
4051 25
pF4052 12
4053 8
fMAX
Minimum switch frequency
response at –3 dB
(see Figure 3,Figure 5, and
Figure 7)
See Figure 10(1)(2)
4051
–2.25 2.25
145
MHz
4052 165
4053 200
4051
–4.5 4.5
180
4052 185
4053 200
Sine-wave distortion See Figure 12 All –2.25% 2.25% 0.035%
All 4.5% 4.5% 0.018%
Switch OFF signal feedthrough
(see Figure 4,Figure 6, and
Figure 8)See Figure 14(2)(3)
4051 –2.25 2.25 –73
dB
4052 –65
4053 –64
4051 –4.5 4.5 –75
4052 –67
4053 –66
Figure 1. Recommended Operating Area as a Function of (VCC – VEE)
Figure 2. Recommended Operating Area as a Function of (VEE – GND)
*9 TEXAS INSTRUMENTS
FREQUENCY (Hz)
10K 100K 1M 10M 100M
−80
−100
VCC = 2.25 V
GND = −2.25 V
VEE = −2.25 V
RL= 50 Ω
PIN 5 TO 4
0
−40
−60
−20
VCC = 4.5 V
GND = −4.5 V
VEE = −4.5 V
RL= 50 Ω
PIN 5 TO 4
dB
dB
0
−1
−2
−3
−4
FREQUENCY (Hz)
10K 100K 1M 10M 100M
VCC = 2.25 V
GND = −2.25 V
VEE = −2.25 V
RL= 50 Ω
PIN 5 TO 4
VCC = 4.5 V
GND = −4.5 V
VEE = −4.5 V
RL= 50 Ω
PIN 5 TO 4
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
−10
−2
0
−4
−6
−8
VCC = 4.5 V
GND = −4.5 V
VEE = −4.5 V
RL= 50 Ω
PIN 4 TO 3
VCC = 2.25 V
GND = −2.25 V
VEE = −2.25 V
RL= 50 Ω
PIN 4 TO 3
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
−80
−100
VCC = 4.5 V
GND = −4.5 V
VEE = −4.5V
RL= 50 Ω
PIN 4 TO 3
VCC = 2.25 V
GND = −2.25 V
VEE = −2.25 V
RL= 50 Ω
PIN 4 TO 3
−20
0
−40
−60
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
VCC = 4.5 V
GND = −4.5 V
VEE = −4.5 V
RL= 50 Ω
PIN 12 TO 3
VCC = 2.25 V
GND = −2.25 V
VEE = −2.25 V
RL= 50 Ω
PIN 12 TO 3
−80
−100
−20
0
−40
−60
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
−4
−6
−8
−10
−2
0
VCC = 4.5 V
GND = −4.5 V
VEE = −4.5 V
RL= 50 Ω
PIN 12 TO 3
VCC = 2.25 V
GND = −2.25 V
VEE = −2.25 V
RL= 50 Ω
PIN 12 TO 3
17
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6.10 Typical Characteristics
Figure 3. Channel ON Bandwidth
(HC and HCT4051) Figure 4. Channel OFF Feedthrough
(HC and HCT4051)
Figure 5. Channel ON Bandwidth
(HC and HCT4052)
Figure 6. Channel OFF Feedthrough
(HC and HCT4052)
Figure 7. Channel ON Bandwidth
(HC and HCT4053) Figure 8. Channel OFF Feedthrough
(HC and HCT4053)
N—u—w—l— ? III— — :71 IIF J
VIS
0.1µF
VCC
VCC /2
C
VOS1
SWITCH
ON
R
R
fIS = 1MHz SINEWAVE
R = 50Ω
C = 10pF
VCC
R
VCC /2
C
SWITCH
OFF
R
INPUT
VCC /2
VOS2
dB
METER
VIS
0.1
μF
VCC
50Ω
VCC /2
10pF
VOS
SWITCH
ON
dB
METER
(FIGURE A)
(FIGURE B) HC TYPES (FIGURE C) HCT TYPES
50%
10%
90%
VCC
SWITCH INPUT
tr= 6ns tf= 6ns
tPHL
tPLH VEE
50%
10%
90%
SWITCH OUTPUT
50% 10%
90%
GND
VCC
10%
90%
50%
50%
E OR Sn
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
SWITCH ON
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
SWITCH ONSWITCH OFF
1.3 0.3
2.7
GND
3V
10%
90%
50%
50%
E OR Sn
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
SWITCH ON
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
SWITCH ONSWITCH OFF
trtf
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7 Parameter Measurement Information
Figure 9. Switch Propagation Delay, Turn-On, Turn-Off Times
Figure 10. Frequency Response Test Circuit Figure 11. Crosstalk Between Two Switches
Test Circuit
l TEXAS INSTRUMENTS v ? W*;%j‘r T8313; l"— |”— O .”_ v 1MH1 SINEWAVE
OUT
50pF
TG
IN
OUT
VCC FOR
VEE FOR
RL= 1kΩ
CL
50pF
TG
VEE FOR
VCC FOR IN
tPLZ AND tPZL
tPHZ AND tPZH
tPLZ AND tPZL
tPHZ AND tPZH
VIS
0.1µF
VCC
R
VCC /2
C
VOS
SWITCH
OFF
dB
METER
R
VCC /2
VC= VIL
fIS 1MHz SINEWAVE
R = 50Ω
C = 10pF
VCC
600Ω
VCC /2 50pF
SWITCH
ALTERNATING
SCOPE
VOS
600Ω
VCC /2
ON AND OFF
tr, tf6ns
fCONT = 1MHz
50% DUTY
CYCLE
VOS
VPP
E
VIS
10µF
VCC
10kΩ
VCC /2
50pF
VOS
SWITCH
ON
DISTORTION
METER
SINE
WAVE
VI= VIH VIS
fIS = 1kHz TO 10kHz
19
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Figure 12. ¼Sine-Wave Distortion Test Circuit Figure 13. Control to Switch Feedthrough Noise
Test Circuit
Figure 14. Switch OFF Signal Feedthrough
Figure 15. Switch ON/OFF
Propagation Delay Test Circuit
Figure 16. Switch In to Switch Out
Propagation Delay Test Circuit
l TEXAS INSTRUMENTS 9‘53??? OOOOOOO 5T
TG
TG
TG
TG
TG
TG
TG
3
A
COMMON
OUT/IN
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
11
10
9
6E
S2
S1
S0
LOGIC
LEVEL
CONVERSION
8 7
GND VEE
16
VCC
131415121524
A A A A A A A A
7 6 5 4 3 2 1 0
CHANNEL IN/OUT
TG
20
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,
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,
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,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The CDx4HCx4051 devices are a single 8-channel multiplexer having three binary control inputs, S0, S1, and S2
and an ENABLE input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8
inputs to the output.
The CDx4HCx4052 devices are a differential 4-channel multiplexer having two binary control inputs, S0and S1,
and an ENABLE input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect
the analog inputs to the outputs.
The CDx4HCx4053 devices are a triple 2-channel multiplexer having three separate digital control inputs, S0, S1,
and S2and an ENABLE input. Each control input selects one of a pair of channels that are connected in a single-
pole, double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.
8.2 Functional Block Diagrams
All inputs are protected by standard CMOS protection network.
Figure 17. CDx4HCx4051 Functional Block Diagram
l TEXAS INSTRUMENTS 0000 $ —I:|— {F —|:|~ N} —I:H> So_ —I:|—-O ,% —1:F —|:|~ W ??/ 6?
TG
TG
TG
TG
TG
TG
14
11
10
9
6E
S2
S1
S0
7
GND VEE
16
VCC
15
C COMMON
OUT/IN
4
B COMMON
OUT/IN
A COMMON
OUT/IN
LOGIC LEVEL
CONVERSION
BINARY TO
1 OF 2
DECODERS
WITH ENABLE 12132153
C C B B A A
1 0 1 0 1 0
IN/OUT
8
TG
TG
TG
TG
TG
TG
TG
TG
13 COMMON A
OUT/IN
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
10
9
6E
S1
S0
LOGIC
LEVEL
CONVERSION
16
VCC
4251
B B B B
0123
B CHANNELS IN/OUT
3COMMON B
OUT/IN
8 7
GND VEE
12141511
A A A A
3210
A CHANNELS IN/OUT
21
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CD54HCT4051
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CD54HC4052
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CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
www.ti.com
SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
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Functional Block Diagrams (continued)
All inputs are protected by standard CMOS protection network.
Figure 18. CDx4HCx4052 Functional Block Diagram
All inputs are protected by standard CMOS protection network.
Figure 19. CDx4HCx4053 Functional Block Diagram
l TEXAS INSTRUMENTS
22
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
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CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
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(1) X = Don't care
8.3 Feature Description
The CDx4HCx405x line of multiplexers and demultiplexers can accept a wide range of analog signal levels from
–5 to +5 V. They have low ON resistance, typically 70-for VCC – VEE = 4.5 V and 40-for VC– VEE = 4.5 V,
which allows for very little signal loss through the switch.
Binary address decoding on chip makes channel selection easy. When channels are changed, a break-before-
make system eliminates channel overlap.
8.4 Device Functional Modes
Table 1. CD54HC4051, CD74HC4051, CD54HCT4051, CD74HCT4051 Function Table(1)
INPUT STATES ON
CHANNEL
ENABLE S2S1S0
L L L L A0
L L L H A1
L L H L A2
L L H H A3
L H L L A4
L H L H A5
L H H L A6
L H H H A7
H X X X None
(1) X = Don't care
Table 2. CD54HC4052, CD74HC4052, CD54HCT4052, CD74HCT4052 Function Table(1)
INPUT STATES ON
CHANNELS
ENABLE S1S0
L L L A0, B0
L L H A1, B1
L H L A2, B2
L H H A3, B3
H X X None
(1) X = Don't care
Table 3. CD54HC4053, CD74HC4053, CD54HCT4053, CD74HCT4053 Function Table(1)
INPUT STATES ON
CHANNELS
ENABLE S2S1S0
L L L L C0, B0, A0
L L L H C0, B0, A1
L L H L C0, B1, A0
L L H H C0, B1, A1
L H L L C1, B0, A0
L H L H C1, B0, A1
L H H L C1, B1, A0
L H H H C1, B1, A1
H X X X None
l TEXAS INSTRUMENTS
E
S2S1S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
S2S1S0
COM
CD74HC4051
Microcontroller
k0
k1
k3
k7
k5
k4
k2
k6
Polling Input Channel Select
3.3V
VEE
GND
VCC
Pull-down resistors (10)
23
CD54HC4051
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CD74HC4051
CD54HCT4051
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CD74HCT4051
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CD54HC4052
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CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
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SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDx4HCx405x line of multiplexers and demultiplexers can be used for a wide variety of applications.
9.2 Typical Application
One application of the CD74HC4051 device is used in conjunction with a microcontroller to poll a keypad.
Figure 20 shows the basic schematic for such a polling system. The microcontroller uses the channel-select pins
to cycle through the different channels while reading the input to see if a user is pressing any of the keys. This is
a very robust setup that allows for simultaneous key presses with very little power consumption. It also uses very
few pins on the microcontroller. The down side of polling is that the microcontroller must frequently scan the keys
for a press.
Figure 20. CD74HC4051 Being Used to Help Read Button Presses on a Keypad
9.2.1 Design Requirements
These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads, so routing and load conditions must be considered to prevent ringing.
l TEXAS INSTRUMENTS 120 INPUT SIGNAL VOLTAGE 1v.
120
100
80
60
40
20
1 2 3 4 5 6 7 8 9
ON RESISTANCE ()
INPUT SIGNAL VOLTAGE (V)
VCC − VEE = 4.5V
VCC − VEE = 6V
VCC − VEE = 9V
24
CD54HC4051
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CD74HC4051
CD54HCT4051
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CD74HCT4051
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CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
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Typical Application (continued)
See Table 4 for the input loading details.
(1) Unit load is ΔICC limit specified in Specifications, for example, 360-mA MAX at 25°C.
Table 4. HCT Input Loading Table
TYPE INPUT UNIT LOADS(1)
4051, 4053 All 0.5
4052 All 0.4
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
For switch time specifications, see propagation delay times in Electrical Characteristics: HC Devices.
Inputs must not be pushed more than 0.5 V above VDD or below VEE.
For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics: HC
Devices.
2. Recommended output conditions:
Outputs must not be pulled above VDD or below VEE.
3. Input and output current consideration:
The CDx4HCx405x series of parts do not have internal current-drive circuitry, and thus cannot sink or
source current. Any current will be passed through the device.
9.2.3 Application Curve
Figure 21. Typical ON Resistance vs Input Signal Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Electrical Characteristics: HC Devices.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. A 0.1-μF and a 1-μF capacitor are commonly used in parallel. For best results, the
bypass capacitor or capacitors must be installed as close as possible to the power terminal.
l TEXAS INSTRUMENTS WORST B ETTER / /
WORST BETTER BEST
1W min.
W
2W
25
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
www.ti.com
SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
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11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change in width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
change in width upsets the transmission line characteristics, especially the distributed capacitance and self-
inductance of the trace, thus resulting in the reflection. Not all PCB traces can be straight, so they will have to
turn corners. Figure 22 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
11.2 Layout Example
Figure 22. Trace Example
l TEXAS INSTRUMENTS Am
26
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
SCHS122M NOVEMBER 1997REVISED MAY 2019
www.ti.com
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
CD54HC4051 Click here Click here Click here Click here Click here
CD74HC4051 Click here Click here Click here Click here Click here
CD54HCT4051 Click here Click here Click here Click here Click here
CD74HCT4051 Click here Click here Click here Click here Click here
CD54HC4052 Click here Click here Click here Click here Click here
CD74HC4052 Click here Click here Click here Click here Click here
CD54HCT4052 Click here Click here Click here Click here Click here
CD74HCT4052 Click here Click here Click here Click here Click here
CD54HC4053 Click here Click here Click here Click here Click here
CD74HC4053 Click here Click here Click here Click here Click here
CD54HCT4053 Click here Click here Click here Click here Click here
CD74HCT4053 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
l TEXAS INSTRUMENTS
27
CD54HC4051
,
CD74HC4051
CD54HCT4051
,
CD74HCT4051
,
CD54HC4052
,
CD74HC4052
,
CD54HCT4052
CD74HCT4052
,
CD54HC4053
,
CD74HC4053
,
CD54HCT4053
,
CD74HCT4053
www.ti.com
SCHS122M –NOVEMBER 1997REVISED MAY 2019
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052
CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
Submit Documentation FeedbackCopyright © 1997–2019, Texas Instruments Incorporated
12.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8775401EA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8775401EA
CD54HC4053F3A Samples
5962-8855601EA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8855601EA
CD54HC4052F3A Samples
5962-9065401MEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9065401ME
A
CD54HCT4051F3A
Samples
CD54HC4051F ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD54HC4051F Samples
CD54HC4051F3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD54HC4051F3A Samples
CD54HC4052F ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD54HC4052F Samples
CD54HC4052F3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8855601EA
CD54HC4052F3A Samples
CD54HC4053F ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD54HC4053F Samples
CD54HC4053F3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8775401EA
CD54HC4053F3A Samples
CD54HCT4051F3A ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-9065401ME
A
CD54HCT4051F3A
Samples
CD74HC4051E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E Samples
CD74HC4051EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E Samples
CD74HC4051M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96G3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
Addendum-Page 1
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Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC4051ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051NSRE4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4051PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4051PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4051PWTG4 ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4052E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4052E Samples
CD74HC4052M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M Samples
CD74HC4052M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC4052M Samples
CD74HC4052M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M Samples
CD74HC4052M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M Samples
CD74HC4052MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M Samples
CD74HC4052NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M Samples
CD74HC4052NSRG4 ACTIVE SO NS 16 2000 TBD Call TI Call TI -55 to 125 Samples
CD74HC4052PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 Samples
CD74HC4052PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HJ4052 Samples
CD74HC4052PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 Samples
CD74HC4052PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 Samples
CD74HC4053E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4053E Samples
Addendum-Page 2
{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC4053EE4 ACTIVE PDIP N 16 25 TBD Call TI Call TI -55 to 125 Samples
CD74HC4053M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053M96G3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 Samples
CD74HC4053PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HJ4053 Samples
CD74HC4053PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 Samples
CD74HC4053PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 Samples
CD74HCT4051E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4051E Samples
CD74HCT4051M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
Addendum-Page 3
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PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HCT4051MTG4 ACTIVE SOIC D 16 250 TBD Call TI Call TI -55 to 125 Samples
CD74HCT4052E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4052E Samples
CD74HCT4052M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M Samples
CD74HCT4052M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M Samples
CD74HCT4052M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M Samples
CD74HCT4052ME4 ACTIVE SOIC D 16 40 TBD Call TI Call TI -55 to 125 Samples
CD74HCT4052MG4 ACTIVE SOIC D 16 40 TBD Call TI Call TI -55 to 125 Samples
CD74HCT4052MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M Samples
CD74HCT4053E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4053E Samples
CD74HCT4053M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HK4053 Samples
CD74HCT4053PWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 Samples
CD74HCT4053PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 Samples
CD74HCT4053PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 4
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4051, CD54HC4052, CD54HC4053, CD54HCT4051, CD74HC4051, CD74HC4052, CD74HC4053, CD74HCT4051 :
Catalog : CD74HC4051, CD74HC4052, CD74HC4053, CD74HCT4051
Automotive : CD74HC4051-Q1, CD74HCT4051-Q1, CD74HC4051-Q1, CD74HCT4051-Q1
Enhanced Product : CD74HC4051-EP, CD74HC4051-EP
Military : CD54HC4051, CD54HC4052, CD54HC4053, CD54HCT4051
NOTE: Qualified Version Definitions:
Addendum-Page 5
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Military - QML certified for Military and Defense Applications
Addendum-Page 6
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC4051M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC4051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4051PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4051PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4052M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4052M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4052M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4052NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC4052PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4052PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4052PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC4052PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4053M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC4053PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4053PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4053PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4053PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4051M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT4052M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT4053M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT4053PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4053PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4053PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4053PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4051M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4051M96 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4051M96G3 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4051M96G4 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4051NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC4051PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4051PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4051PWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4051PWT TSSOP PW 16 250 356.0 356.0 35.0
CD74HC4052M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4052M96 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4052M96G4 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4052NSR SO NS 16 2000 356.0 356.0 35.0
CD74HC4052PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4052PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4052PWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4052PWT TSSOP PW 16 250 356.0 356.0 35.0
CD74HC4053M96 SOIC D 16 2500 364.0 364.0 27.0
Pack Materials-Page 3
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4053M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4053M96G3 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4053M96G4 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4053NSR SO NS 16 2000 356.0 356.0 35.0
CD74HC4053PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4053PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4053PWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4053PWT TSSOP PW 16 250 356.0 356.0 35.0
CD74HCT4051M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HCT4052M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HCT4053M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HCT4053PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HCT4053PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HCT4053PWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
CD74HCT4053PWT TSSOP PW 16 250 356.0 356.0 35.0
Pack Materials-Page 4
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051M D SOIC 16 40 507 8 3940 4.32
CD74HC4051ME4 D SOIC 16 40 507 8 3940 4.32
CD74HC4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4052M D SOIC 16 40 507 8 3940 4.32
CD74HC4052PW PW TSSOP 16 90 530 10.2 3600 3.5
CD74HC4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4053M D SOIC 16 40 507 8 3940 4.32
CD74HC4053ME4 D SOIC 16 40 507 8 3940 4.32
CD74HC4053MG4 D SOIC 16 40 507 8 3940 4.32
CD74HC4053PW PW TSSOP 16 90 530 10.2 3600 3.5
CD74HCT4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4051M D SOIC 16 40 507 8 3940 4.32
CD74HCT4051ME4 D SOIC 16 40 507 8 3940 4.32
CD74HCT4051MG4 D SOIC 16 40 507 8 3940 4.32
CD74HCT4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4052M D SOIC 16 40 507 8 3940 4.32
CD74HCT4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4053M D SOIC 16 40 507 8 3940 4.32
CD74HCT4053ME4 D SOIC 16 40 507 8 3940 4.32
Pack Materials-Page 5
www.ti.com
PACKAGE OUTLINE
C
8.2
7.4 TYP
14X 1.27
16X 0.51
0.35
2X
8.89
0.15 TYP
0 - 10
0.3
0.1
2.00 MAX
(1.25)
0.25
GAGE PLANE
1.05
0.55
A
10.4
10.0
NOTE 3
B5.4
5.2
NOTE 4
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
£353 RE Vi“““‘ ““““““ WEECE = Era ,MQL 1"
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
14X (1.27)
(R0.05) TYP
(7)
16X (1.85)
16X (0.6)
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
Efimfifij v¢\‘\‘\‘\
www.ti.com
EXAMPLE STENCIL DESIGN
(7)
(R0.05) TYP
16X (1.85)
16X (0.6)
14X (1.27)
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
MECHANICAL DATA D ( *"ifi O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘ fimmamfl J
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
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