Datenblatt für ML9473 von Rohm Semiconductor

Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
LAPIS Semiconductor ML9473
Semiconducto
r
FEDL9473-01
Issue Date: Aug. 21, 2008
ML9473
1/3, 1/4, 1/5 Duty 60 Output LCD Driver
1/20
GENERAL DESCRIPTION
The ML9473 is a LCD driver for dynamic display providing 3-duty-switchable pins (1/3, 1/4, 1/5 duty). It can
directly drive LCDs of up to 300, 240 and 180 segments when 1/5, 1/4 and 1/3 duty are selected respectively.
FEATURES
• Operating range
Supply voltage : 3.0 to 5.5 V
Operating temperature range : 40 to + 105C
• Segment output : 60 pins
1/5 duty : Up to 300 segments can be displayed.
1/4 duty : Up to 240 segments can be displayed.
1/3 duty : Up to 180 segments can be displayed.
• Serial transfer clock frequency : 4 MHz
• Serical interface with CPU :Through three input pins (DATA_IN, LOAD, and CLOCK)
• Built-in oscillator circuit for COMMON signals
• One-to-one correspondence between input data and output data
When input data is at “H” level : Display goes on.
When input data is at “L” level : Display goes off.
• The entire display can be turned off. (BLANK pin)
• Package options
80-pin plastic TQFP (TQFP80-P-1212-0.50-K) (Product name: ML9473TB)
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BLOCK DIAGRAM
60-Dot Segment Driver
60-Bit
Latch 5
60-Bit
Latch 4
Latch
Selector
LOAD
OSC
60
60-Bit
Latch 3
60-Bit
Latch 1
60-Bit
Latch 2
DATA_IN
CLOCK
OSC_OUT
OSC_OUT
OSC_IN
DSEL1
DSEL2
VDD
GND
BLANK
Timing Generator
60-Ch Data Selector
Common
Driver
SEG1 SEG60
VLC1
VLC2
VLC3
COM1
COM2
COM3
COM4
COM5
60 606060
60
68-Stage Shift Register
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PIN CONFIGURATION (TOP VIEW)
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
NC
V
DD
LOAD
CLOCK
DATA_IN
BLANK
DSEL2
DSEL1
OSC_OUT
OSC_OUT
OSC_IN
GND
V
LC3
V
LC2
V
LC1
COM5
COM4
COM3
COM2
COM1
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG25
SEG24
SEG23
SEG22
SEG21
80-Pin Plastic TQFP
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PIN DESCRIPTION
Symbol Type Description
OSC_IN
OSC_OUT
OSC_OUT
I
O
O
Pins for oscillation. The oscillator circuit is configured by externally connecting two
resistors and a capacitor. Make the wiring length as short as possible, because
the resistor connected to the OSC_IN pin has a higher value and the circuit is
susceptible to external noise.
DATA_IN I
Serial data input pin. The display goes on when input data is at a “H” level, and it
goes off when input data is at a “L” level.
CLOCK I
Shift clock input pin. Data from the DATA_IN pin is transferred in synchronization
with the rising edge of the shift clock.
LOAD I
Load signal input pin. Serially input data is transferred to the 60-bit latch at “H”
level of this load signal, then held at “L” level.
BLANK l Input pin that turns off all segments. The entire display goes off when “L” level is
applied to this pin. The display returns to the previous state when “H” level is
applied.
DSEL1
DSEL2 I
I
Input pins to select 1/3, 1/4, or 1/5 duty. Following shows how each duty is
selected.
DSEL2 DSEL1 Duty selected
L L 1/3
L H 1/4
H X 1/5
X: Don’t care
COM1 to
COM5 O Display output pins for LCD. These pins are connected to the COMMON side of
the LCD panel.
SEG1 to
SEG60 O Display output pins for LCD. Theses pins are connected to the SEGMENT side of
the LCD panel. For the correspondence between the output of these pins and
input data, see the “Data Structure” Section.
VLC1, VLC2,
VLC3 — Bias pins for LCD driver. Through these pins, bias voltages for the LCD are
externally supplied. The bias potential must meet the following condition:
VDD > VLC1 VLC2 > VLC3 =GND
VDD, GND — Supply voltage pin and ground pin.
Note: Built-in schmitt circuit is used for all input pins.
% ML9473 ‘ Ra OSC_OiUT
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ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
Supply Voltage VDD Ta = 25°C –0.3 to 6.5 V
Input Voltage VI Ta = 25°C –0.3 to VDD+0.3 V
Storage Temperature TSTG — –55 to 150 °C
Power Dissipation PD Ta < 105°C 650 mW
Output Current IO — –2.0 to 2.0 mA
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition Range Unit
Supply Voltage VDD V
LC3 = GND 3.0 to 5.5 V
CLOCK Frequency fCP — 0.75 to 4 MHz
Operating Temperature Ta — –40 to 105 °C
Oscillator Circuit
Parameter Symbol Applicable pin Condition Min. Max. Unit
Oscillator Resistance R0 OSC_OUT — 20 120 k
Oscillator Capacitance C0 OSC_OUT — 0.00047 0.01 F
Current Limiting Resistance R1 OSC_IN — 62 360 k
Common Signal Frequency fCOM COM1 to COM5 — 25 250 Hz
Note: See Section, “Reference Data”, for the resistor and capacitor values in the table.
RC Values in Oscillator Circuit
Parameter Symbol Applicable pin 1/3 duty 1/4 duty 1/5 duty Unit
Oscillator Resistance R0 OSC_OUT 68 51 43 k
Oscillator Capacitance C0 OSC_OUT 0.001 0.001 0.001 F
Current Limiting Resistance R1 OSC_IN 220 160 130 k
Example of an oscillator circuit:
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ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 3.0 to 5.5 V, Ta = –40 to +105°C, unless otherwise specified)
Parameter Symbol Applicable pin Condition Min. Max. Unit
“H” Input Voltage 1 VIH1 CLOCK,
OSC_IN — 0.85 VDD V
DD V
“L” Input Voltage 1 VIL1 CLOCK,
OSC_IN — GND 0.15 VDD V
“H” Input Voltage 2 VIH2 *1 — 0.8 VDD V
DD V
“L” Input Voltage 2 VIL2 *1 — GND 0.2 VDD V
“H” Input Current IIH All input pins VDD = 5.5 V, VI = VDD — 10 A
“L” Input Current IIL All input pins VDD = 5.5 V, VI = 0 V 10 — A
VOC0a I
O = 100 A VDD 1 — V
VOC1 I
O = 100 A *3 VLC1 1 VLC1 +1 V
VOC2 I
O = 100 A *4 VLC2 1 VLC2 +1 V
COMMON Output
Voltage
VOC3
COM1 - COM5 VDD = 3.0 V
IO = +100 A *5 — VLC3 +1 V
VOS0 I
O = 10 A VDD 1 — V
VOS1 I
O = 10 A *3 VLC1 1 VLC1 +1 V
VOS2 I
O = 10 A *4 VLC2 1 VLC2 +1 V
Segment Output
Voltage
VOS3
SEG1 - SEG60, VDD = 3.0 V
IO = +10 A *5 — VLC3 +1 V
Supply Current IDD V
DD V
DD = 5.0 V, no load. *2 — 0.5 mA
*1 Applies to all input pins excluding CLOCK and OSC_IN.
*2 R0 = 51 k R
1 = 160 k C
0 = 0.001 F
*3 VLC1 = 2.0V
*4 VLC2 = 1.0V
*5 VLC3 = 0V
DAT/LIN VILZ VHZ hr» 475 "m’f "1 M w CLOCK \ Vm ‘7'CL LOAD mos Im ‘ ‘ 'R m \ vm vm q Vm Wu 7 7 Wu 05c Mm
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AC Characteristics (VDD =3.0 to 5.5V, Ta = –40 to +105°C, unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Clock “H” Time tWHC — 70 — — ns
Clock “L” Time tWLC — 70 — — ns
Data Set-up Time tDS — 50 — — ns
Data Hold Time tDH — 50 — — ns
Load “H” Time tWHL — 100 — — ns
Clock-to-load Time tCL — 100 — — ns
Load-to-Clock Time tLC — 100 — — ns
Clock Rise time, Fall time tR1, tF1 — — — 50 ns
OSC_IN Input Frequency fOSC — — — 20 kHz
OSC_IN “H” Time tWHO — 20 — — s
OSC_IN “L” Time tWLO — 20 — — s
OSC_IN Rise time, Fall time tR2, tF2 — — — 100 ns
[Voltage] <7 [vdd="" terminal="" voltage]="" *="" *7="" [vlc1="" terminal="" voltage]="" '="" '=""><— [vchterminal="" voltage]="" [lime]="" [“0="">
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POWER-ON/OFF TIMING
* VLC1, VLC2 are applied when VDD is applied to external bias resistor.
INITIAL SIGNAL TIMING
* Once VDD is applied, BLANK should be applied to ‘L’ level to make all SEGMENTs off until first group of
display data is latched.
VDD
BLANK
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FUNCTIONAL DESCRIPTION
Operation
As shown in “Data Structure”, the display data consists of the data field corresponding to the output for turning
the segments on or off and the select field that selects field that selects the input block of data. Data input to the
DATA_IN pin is loaded into the 68-bit shift register, transferred to the 60-bit latch while the load signal is at “H”
level, and then output via the 60-dot segment driver.
D1 D60 DM2 C1 C3 C5
1 60 61 62 63 64 65 66 67 68
Old data New data
DATA_IN
CLOCK
LOAD
Data in
display
latch
DM1 DM3 C2 C4
Data Structure
Input data
C5C4C3C2C1DM3 DM2 DM1 D60 D59 D5D4D3D2D1
Select bit
(5 bits) Dummy bit
(3 bits) LCD display data
(60 bits)
End bit Corresponds to SEG1 Corresponds to SEG60
First bit
Correspondence between select bits and COM1 to COM5
C5 C4 C3 C2 C1 Description
0 0 0 0 1 Display data corresponding to COM1
0 0 0 1 0 Display data corresponding to COM2
0 0 1 0 0 Display data corresponding to COM3
0 1 0 0 0 Display data corresponding to COM4
1 0 0 0 0 Display data corresponding to COM5
Notes: 1. Arbitrary data can be set for the dummy bits.
2. Select bit, C1 to C5, selects 60-bit latches that correspond to COM1 to COM5, respectively.
Therefore, if “1” is set for more than one select bit, data is set to all the corresponding 60-bit latches.
Example:
If “1” is set to all the select bits C1 to C5, the display data of D1 to D60 is set to all the 60-bit latches that
correspond to COM1 to COM5.
COM1 COMZ CONE COM4 1/4 DUTY COM TIMING
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COM1 – COM5 Timing Chart:
VDD
VLC1
VLC2
VLC3
COM1
COM2
COM3
1/3 DUTY COM
TIMING
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
COM1 COMZ CONS COM4 CONE Von VLC1 sz Vma VLC1 sz Von vm 1/5 DUTY COM TIMING
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SEGn True Value Table:
LATCH1 LATCH2 LATCH3 LATCH4 LATCH5 COM1 COM2 COM3 COM4 COM5 SEGn
“H” “M2” “M2” “M2” “M2” “M1”
“L” “M1” “M1” “M1” “M1” “M2”
“M2” “H” “M2” “M2” “M2” “M1”
“M1” “L” “M1” “M1” “M1” “M2”
“M2” “M2” “H” “M2” “M2” “M1”
“M1” “M1” “L” “M1” “M1” “M2”
“M2” “M2” “M2” “H” “M2” “M1”
“M1” “M1” “M1” “L” “M1” “M2”
“M2” “M2” “M2” “M2” “H” “L”
0 0 0 0 1
“M1” “M1” “M1” “M1” “L” “H”
*Note: “H” = VDD; “M1” = VLC1; “M2” = VLC2; “L” = VLC3=GND
SE61 SE02 COM1 — COM2 7 com +7 com VLC‘ com vLCZ CONS SE61 SE62 VLC1
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Timing Chart FOR 1/3 DUTY DRIVE MODE:
N015 Gum _ 7
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Timing Chart FOR 1/4 DUTY DRIVE MODE:
VDD
VLC1
VLC2
VLC3
COM1
COM2
COM3
COM4
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
SEG1
SEG2
COM1
COM2
COM3
COM4
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Timing Chart FOR 1/5 DUTY DRIVE MODE:
VDD
VLC1
VLC2
VLC3
COM1
COM2
COM3
COM4
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
VDD
VLC1
VLC2
VLC3
SEG1
SEG2
COM1
COM2
COM3
COM4
SEG1
SEG2
COM5
COM5
VDD
VLC1
VLC2
VLC3
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APPLICATION CIRCUITS
(For 1/4 duty)
P
O
R
T
1/4 DUTY
240-SEGMENT
LCD PANEL
BIAS CIRCUIT
CPU
Open
+5V
R1
R0
C0
COM2
COM1
COM3
COM4
COM5
SEG1 SEG60DATA_IN
CLOCK
LOAD
BLANK
VDD
OSC_IN
OSC_OUT
OSC_OUT
DSEL1
DSEL2 VSS VLC1 VLC2 VLC3
ML9473
IDD [mA] IDD vs‘ VDD
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REFERENCE DATA
The data shown in this section is for reference (a metal film resistor and a film capacitor are used). Resistor and
capacitor values must be determined based on experiments.
Use the following expression to convert oscillation frequency to COMMON frame frequency (or vice versa):
f
COM=fOSC × Duty/16
f
COM : COMMON frame frequency
f
OSC : Oscillation frequency
Duty : e.g., 1/4 for 1/4 duty
For example, if fCOM=100Hz at 1/5 duty, the oscillation frequency is fOSC =8000Hz.
IDD vs. VDD
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.5 22.5 33.5 44.5 55.5 6 6.5
VDD
[V]
IDD [mA]
Ta=25°C
R0=51k
R1=160k
C0=0.001µF
1/4 duty
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fOSC---R0,C0
ML9473 Oscillator Frequency Result
VDD=3V 25°C
0.10
1.00
10.00
100.00
0 25 50 75 100 125 150
R0[kΩ]
fOSC[kHz]
0.00047µF | 62kΩ
0.00047µF | 360kΩ
0.01µF | 62kΩ
0.01µF | 360kΩ
ML9473 Oscillator Frequency Result
VDD=5.5V 25°C
0.10
1.00
10.00
100.00
0 25 50 75 100 125 150
R0[kΩ]
fOSC[kHz]
0.00047µF | 62kΩ
0.00047µF | 360kΩ
0.01µF | 62kΩ
0.01µF | 360kΩ
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PACKAGE DIMENSIONS
TQFP80-P-1212-0.50-K
Package material Epoxy resin
Lead frame material 42 alloy
Lead finish Sn-2Bi (Bi 2% typ.)
Pin treatment Plating (≥5µm)
Package weight (g) 0.40 TYP.
5
Rev. No./Last Revised 1/Feb. 1, 2008
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
(
Unit: mm
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REVISION HISTORY
Page
Document No. Date Previous
Edition Current
Edition
Description
PEDL9473-01 Dec. 15, 2006 – – Preliminary edition 1
PEDL9473-02 Jan. 15, 2007 – – Preliminary edition 2
PEDL9473-03 Jan. 9, 2008 – – Preliminary edition 3
FEDL9473-01 Aug. 21, 2008 – – Final edition 1
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